coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/volteer: pull-up GPP_D16 instead of driving it
by Caveh Jalali (Code Review) 03 Aug '20

03 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44116 ) Change subject: mb/google/volteer: pull-up GPP_D16 instead of driving it ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Gerrit-Change-Number: 44116 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 11:31:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Added GBYT4 port
by Máté Kukri (Code Review) 03 Aug '20

03 Aug '20

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43087 ) Change subject: Added GBYT4 port ...................................................................... Added GBYT4 port Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe --- A src/mainboard/unk/Kconfig A src/mainboard/unk/Kconfig.name A src/mainboard/unk/gbyt4/Kconfig A src/mainboard/unk/gbyt4/Kconfig.name A src/mainboard/unk/gbyt4/Makefile.inc A src/mainboard/unk/gbyt4/acpi/dptf.asl A src/mainboard/unk/gbyt4/acpi/ec.asl A src/mainboard/unk/gbyt4/acpi/mainboard.asl A src/mainboard/unk/gbyt4/acpi/superio.asl A src/mainboard/unk/gbyt4/acpi_tables.c A src/mainboard/unk/gbyt4/board_info.txt A src/mainboard/unk/gbyt4/cmos.layout A src/mainboard/unk/gbyt4/devicetree.cb A src/mainboard/unk/gbyt4/dsdt.asl A src/mainboard/unk/gbyt4/early_init.c A src/mainboard/unk/gbyt4/gpio.c A src/mainboard/unk/gbyt4/irqroute.c A src/mainboard/unk/gbyt4/irqroute.h A src/mainboard/unk/gbyt4/mainboard.c A src/mainboard/unk/gbyt4/romstage.c 20 files changed, 792 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43087/1 diff --git a/src/mainboard/unk/Kconfig b/src/mainboard/unk/Kconfig new file mode 100644 index 0000000..86fe2d6 --- /dev/null +++ b/src/mainboard/unk/Kconfig @@ -0,0 +1,19 @@ +if VENDOR_UNK + +choice + prompt "Mainboard model" + +source "src/mainboard/unk/*/Kconfig.name" + +endchoice + +source "src/mainboard/unk/*/Kconfig" + +config MAINBOARD_VENDOR + default "Unknown" + +config MAINBOARD_FAMILY + string + default MAINBOARD_PART_NUMBER + +endif # VENDOR_UNK diff --git a/src/mainboard/unk/Kconfig.name b/src/mainboard/unk/Kconfig.name new file mode 100644 index 0000000..a5f8bf4 --- /dev/null +++ b/src/mainboard/unk/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_UNK + bool "Unknown" diff --git a/src/mainboard/unk/gbyt4/Kconfig b/src/mainboard/unk/gbyt4/Kconfig new file mode 100644 index 0000000..b57f977 --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig @@ -0,0 +1,24 @@ +if BOARD_UNK_GBYT4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select SUPERIO_ITE_IT8728F + +config MAINBOARD_DIR + string + default "unk/gbyt4" + +config MAINBOARD_PART_NUMBER + string + default "GBYT4" + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "UNKNOWN" + +endif # BOARD_KM_GBYT4 diff --git a/src/mainboard/unk/gbyt4/Kconfig.name b/src/mainboard/unk/gbyt4/Kconfig.name new file mode 100644 index 0000000..29c4e9d --- /dev/null +++ b/src/mainboard/unk/gbyt4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_UNK_GBYT4 + bool "GBYT4" diff --git a/src/mainboard/unk/gbyt4/Makefile.inc b/src/mainboard/unk/gbyt4/Makefile.inc new file mode 100644 index 0000000..2bde1bd --- /dev/null +++ b/src/mainboard/unk/gbyt4/Makefile.inc @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += irqroute.c gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + +# Temporary shit to test MRC +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd diff --git a/src/mainboard/unk/gbyt4/acpi/dptf.asl b/src/mainboard/unk/gbyt4/acpi/dptf.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/dptf.asl diff --git a/src/mainboard/unk/gbyt4/acpi/ec.asl b/src/mainboard/unk/gbyt4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/ec.asl diff --git a/src/mainboard/unk/gbyt4/acpi/mainboard.asl b/src/mainboard/unk/gbyt4/acpi/mainboard.asl new file mode 100644 index 0000000..f343574 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 14 } + + /* Mic Detect (index 1) */ + GpioInt (Level, ActiveHigh, Exclusive, PullNone,, + "\\_SB.GPSC") { 15 } + }) +} diff --git a/src/mainboard/unk/gbyt4/acpi/superio.asl b/src/mainboard/unk/gbyt4/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi/superio.asl diff --git a/src/mainboard/unk/gbyt4/acpi_tables.c b/src/mainboard/unk/gbyt4/acpi_tables.c new file mode 100644 index 0000000..41ec5f9 --- /dev/null +++ b/src/mainboard/unk/gbyt4/acpi_tables.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include <soc/iomap.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/unk/gbyt4/board_info.txt b/src/mainboard/unk/gbyt4/board_info.txt new file mode 100644 index 0000000..5152b2a --- /dev/null +++ b/src/mainboard/unk/gbyt4/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Unknown +Board name: GBYT4 +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/unk/gbyt4/cmos.layout b/src/mainboard/unk/gbyt4/cmos.layout new file mode 100644 index 0000000..da1b185 --- /dev/null +++ b/src/mainboard/unk/gbyt4/cmos.layout @@ -0,0 +1,89 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/unk/gbyt4/devicetree.cb b/src/mainboard/unk/gbyt4/devicetree.cb new file mode 100644 index 0000000..d442127 --- /dev/null +++ b/src/mainboard/unk/gbyt4/devicetree.cb @@ -0,0 +1,94 @@ +chip soc/intel/baytrail + + register "usb2_comp_bg" = "0x4700" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + # IGD Displays + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Do not route USB ports to XHCI + register "usb_route_to_xhci" = "0" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + register "usb2_per_port_lane0" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 10.0 off end # MMC + device pci 11.0 off end # SDIO + device pci 12.0 off end # SD + device pci 13.0 on end # SATA + device pci 14.0 off end # XHCI + device pci 15.0 off end # LPE + device pci 17.0 off end # MMC45 + device pci 18.0 off end # SIO_DMA1 + device pci 18.1 off end # I2C1 + device pci 18.2 off end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 off end # I2C5 + device pci 18.6 off end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 off end # HDA + device pci 1c.0 on end # PCI-e #1 (LAN1) + device pci 1c.1 on end # PCI-e #2 (LAN2) + device pci 1c.2 on end # PCI-e #3 (LAN3) + device pci 1c.3 on end # PCI-e #4 (LAN4) + device pci 1d.0 on end # EHCI + device pci 1e.0 off end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI + + device pci 1f.0 on # LPC + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + irq 0x70 = 9 + io 0x62 = 0x0a20 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + + device pci 1f.3 on end # SMBus + end +end diff --git a/src/mainboard/unk/gbyt4/dsdt.asl b/src/mainboard/unk/gbyt4/dsdt.asl new file mode 100644 index 0000000..fb037b1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define ENABLE_TPM + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/unk/gbyt4/early_init.c b/src/mainboard/unk/gbyt4/early_init.c new file mode 100644 index 0000000..89da435 --- /dev/null +++ b/src/mainboard/unk/gbyt4/early_init.c @@ -0,0 +1,11 @@ +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 0x01) + +void bootblock_mainboard_early_init(void) +{ + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/unk/gbyt4/gpio.c b/src/mainboard/unk/gbyt4/gpio.c new file mode 100644 index 0000000..b5e68c1 --- /dev/null +++ b/src/mainboard/unk/gbyt4/gpio.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <mainboard/unk/gbyt4/irqroute.h> + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_END +}; + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(2, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_DOWN, 20K), + GPIO_FUNC(0, PULL_UP, 20K), + GPIO_FUNC(2, PULL_UP, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(0, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_DISABLE, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_FUNC(1, PULL_UP, 20K), + GPIO_FUNC(1, PULL_DOWN, 20K), + GPIO_END +}; + +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/unk/gbyt4/irqroute.c b/src/mainboard/unk/gbyt4/irqroute.c new file mode 100644 index 0000000..6fa0366 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/unk/gbyt4/irqroute.h b/src/mainboard/unk/gbyt4/irqroute.h new file mode 100644 index 0000000..7dd9ad2 --- /dev/null +++ b/src/mainboard/unk/gbyt4/irqroute.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) diff --git a/src/mainboard/unk/gbyt4/mainboard.c b/src/mainboard/unk/gbyt4/mainboard.c new file mode 100644 index 0000000..b6ccc7f --- /dev/null +++ b/src/mainboard/unk/gbyt4/mainboard.c @@ -0,0 +1,131 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG(VGA_ROM_RUN) +#include <x86emu/x86emu.h> +#endif +#include <acpi/acpi.h> +#include <arch/interrupt.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <bootstate.h> + +void mainboard_suspend_resume(void) +{ +} + +#if CONFIG(VGA_ROM_RUN) +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video BIOS default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV + * bit 2 = EFP (HDMI) + * bit 3 = LFP (eDP)* + * bit 4 = CRT2 + * bit 5 = TV2 + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0008; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +static void mainboard_init(struct device *dev) +{ + +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + return 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; +#if CONFIG(VGA_ROM_RUN) + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/unk/gbyt4/romstage.c b/src/mainboard/unk/gbyt4/romstage.c new file mode 100644 index 0000000..3ca7f77 --- /dev/null +++ b/src/mainboard/unk/gbyt4/romstage.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/mrc_wrapper.h> +#include <soc/romstage.h> + +//static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +//{ +// int ram_id = 0; +// +// /* The ram_id[2:0] pullups are too large for the default 20K +// * pulldown on the pad. Therefore, disable the internal pull resistor to +// * read high values correctly. */ +// ssus_disable_internal_pull(GPIO_SSUS_37_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_38_PAD); +// ssus_disable_internal_pull(GPIO_SSUS_39_PAD); +//#ifdef GPIO_SSUS_40_PAD_USE_PULLDOWN +// /* To prevent floating pin on shipped systems. */ +// ssus_enable_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K); +//#elif defined(GPIO_SSUS_40_PAD) +// ssus_disable_internal_pull(GPIO_SSUS_40_PAD); +//#endif +// ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); +// ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); +//#ifdef GPIO_SSUS_40_PAD +// ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3); +//#endif +// printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); +// +// if (ram_id >= total_spds) +// return NULL; +// +// /* Single channel configs */ +// if (dual_channel_config & (1 << ram_id)) +// *dual = 1; +// +// return &spd_file_content[SPD_SIZE * ram_id]; +//} + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + /*void *spd_content;*/ + int dual_channel = 0; + void *spd_file; + size_t spd_fsize; + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_fsize); + if (!spd_file) + die("SPD data not found."); + + /*spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + &dual_channel);*/ + + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mp->mainboard.dram_is_slotted = 1; + + mp->mainboard.dram_data[0] = spd_file; + if (dual_channel) + mp->mainboard.dram_data[1] = spd_file; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe Gerrit-Change-Number: 43087 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 70

Change in coreboot[master]: soc/intel/baytrail: Add MRC SMBus workaround
by Máté Kukri (Code Review) 03 Aug '20

03 Aug '20

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44092 ) Change subject: soc/intel/baytrail: Add MRC SMBus workaround ...................................................................... soc/intel/baytrail: Add MRC SMBus workaround - The Bay Trail MRC failes to read the SPDs from SMBus. - Instead the SPDs are read into a buffer and the buffer is passed to the MRC. Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- M src/soc/intel/baytrail/romstage/raminit.c 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44092/1 diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 7e6bcab..836e911 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -115,11 +115,15 @@ populate_smbios_tables(dram_data, speed, num_channels); } +#define SPD_SIZE 256 +static u8 spd_buf[SPD_SIZE * NUM_CHANNELS]; + void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; mrc_wrapper_entry_t mrc_entry; struct region_device rdev; + size_t i; /* Fill in default entries. */ mp->version = MRC_PARAMS_VER; @@ -158,8 +162,18 @@ */ mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; - if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) + if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) { + /* Workaround for broken SMBus support in the MRC */ enable_smbus(); + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + for (i = 0; i < NUM_CHANNELS; ++i) + if (mp->mainboard.spd_addrs[i]) { + i2c_eeprom_read(mp->mainboard.spd_addrs[i], + 0, SPD_SIZE, &spd_buf[SPD_SIZE * i]); + mp->mainboard.dram_data[i] = + &spd_buf[SPD_SIZE * i]; + } + } ret = mrc_entry(mp); -- To view, visit https://review.coreboot.org/c/coreboot/+/44092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193 Gerrit-Change-Number: 44092 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 20

Change in coreboot[master]: mb/**/{devicetree,overridetree}.cb: Indent with tabs
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/44113 ) Change subject: mb/**/{devicetree,overridetree}.cb: Indent with tabs ...................................................................... mb/**/{devicetree,overridetree}.cb: Indent with tabs Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/union_station/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/octopus/variants/bloog/overridetree.cb M src/mainboard/google/octopus/variants/lick/overridetree.cb M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 22 files changed, 209 insertions(+), 209 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44113/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/44113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Gerrit-Change-Number: 44113 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/**/{devicetree,overridetree}.cb: Indent with tabs
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/44113 ) Change subject: mb/**/{devicetree,overridetree}.cb: Indent with tabs ...................................................................... mb/**/{devicetree,overridetree}.cb: Indent with tabs Use tabs instead of eight spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/union_station/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb M src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb M src/mainboard/google/hatch/variants/palkia/overridetree.cb M src/mainboard/google/octopus/variants/bloog/overridetree.cb M src/mainboard/google/octopus/variants/lick/overridetree.cb M src/mainboard/google/octopus/variants/phaser/overridetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 22 files changed, 209 insertions(+), 209 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44113/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Gerrit-Change-Number: 44113 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: device/pci_device.c: Drop static device checking code
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44081 ) Change subject: device/pci_device.c: Drop static device checking code ...................................................................... device/pci_device.c: Drop static device checking code Instead, promote a more useful message to warning log level. Change-Id: I798f825690320d59d447d7fcd9cf9d53a093d05e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/pci_device.c 1 file changed, 3 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44081/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index f3cced9..4a2598a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1113,8 +1113,8 @@ if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { if (dev->enabled) { - printk(BIOS_INFO, "PCI: Static device %s not " - "found, disabling it.\n", dev_path(dev)); + printk(BIOS_WARNING, "PCI: Static device %s not found, " + "disabling it.\n", dev_path(dev)); dev->enabled = 0; } return dev; @@ -1223,8 +1223,7 @@ unsigned int max_devfn) { unsigned int devfn; - struct device *dev, **prev; - int once = 0; + struct device *dev; printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); @@ -1278,38 +1277,6 @@ post_code(0x25); /* - * Warn if any leftover static devices are are found. - * There's probably a problem in devicetree.cb. - */ - - prev = &bus->children; - for (dev = bus->children; dev; dev = dev->sibling) { - /* - * The device is only considered leftover if it is not hidden - * and it has a Vendor ID of 0 (the default for a device that - * could not be probed). - */ - if (dev->vendor != 0 || dev->hidden) { - prev = &dev->sibling; - continue; - } - - /* Unlink it from list. */ - *prev = dev->sibling; - - /* If disabled in devicetree, do not print any messages. */ - if (!dev->enabled) - continue; - - if (!once++) - printk(BIOS_WARNING, "PCI: Leftover static devices:\n"); - printk(BIOS_WARNING, "%s\n", dev_path(dev)); - } - - if (once) - printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n"); - - /* * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I798f825690320d59d447d7fcd9cf9d53a093d05e Gerrit-Change-Number: 44081 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: lib/gcov: Remove assert(0)
by Patrick Georgi (Code Review) 03 Aug '20

03 Aug '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44105 ) Change subject: lib/gcov: Remove assert(0) ...................................................................... lib/gcov: Remove assert(0) This follows CB:44047 which probably missed this because it's a custom assert macro (in code that has only recently been added to build checks). Without this change, building with gcov fails because gcc_assert(0) can be build-time verified (as introduced by CB:44044) while we need runtime failure semantics here. Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/lib/gcov-glue.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44105/1 diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 101aec9..14f3e3e 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -82,7 +82,7 @@ static long ftell(FILE *stream) { /* ftell should currently not be called */ - gcc_assert(0); + BUG(); #if CONFIG(DEBUG_COVERAGE) printk(BIOS_DEBUG, "ftell %s\n", stream->filename); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71a38631955a6a45abe90f2b9ce3a924cc5d6837 Gerrit-Change-Number: 44105 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/x230: introduce FHD variant
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 12: > Patch Set 12: > > I'm seeing an issue where zero-brightness (Backlight off) is being treated as full brightness. So instead of turning off the backlight when the lid is closed, it's set to max. > > Tested with patchset 12 on master @ e2f5fb25 Which OS did you test this on? -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 12 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kilian Neuner <cb(a)9-r.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Aleksei Kharlamov <derlafff(a)ya.ru> Gerrit-CC: Christian Herzog Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Pavel Kovalenko <su(a)nitrocaster.me> Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-CC: Tomasz Jan Góralczyk Gerrit-CC: clayton craft Gerrit-CC: slact Gerrit-Comment-Date: Mon, 03 Aug 2020 09:40:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure STACK_SIZE
by Jonathan Zhang (Code Review) 03 Aug '20

03 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44091 ) Change subject: soc/intel/xeon_sp/cpx: configure STACK_SIZE ...................................................................... soc/intel/xeon_sp/cpx: configure STACK_SIZE Before this change, we have this problem (boot log from DeltaLake config A server): Jumping to boot code at 0x00040000(0x755f6000) Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43 Linux version 4.16.18 Configure STACK_SIZE to make it larger to fix above problem. Now, we have this boot log: BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms Jumping to boot code at 0x00040000(0x752f2000) CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes Linux version 4.16.18 TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458 --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44091/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 93098e8..0df9847 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -56,6 +56,10 @@ hex default 0x80000 +config STACK_SIZE + hex + default 0x4000 + config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK -- To view, visit https://review.coreboot.org/c/coreboot/+/44091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458 Gerrit-Change-Number: 44091 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2
by Jonathan Zhang (Code Review) 03 Aug '20

03 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44049 ) Change subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 ...................................................................... soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 CPX-SP FSP is of FSP 2.2, so select PLATFORM_USES_FSP2_2. The corresponding workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implmentation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Update DCACHE_RAM_BASE. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ramstage.c M src/soc/intel/xeon_sp/cpx/romstage.c 4 files changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44049/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 8139930..031d10b 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -6,6 +6,8 @@ bool default y +select PLATFORM_USES_FSP2_2 + config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -25,18 +27,24 @@ help This option allows you to select MMIO Base Address of sideband bus. -# currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe9a0000 + default 0xfe8b0000 config DCACHE_RAM_SIZE hex - default 0x60000 + default 0x170000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x10000 + default 0xA0000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. It needs to include FSP-M stack requirement and + CB romstage stack requirement. config CPU_MICROCODE_CBFS_LOC hex @@ -57,7 +65,7 @@ config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0x70000 + default 0xA0000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 969fe25..89f18d1 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -12,7 +12,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c -ramstage-y += chip.c acpi.c cpu.c soc_util.c +ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c new file mode 100644 index 0000000..deb9030 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> + +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 9952d62..7093ec9 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,16 +13,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; - FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; - - /* - * Currently FSP for CPX does not implement user-provided StackBase/Size - * properly. When KTI link needs to be trained, inter-socket communication - * library needs quite a bit of memory for its heap usage. However, location - * is hardcoded so this workaround is needed. - */ - arch_upd->StackBase = (void *) 0xfe930000; - arch_upd->StackSize = 0x70000; /* ErrorLevel - 0 (disable) to 8 (verbose) */ m_cfg->DebugPrintLevel = 8; -- To view, visit https://review.coreboot.org/c/coreboot/+/44049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Gerrit-Change-Number: 44049 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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