coreboot-gerrit August 2020

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Change in coreboot[master]: nb/intel/ironlake: Drop `D0F0_` prefix from register names
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43731 ) Change subject: nb/intel/ironlake: Drop `D0F0_` prefix from register names ...................................................................... nb/intel/ironlake: Drop `D0F0_` prefix from register names Only some registers have such a prefix. Drop it for consistency. Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lenovo/t410/romstage.c M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c 5 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43731/1 diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 6856f5b3..445ef7a 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -32,7 +32,7 @@ early_hybrid_graphics(&igd, &peg); /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); if (peg) @@ -42,9 +42,9 @@ reg32 |= DEVEN_IGD; else /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } void mainboard_pre_raminit(void) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 34ae6c1..b68d954 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -102,7 +102,7 @@ elog_boot_notify(s3_resume); /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); early_cpu_init(); diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index cd865aa..b835736 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -5,8 +5,8 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 +#define GGC 0x52 +#define DEVEN 0x54 #define DEVEN_IGD (1 << 3) #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) @@ -16,17 +16,17 @@ #define LAC 0x87 /* Legacy Access Control */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define TOM 0xa0 +#define TOUUD 0xa2 +#define IGD_BASE 0xa4 +#define GTT_BASE 0xa8 #define TSEG 0xac /* TSEG base */ -#define D0F0_TOLUD 0xb0 +#define TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define CAPID0 0xe0 #endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4cd098c..b99e2d5 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -103,7 +103,7 @@ tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); touud = pci_read_config16(pcidev_on_root(0, 0), - D0F0_TOUUD); + TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); @@ -114,7 +114,7 @@ mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); - reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; /* Igd memory */ @@ -128,9 +128,9 @@ uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; igd_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); + pci_read_config32(pcidev_on_root(0, 0), IGD_BASE); gtt_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); + pci_read_config32(pcidev_on_root(0, 0), GTT_BASE); mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); @@ -183,7 +183,7 @@ } const struct device *const d0f0 = pcidev_on_root(0, 0); if (d0f0) - pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + pci_update_config32(d0f0, DEVEN, deven_mask, 0); } diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 0edb51c..3d27762 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1380,7 +1380,7 @@ memset(memory_map, 0, sizeof(memory_map)); if (info->uma_enabled) { - u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); + u16 t = pci_read_config16(NORTHBRIDGE, GGC); gav(t); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; @@ -1433,17 +1433,17 @@ tseg_base -= quickpath_reserved; tseg_base = ALIGN_DOWN(tseg_base, 8); - pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, tolud << 4); - pci_write_config16(NORTHBRIDGE, D0F0_TOM, tom >> 6); + pci_write_config16(NORTHBRIDGE, TOLUD, tolud << 4); + pci_write_config16(NORTHBRIDGE, TOM, tom >> 6); if (memory_remap) { - pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, remap_base >> 6); - pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (touud - 64) >> 6); + pci_write_config16(NORTHBRIDGE, REMAPBASE, remap_base >> 6); + pci_write_config16(NORTHBRIDGE, REMAPLIMIT, (touud - 64) >> 6); } - pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, touud); + pci_write_config16(NORTHBRIDGE, TOUUD, touud); if (info->uma_enabled) { - pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); - pci_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); + pci_write_config32(NORTHBRIDGE, IGD_BASE, uma_base_igd << 20); + pci_write_config32(NORTHBRIDGE, GTT_BASE, uma_base_gtt << 20); } pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); @@ -1480,7 +1480,7 @@ for (i = 0; i < 3; i++) gav(capid0[i] = - pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); + pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2))); gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); info->max_supported_clock_speed_index = (~capid0[1] & 7); @@ -1488,7 +1488,7 @@ info->uma_enabled = 0; else gav(info->uma_enabled = - pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8); + pci_read_config8(NORTHBRIDGE, DEVEN) & 8); /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ info->silicon_revision = 0; @@ -1819,7 +1819,7 @@ info->memory_reserved_for_heci_mb = reg44 & 0x3f; info->heci_uma_addr = ((u64) - ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) - + ((((u64) pci_read_config16(NORTHBRIDGE, TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; pci_read_config32(NORTHBRIDGE, DMIBAR); @@ -3665,10 +3665,10 @@ ggc = 0xb00 | ((gfxsize + 5) << 4); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); + pci_write_config16(NORTHBRIDGE, GGC, ggc | 2); u16 deven; - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 + deven = pci_read_config16(NORTHBRIDGE, DEVEN); // = 0x3 if (deven & 8) { MCHBAR8(0x2c30) = 0x20; @@ -3686,7 +3686,7 @@ MCHBAR32_AND_OR(0x30, 0, 0x40); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); + pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); write32(DEFAULT_RCBA + 0x3428, 0x1d); } @@ -3704,7 +3704,7 @@ printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); + deven = pci_read_config16(NORTHBRIDGE, DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -3832,7 +3832,7 @@ gav(0x55); - gav(pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4)); + gav(pci_read_config32(NORTHBRIDGE, CAPID0 + 4)); } /* after SPD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90 Gerrit-Change-Number: 43731 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Rename memory map variables
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43730 ) Change subject: nb/intel/ironlake: Rename memory map variables ...................................................................... nb/intel/ironlake: Rename memory map variables Uppercase variable names can be confused with register definitions. Use lowercase names instead, conforming to the coding style guidelines. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/raminit.c 2 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/43730/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index c1a2840..4cd098c 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -94,7 +94,7 @@ static void mc_read_resources(struct device *dev) { uint32_t tseg_base; - uint64_t TOUUD; + uint64_t touud; uint16_t reg16; pci_dev_read_resources(dev); @@ -102,11 +102,11 @@ mmconf_resource(dev, 0x50); tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); - TOUUD = pci_read_config16(pcidev_on_root(0, 0), + touud = pci_read_config16(pcidev_on_root(0, 0), D0F0_TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); - printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD); + printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); /* Report the memory regions */ ram_resource(dev, 3, 0, 640); @@ -134,11 +134,11 @@ mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); - if (TOUUD > 4096) - ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); + if (touud > 4096) + ram_resource(dev, 8, (4096 << 10), ((touud - 4096) << 10)); /* This memory is not DMA-capable. */ - if (TOUUD >= 8192 - 64) + if (touud >= 8192 - 64) bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); add_fixed_resources(dev, 10); diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index cfb889f..0edb51c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1364,9 +1364,9 @@ static void program_total_memory_map(struct raminfo *info) { - unsigned int TOM, TOLUD, TOUUD; + unsigned int tom, tolud, touud; unsigned int quickpath_reserved; - unsigned int REMAPbase; + unsigned int remap_base; unsigned int uma_base_igd; unsigned int uma_base_gtt; unsigned int mmio_size; @@ -1396,20 +1396,20 @@ mmio_size = get_mmio_size(); - TOM = info->total_memory_mb; - if (TOM == 4096) - TOM = 4032; - TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) - , TOUUD), 64); + tom = info->total_memory_mb; + if (tom == 4096) + tom = 4032; + touud = ALIGN_DOWN(tom - info->memory_reserved_for_heci_mb, 64); + tolud = ALIGN_DOWN(MIN(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + , touud), 64); memory_remap = 0; - if (TOUUD - TOLUD > 64) { + if (touud - tolud > 64) { memory_remap = 1; - REMAPbase = MAX(4096, TOUUD); - TOUUD = TOUUD - TOLUD + 4096; + remap_base = MAX(4096, touud); + touud = touud - tolud + 4096; } - if (TOUUD > 4096) - memory_map[2] = TOUUD | 1; + if (touud > 4096) + memory_map[2] = touud | 1; quickpath_reserved = 0; u32 t = pci_read_config32(PCI_DEV(QUICKPATH_BUS, 0, 1), 0x68); @@ -1424,22 +1424,22 @@ } if (memory_remap) - TOUUD -= quickpath_reserved; + touud -= quickpath_reserved; - uma_base_igd = TOLUD - uma_size_igd; + uma_base_igd = tolud - uma_size_igd; uma_base_gtt = uma_base_igd - uma_size_gtt; tseg_base = ALIGN_DOWN(uma_base_gtt, 64) - (CONFIG_SMM_TSEG_SIZE >> 20); if (!memory_remap) tseg_base -= quickpath_reserved; tseg_base = ALIGN_DOWN(tseg_base, 8); - pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, TOLUD << 4); - pci_write_config16(NORTHBRIDGE, D0F0_TOM, TOM >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, tolud << 4); + pci_write_config16(NORTHBRIDGE, D0F0_TOM, tom >> 6); if (memory_remap) { - pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, REMAPbase >> 6); - pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (TOUUD - 64) >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, remap_base >> 6); + pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (touud - 64) >> 6); } - pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, TOUUD); + pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, touud); if (info->uma_enabled) { pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); -- To view, visit https://review.coreboot.org/c/coreboot/+/43730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba Gerrit-Change-Number: 43730 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake/raminit.c: Drop unused define
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43729 ) Change subject: nb/intel/ironlake/raminit.c: Drop unused define ...................................................................... nb/intel/ironlake/raminit.c: Drop unused define This is the only instance of `BETTER_MEMORY_MAP` in the tree. Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/43729/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f1f8aa5..cfb889f 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1362,8 +1362,6 @@ return cfg->pci_mmio_size; } -#define BETTER_MEMORY_MAP 0 - static void program_total_memory_map(struct raminfo *info) { unsigned int TOM, TOLUD, TOUUD; -- To view, visit https://review.coreboot.org/c/coreboot/+/43729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855 Gerrit-Change-Number: 43729 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASE
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43728 ) Change subject: nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASE ...................................................................... nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASE This register does not seem to exist on Ironlake. Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/hostbridge_regs.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43728/1 diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index 087e3ef..cd865aa 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -14,8 +14,6 @@ #define PCIEXBAR 0x60 #define DMIBAR 0x68 -#define D0F0_PMBASE 0x78 - #define LAC 0x87 /* Legacy Access Control */ #define D0F0_REMAPBASE 0x98 -- To view, visit https://review.coreboot.org/c/coreboot/+/43728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536 Gerrit-Change-Number: 43728 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: nb/intel/ironlake/hostbridge_regs.h: Clean up registers
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43727 ) Change subject: nb/intel/ironlake/hostbridge_regs.h: Clean up registers ...................................................................... nb/intel/ironlake/hostbridge_regs.h: Clean up registers Remove duplicated definitios and sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/hostbridge_regs.h 1 file changed, 21 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/43727/1 diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index c5341cb..087e3ef 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -3,43 +3,32 @@ #ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ #define __IRONLAKE_HOSTBRIDGE_REGS_H__ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 - -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ - -#define D0F0_CAPID0 0xe0 - -#define TSEG 0xac /* TSEG base */ - -/* FIXME: Deduplicate these registers */ #define EPBAR 0x40 #define MCHBAR 0x48 +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) + #define PCIEXBAR 0x60 #define DMIBAR 0x68 -#define X60BAR 0x60 -#define LAC 0x87 /* Legacy Access Control */ +#define D0F0_PMBASE 0x78 -#define SKPAD 0xdc /* Scratchpad Data */ +#define LAC 0x87 /* Legacy Access Control */ + +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define TSEG 0xac /* TSEG base */ +#define D0F0_TOLUD 0xb0 + +#define D0F0_SKPD 0xdc /* Scratchpad Data */ + +#define D0F0_CAPID0 0xe0 #endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84 Gerrit-Change-Number: 43727 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Put host bridge registers into its own file
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43726 ) Change subject: nb/intel/ironlake: Put host bridge registers into its own file ...................................................................... nb/intel/ironlake: Put host bridge registers into its own file Looks like some registers are defined twice. Also, group some QPI registers together. They were scattered around and mixed with the host bridge registers, probably because other northbridges have such registers in the host bridge's PCI config space. But not Ironlake. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/ironlake/hostbridge_regs.h M src/northbridge/intel/ironlake/ironlake.h 2 files changed, 50 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43726/1 diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h new file mode 100644 index 0000000..c5341cb --- /dev/null +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __IRONLAKE_HOSTBRIDGE_REGS_H__ +#define __IRONLAKE_HOSTBRIDGE_REGS_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 + +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ + +#define D0F0_CAPID0 0xe0 + +#define TSEG 0xac /* TSEG base */ + +/* FIXME: Deduplicate these registers */ +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define X60BAR 0x60 + +#define LAC 0x87 /* Legacy Access Control */ + +#define SKPAD 0xdc /* Scratchpad Data */ + +#endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 92ee76c..5a1d52e 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -12,37 +12,6 @@ #define IOMMU_BASE4 0xfed93000 /* - * D0:F0 - */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ - -#define D0F0_CAPID0 0xe0 - -#define TSEG 0xac /* TSEG base */ - -/* * D1:F0 PEG */ #define PEG_CAP 0xa2 @@ -76,17 +45,14 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define X60BAR 0x60 +#include "hostbridge_regs.h" -#define LAC 0x87 /* Legacy Access Control */ +/* + * QPI D0:F1 + */ +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ -#define SKPAD 0xdc /* Scratchpad Data */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Gerrit-Change-Number: 43726 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/pineview/hostbridge_regs.h: Clean up registers
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43725 ) Change subject: nb/intel/pineview/hostbridge_regs.h: Clean up registers ...................................................................... nb/intel/pineview/hostbridge_regs.h: Clean up registers Sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/pineview/hostbridge_regs.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43725/1 diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h index b320b9e..506efcf 100644 --- a/src/northbridge/intel/pineview/hostbridge_regs.h +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -5,9 +5,6 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78 #define GGC 0x52 /* GMCH Graphics Control */ @@ -21,6 +18,10 @@ #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) #endif /* BOARD_DEVEN */ +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + #define PAM0 0x90 #define PAM1 0x91 #define PAM2 0x92 -- To view, visit https://review.coreboot.org/c/coreboot/+/43725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Gerrit-Change-Number: 43725 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/pineview: Put host bridge registers into its own file
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43724 ) Change subject: nb/intel/pineview: Put host bridge registers into its own file ...................................................................... nb/intel/pineview: Put host bridge registers into its own file Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/pineview/hostbridge_regs.h M src/northbridge/intel/pineview/pineview.h 2 files changed, 57 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/43724/1 diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h new file mode 100644 index 0000000..b320b9e --- /dev/null +++ b/src/northbridge/intel/pineview/hostbridge_regs.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __PINEVIEW_HOSTBRIDGE_REGS_H__ +#define __PINEVIEW_HOSTBRIDGE_REGS_H__ + +#define EPBAR 0x40 +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define DMIBAR 0x68 +#define PMIOBAR 0x78 + +#define GGC 0x52 /* GMCH Graphics Control */ + +#define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D0F0 (1 << 0) +#define DEVEN_D1F0 (1 << 1) +#define DEVEN_D2F0 (1 << 3) +#define DEVEN_D2F1 (1 << 4) + +#ifndef BOARD_DEVEN +#define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1) +#endif /* BOARD_DEVEN */ + +#define PAM0 0x90 +#define PAM1 0x91 +#define PAM2 0x92 +#define PAM3 0x93 +#define PAM4 0x94 +#define PAM5 0x95 +#define PAM6 0x96 + +#define LAC 0x97 /* Legacy Access Control */ +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define SMRAM 0x9d /* System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ + +#define TOM 0xa0 +#define TOUUD 0xa2 +#define GBSM 0xa4 +#define BGSM 0xa8 +#define TSEG 0xac +#define TOLUD 0xb0 /* Top of Low Used Memory */ +#define ERRSTS 0xc8 +#define ERRCMD 0xca +#define SMICMD 0xcc +#define SCICMD 0xce +#define CGDIS 0xd8 +#define SKPAD 0xdc /* Scratchpad Data */ +#define CAPID0 0xe0 +#define DEV0T 0xf0 +#define MSLCK 0xf4 +#define MID0 0xf8 +#define DEBUP0 0xfc + +#endif /* __PINEVIEW_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 7c41b4c..d557d22 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -19,55 +19,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#define EPBAR 0x40 -#define MCHBAR 0x48 -#define PCIEXBAR 0x60 -#define DMIBAR 0x68 -#define PMIOBAR 0x78 - -#define GGC 0x52 /* GMCH Graphics Control */ - -#define DEVEN 0x54 /* Device Enable */ -#define DEVEN_D0F0 (1 << 0) -#define DEVEN_D1F0 (1 << 1) -#define DEVEN_D2F0 (1 << 3) -#define DEVEN_D2F1 (1 << 4) - -#ifndef BOARD_DEVEN -#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 ) -#endif /* BOARD_DEVEN */ - -#define PAM0 0x90 -#define PAM1 0x91 -#define PAM2 0x92 -#define PAM3 0x93 -#define PAM4 0x94 -#define PAM5 0x95 -#define PAM6 0x96 - -#define LAC 0x97 /* Legacy Access Control */ -#define REMAPBASE 0x98 -#define REMAPLIMIT 0x9a -#define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAMC 0x9e /* Extended System Management RAM Control */ - -#define TOM 0xa0 -#define TOUUD 0xa2 -#define GBSM 0xa4 -#define BGSM 0xa8 -#define TSEG 0xac -#define TOLUD 0xb0 /* Top of Low Used Memory */ -#define ERRSTS 0xc8 -#define ERRCMD 0xca -#define SMICMD 0xcc -#define SCICMD 0xce -#define CGDIS 0xd8 -#define SKPAD 0xdc /* Scratchpad Data */ -#define CAPID0 0xe0 -#define DEV0T 0xf0 -#define MSLCK 0xf4 -#define MID0 0xf8 -#define DEBUP0 0xfc +#include "hostbridge_regs.h" /* Device 0:1.0 PCI configuration space (PCI Express) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef Gerrit-Change-Number: 43724 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/x4x/hostbridge_regs.h: Clean up registers
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43723 ) Change subject: nb/intel/x4x/hostbridge_regs.h: Clean up registers ...................................................................... nb/intel/x4x/hostbridge_regs.h: Clean up registers Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/x4x/hostbridge_regs.h 1 file changed, 23 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/43723/1 diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h index fea113f..00b496d 100644 --- a/src/northbridge/intel/x4x/hostbridge_regs.h +++ b/src/northbridge/intel/x4x/hostbridge_regs.h @@ -3,12 +3,12 @@ #ifndef __X4X_HOSTBRIDGE_REGS_H__ #define __X4X_HOSTBRIDGE_REGS_H__ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 #define D0EN (1 << 0) #define D1EN (1 << 1) #define IGD0EN (1 << 3) @@ -19,22 +19,22 @@ #define D3F3EN (1 << 9) #define PEG1EN (1 << 13) #define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_GBSM 0xa4 -#define D0F0_BGSM 0xa8 -#define D0F0_TSEG 0xac -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 #endif /* __X4X_HOSTBRIDGE_REGS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f Gerrit-Change-Number: 43723 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x: Put host bridge registers into its own file
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43722 ) Change subject: nb/intel/x4x: Put host bridge registers into its own file ...................................................................... nb/intel/x4x: Put host bridge registers into its own file Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/x4x/hostbridge_regs.h M src/northbridge/intel/x4x/x4x.h 2 files changed, 41 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/43722/1 diff --git a/src/northbridge/intel/x4x/hostbridge_regs.h b/src/northbridge/intel/x4x/hostbridge_regs.h new file mode 100644 index 0000000..fea113f --- /dev/null +++ b/src/northbridge/intel/x4x/hostbridge_regs.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_HOSTBRIDGE_REGS_H__ +#define __X4X_HOSTBRIDGE_REGS_H__ + +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +#endif /* __X4X_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 5418b41..133f31d 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -9,39 +9,7 @@ /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define D0EN (1 << 0) -#define D1EN (1 << 1) -#define IGD0EN (1 << 3) -#define IGD1EN (1 << 4) -#define D3F0EN (1 << 6) -#define D3F1EN (1 << 7) -#define D3F2EN (1 << 8) -#define D3F3EN (1 << 9) -#define PEG1EN (1 << 13) -#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN | PEG1EN) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_SMRAM 0x9d -#define D0F0_ESMRAMC 0x9e -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_TOLUD 0xb0 -#define D0F0_GBSM 0xa4 -#define D0F0_BGSM 0xa8 -#define D0F0_TSEG 0xac -#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#include "hostbridge_regs.h" /* * D1:F0 PEG -- To view, visit https://review.coreboot.org/c/coreboot/+/43722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6 Gerrit-Change-Number: 43722 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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