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Change in coreboot[master]: configs: Add a weird config for Asrock B85M Pro4
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43977 ) Change subject: configs: Add a weird config for Asrock B85M Pro4 ...................................................................... configs: Add a weird config for Asrock B85M Pro4 Please do not try to use it on real hardware. Or maybe do try. Change-Id: I8bc19a1987b405d5a654276050b00b956acbdf36 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 1 file changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/43977/1 diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 new file mode 100644 index 0000000..e4d3b2f --- /dev/null +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -0,0 +1,36 @@ +CONFIG_CCACHE=y +CONFIG_COVERAGE=y +CONFIG_UBSAN=y +CONFIG_VENDOR_ASROCK=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_CONSOLE_POST=y +# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_FINALIZE_USB_ROUTE_XHCI is not set +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_SMMSTORE=y +CONFIG_SMMSTORE_SIZE=0x30000 +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_USBDEBUG=y +CONFIG_USBDEBUG_DONGLE_FTDI_FT232H=y +CONFIG_DRIVERS_SIL_3114=y +# CONFIG_SQUELCH_EARLY_SMP is not set +CONFIG_CONSOLE_SPI_FLASH=y +CONFIG_POST_DEVICE_PCI_PCIE=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_PERIODIC_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_COVERAGE=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y +CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_EM100=y -- To view, visit https://review.coreboot.org/c/coreboot/+/43977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bc19a1987b405d5a654276050b00b956acbdf36 Gerrit-Change-Number: 43977 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/baytrail/northcluster.c: Clean up comments
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43935 ) Change subject: soc/intel/baytrail/northcluster.c: Clean up comments ...................................................................... soc/intel/baytrail/northcluster.c: Clean up comments This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/northcluster.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/43935/1 diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index f4a5c7d..d221009 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -101,14 +101,17 @@ bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, smmrrh, bmbound_k - smmrrh); - /* The BMBOUND_HI register matches register bits of 31:24 with address - * bits of 35:28. Therefore, shift register to align properly. */ + /* + * The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. + */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); - /* Reserve everything between A segment and 1MB: + /* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM -- To view, visit https://review.coreboot.org/c/coreboot/+/43935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe942a20c624e2c74801c8816616ec83851949af Gerrit-Change-Number: 43935 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in libgfxinit[master]: Add Bay Trail support
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Hello Nico Huber, Martin Roth, Patrick Georgi, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/libgfxinit/+/42359 to look at the new patch set (#36). Change subject: Add Bay Trail support ...................................................................... Add Bay Trail support Tested on Asrock Q1900M: HDMI, DVI and VGA all work correctly. Using two displays at the same time also works. UNTESTED: DisplayPort and eDP support, integrated panel support. Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma-dp_aux_request.adb M common/hw-gfx-gma-i2c.adb M common/hw-gfx-gma-panel.adb M common/hw-gfx-gma-pipe_setup.adb M common/hw-gfx-gma-pipe_setup.ads M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma-transcoder.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads A common/valleyview/Makefile.inc A common/valleyview/hw-gfx-gma-connectors.adb A common/valleyview/hw-gfx-gma-dpio.adb A common/valleyview/hw-gfx-gma-dpio.ads A common/valleyview/hw-gfx-gma-iosf.adb A common/valleyview/hw-gfx-gma-iosf.ads A common/valleyview/hw-gfx-gma-plls.adb A common/valleyview/hw-gfx-gma-plls.ads A common/valleyview/hw-gfx-gma-port_detect.adb A common/valleyview/hw-gfx-gma-power_and_clocks.adb A common/valleyview/hw-gfx-gma-power_and_clocks.ads A common/valleyview/hw-gfx-gma-soc-dp.adb A common/valleyview/hw-gfx-gma-soc-dp.ads A common/valleyview/hw-gfx-gma-soc-hdmi.adb A common/valleyview/hw-gfx-gma-soc-hdmi.ads A common/valleyview/hw-gfx-gma-soc-vga.adb A common/valleyview/hw-gfx-gma-soc-vga.ads A common/valleyview/hw-gfx-gma-soc.ads A configs/baytrail 32 files changed, 3,153 insertions(+), 226 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/59/42359/36 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Gerrit-Change-Number: 42359 Gerrit-PatchSet: 36 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] Dirty BYT SATA fix for SeaBIOS
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44088 ) Change subject: [WIP] Dirty BYT SATA fix for SeaBIOS ...................................................................... [WIP] Dirty BYT SATA fix for SeaBIOS Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/q1900m/devicetree.cb M src/mainboard/asrock/q1900m/irqroute.h M src/mainboard/asrock/q1900m/romstage.c M src/soc/intel/baytrail/sata.c 4 files changed, 80 insertions(+), 116 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44088/1 diff --git a/src/mainboard/asrock/q1900m/devicetree.cb b/src/mainboard/asrock/q1900m/devicetree.cb index afa6ed6..d64ccf7 100644 --- a/src/mainboard/asrock/q1900m/devicetree.cb +++ b/src/mainboard/asrock/q1900m/devicetree.cb @@ -29,14 +29,6 @@ register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipeb_port_select" = "3" # DP_D - # Enable PIPEA as DP_C - #register "gpu_pipea_port_select" = "2" # DP_C - #register "gpu_pipea_power_cycle_delay" = "6" # 600ms - #register "gpu_pipea_power_on_delay" = "5000" # 500ms - #register "gpu_pipea_light_on_delay" = "70" # 7ms - #register "gpu_pipea_power_off_delay" = "500" # 50ms - #register "gpu_pipea_light_off_delay" = "2000" # 200ms - # VR PS2 control register "vnn_ps2_enable" = "1" register "vcc_ps2_enable" = "1" diff --git a/src/mainboard/asrock/q1900m/irqroute.h b/src/mainboard/asrock/q1900m/irqroute.h index bc6c071..72a29c3 100644 --- a/src/mainboard/asrock/q1900m/irqroute.h +++ b/src/mainboard/asrock/q1900m/irqroute.h @@ -8,7 +8,7 @@ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ @@ -29,19 +29,3 @@ PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(H, DISABLE) - -/* CORE bank DIRQs - up to 16 supported */ -//#define TPAD_IRQ_OFFSET 0 -//#define TOUCH_IRQ_OFFSET 1 -//#define I8042_IRQ_OFFSET 2 -//#define ALS_IRQ_OFFSET 3 -/* Corresponding SCORE GPIO pins */ -//#define TPAD_IRQ_GPIO 55 -//#define TOUCH_IRQ_GPIO 72 -//#define I8042_IRQ_GPIO 101 -//#define ALS_IRQ_GPIO 70 - -/* SUS bank DIRQs - up to 16 supported */ -//#define CODEC_IRQ_OFFSET 0 -/* Corresponding SUS GPIO pins */ -//#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/asrock/q1900m/romstage.c b/src/mainboard/asrock/q1900m/romstage.c index 0d48149..1d1bec9 100644 --- a/src/mainboard/asrock/q1900m/romstage.c +++ b/src/mainboard/asrock/q1900m/romstage.c @@ -1,18 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <string.h> -#include <cbfs.h> #include <console/console.h> +#include <device/pci_ops.h> #include <device/pnp_ops.h> -#include <soc/gpio.h> +#include <device/smbus_host.h> +#include <soc/gfx.h> #include <soc/mrc_wrapper.h> +#include <soc/pci_devs.h> #include <soc/romstage.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +static uint8_t spd[2][256]; + void mainboard_fill_mrc_params(struct mrc_params *mp) { /* Enable UART */ @@ -21,33 +24,30 @@ /* I'm a bit desperate. */ printk(BIOS_EMERG, "AAAAAAAA WE LIVEEEEEEEEEE\n"); - uint8_t spd[2][256]; - uint8_t *spd_raw; - size_t spd_fsize; - mp->mainboard.dram_type = DRAM_DDR3; mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; - //mp->mainboard.weaker_odt_settings = 1; mp->mainboard.dram_is_slotted = 1; - mp->mainboard.spd_addrs[0] = 0xf0; - mp->mainboard.spd_addrs[1] = 0; // 0xf1; - spd_raw = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); + /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ + enable_smbus(); + i2c_eeprom_read(0x50, 0, sizeof(spd[0]), spd[0]); + i2c_eeprom_read(0x52, 0, sizeof(spd[1]), spd[1]); - if (!spd_raw) - die("SPD data not found."); - - memcpy(&spd[0], spd_raw, 256); - memcpy(&spd[1], spd_raw, 256); - -#if 0 + /* Patch memory type and voltage settings to make MRC happy */ spd[0][3] = 0x03; spd[1][3] = 0x03; spd[0][6] = 0x02; spd[1][6] = 0x02; -#endif - mp->mainboard.dram_data[0] = spd_raw; - mp->mainboard.dram_data[1] = spd_raw; + mp->mainboard.dram_data[0] = spd; + mp->mainboard.dram_data[1] = spd; + + const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); + + uint32_t ggc = pci_read_config32(gfx_dev, GGC); + + ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); + ggc |= GGC_GTT_SIZE_2MB | (0xf << 3); + pci_write_config32(gfx_dev, GGC, ggc); } diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 4dc3ea4..f1b9e52 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -30,24 +30,17 @@ printk(BIOS_DEBUG, "SATA: Initializing...\n"); - if (!config->sata_ahci) { - /* Set legacy or native decoding mode */ - if (config->ide_legacy_combined) { - reg8 = pci_read_config8(dev, 0x09); - reg8 &= ~0x5; - pci_write_config8(dev, 0x09, reg8); - } else { - reg8 = pci_read_config8(dev, 0x09); - reg8 |= 0x5; - pci_write_config8(dev, 0x09, reg8); - } + /* Enable BARs */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); - /* Set capabilities pointer */ - pci_write_config8(dev, 0x34, 0x70); - reg16 = pci_read_config16(dev, 0x70); - reg16 &= ~0xFF00; - pci_write_config16(dev, 0x70, reg16); - } + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); + + /* Set reg 0x94 before starting configuration */ + reg32 = 0x183; + reg32 |= (config->sata_port_map ^ 0xf) << 24; + pci_write_config32(dev, 0x94, reg32); /* Primary timing - decode enable */ reg16 = pci_read_config16(dev, 0x40); @@ -68,21 +61,59 @@ reg16 = pci_read_config16(dev, 0x92); reg16 &= ~0x003f; reg16 |= config->sata_port_map; + reg16 |= (1 << 15); /* Set ORM bit */ pci_write_config16(dev, 0x92, reg16); + /* 1.4 us delay after configuring port / enable bits */ + udelay(2); + + /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ + reg32 = pci_read_config32(dev, 0x98); + reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); + reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | + (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); + printk(BIOS_DEBUG, "%s: R_PCH_SATA_TM2 value is %#08x\n", __func__, reg32); + pci_write_config32(dev, 0x98, reg32); + + /* "Test mode registers" */ + sir_write(dev, 0x70, 0x00288301); + sir_write(dev, 0x54, 0x00000300); + sir_write(dev, 0x58, 0x50000000); + /* "OOB Detection Margin */ + sir_write(dev, 0x6c, 0x130C0603); + /* "Gasket Control" */ + sir_write(dev, 0xf4, 0); + + if (!config->sata_ahci) { + /* Set legacy or native decoding mode */ + if (config->ide_legacy_combined) { + reg8 = pci_read_config8(dev, 0x09); + reg8 &= ~0x5; + pci_write_config8(dev, 0x09, reg8); + } else { + reg8 = pci_read_config8(dev, 0x09); + reg8 |= 0x5; + pci_write_config8(dev, 0x09, reg8); + } + + /* Set capabilities pointer */ + pci_write_config8(dev, 0x34, 0x70); + reg16 = pci_read_config16(dev, 0x70); + reg16 &= ~0xFF00; + pci_write_config16(dev, 0x70, reg16); + } + if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); /* Enable CR memory space decoding */ - reg16 = pci_read_config16(dev, 0x04); - reg16 |= 0x2; - pci_write_config16(dev, 0x04, reg16); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Set capability register */ reg32 = read32(abar + 0x00); reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits - reg32 |= (0x3 << 20); // Gen3 SATA + reg32 |= (2 << 20); // Gen3 SATA write32(abar + 0x00, reg32); /* Ports enabled */ @@ -95,19 +126,19 @@ read32(abar + 0x0c); /* Set cap2 - Support devslp */ - reg32 = (1 << 5) | (1 << 4) | (1 << 3); - write32(abar + 0x24, reg32); + //reg32 = (1 << 5) | (1 << 4) | (1 << 3); + //write32(abar + 0x24, reg32); /* Set PxCMD registers */ reg32 = read32(abar + 0x118); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); + (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x118, reg32); reg32 = read32(abar + 0x198); reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); + (1 << 19) | (1 << 18) | (1 << 1)); reg32 |= 2; write32(abar + 0x198, reg32); @@ -123,19 +154,9 @@ /* TODO(shawnn): Configure IDE SATA speed regs */ } - /* 1.4 us delay after configuring port / enable bits */ - udelay(2); - - /* Enable clock for ports */ - reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; - pci_write_config32(dev, 0x94, reg32); - /* Lock SataGc register */ reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + pci_write_config32(dev, 0x9c, reg32); } static void sata_enable(struct device *dev) @@ -143,7 +164,6 @@ config_t *config = config_of(dev); u8 reg8; u16 reg16; - u32 reg32; southcluster_enable_dev(dev); @@ -155,38 +175,6 @@ reg16 |= 0x60; pci_write_config16(dev, 0x90, reg16); - /* Set reg 0x94 before starting configuration */ - reg32 = pci_read_config32(dev, 0x94); - reg32 &= (u32)(~0x1ff); - reg32 |= 0x183; - pci_write_config32(dev, 0x94, reg32); - - /* Set ORM bit */ - reg16 = pci_read_config16(dev, 0x92); - reg16 |= (1 << 15); - pci_write_config16(dev, 0x92, reg16); - - /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ - reg32 = pci_read_config32(dev, 0x98); - reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); - reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | - (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); - pci_write_config32(dev, 0x98, reg32); - - /* CMD reg - set bus master enable (BME) */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x04, reg8); - - /* "Test mode registers" */ - sir_write(dev, 0x70, 0x00288301); - sir_write(dev, 0x54, 0x00000300); - sir_write(dev, 0x58, 0x50000000); - /* "OOB Detection Margin */ - sir_write(dev, 0x6c, 0x130C0603); - /* "Gasket Control" */ - sir_write(dev, 0xf4, 0); - /* PCS - Enable requested SATA ports */ reg8 = pci_read_config8(dev, 0x92); reg8 &= ~0x03; -- To view, visit https://review.coreboot.org/c/coreboot/+/44088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5 Gerrit-Change-Number: 44088 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: baytrail RFC: native replacement for refcode.elf
by Máté Kukri (Code Review) 02 Aug '20

02 Aug '20

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43133 ) Change subject: baytrail RFC: native replacement for refcode.elf ...................................................................... baytrail RFC: native replacement for refcode.elf - This is a reverse engineered re-implementation of refcode.elf on Bay Trail - What should be done with all the magic numbers? - Is the ModPhy table considered data and can remain in a header or is it considered a blob and should be placed elsewhere? - What is the "coreboot style" of doing all the MMIO access? Change-Id: I91977c509022b0078804dc151d27296260e24bc4 --- A src/soc/intel/baytrail/include/soc/modphy.h M src/soc/intel/baytrail/refcode.c 2 files changed, 785 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43133/1 diff --git a/src/soc/intel/baytrail/include/soc/modphy.h b/src/soc/intel/baytrail/include/soc/modphy.h new file mode 100644 index 0000000..30df97a --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/modphy.h @@ -0,0 +1,575 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MODPHY_H_ +#define _MODPHY_H_ + +static u32 baytrail_modphy_table[] = { + 0x000000a6, 0x0000804c, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0x0000ffff, 0xebeb0000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002208, 0xfffffff3, 0x00000008, 0x00000000, 0x00000001, + 0x000000a3, 0x00002408, 0xfffffff3, 0x00000008, 0x00000000, 0x00000001, + 0x000000a3, 0x00002238, 0xfffffff8, 0x00000006, 0x00000000, 0x00000001, + 0x000000a3, 0x00002438, 0xfffffff8, 0x00000006, 0x00000000, 0x00000001, + 0x000000a3, 0x0000800c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000802c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000808c, 0xffffff00, 0x0000001e, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0x0000ffff, 0x22220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000810c, 0x3fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e0, 0xffff00ff, 0x00005000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xffff00ff, 0x00008000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0xffff00ff, 0x00009800, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0xff00ffff, 0x00800000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x30000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xcfffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xf3ffffff, 0x0c000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0x00ffffff, 0x55000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xffffff00, 0x00000046, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xffff00ff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000028c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000048c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000068c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000088c, 0xff00ffff, 0x00780000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000290, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000490, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000690, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000890, 0x00ffffff, 0xc0000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000294, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000494, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000694, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000894, 0x7fffffff, 0x80000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080a4, 0xffff0000, 0x0000f487, 0x00000000, 0x00000001, + 0x000000a6, 0x00000314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000714, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000914, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00008094, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008034, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008094, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008034, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008014, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008068, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e8, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008068, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008068, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e8, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008068, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e8, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008068, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e8, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008068, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008100, 0xfffffffc, 0x00000003, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a6, 0x00000314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000714, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000914, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002318, 0x0000ffff, 0x45140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0x80ffffff, 0x02000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002304, 0xff80ffff, 0x00020000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x000000a3, 0x00002518, 0x0000ffff, 0x47140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0x80ffffff, 0x04000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002504, 0xff80ffff, 0x00040000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, + 0x00000043, 0x00004100, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004200, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x000000a3, 0x00008100, 0xfffffcff, 0x00000300, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x0000ffff, 0x85850000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002290, 0x00ffffff, 0x00600000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002490, 0x00ffffff, 0x00600000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000230c, 0xff00ffff, 0x00020000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000250c, 0xff00ffff, 0x00020000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080d0, 0xffffff0f, 0x00000050, 0x00000000, 0x00000001, + 0x000000a6, 0x00000288, 0xffff00ff, 0x0000a000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000488, 0xffff00ff, 0x0000a000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000688, 0xffff00ff, 0x0000a000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000888, 0xffff00ff, 0x0000a000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000290, 0xffff00ff, 0x00005500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000290, 0xff00ffff, 0x003b0000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000490, 0xffff00ff, 0x00005500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000490, 0xff00ffff, 0x003b0000, 0x00000000, 0x00000001, + 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0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000803c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000809c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008060, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080e0, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00008100, 0xfffffffc, 0x00000003, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0x00ffffff, 0x43000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000804c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000806c, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080ec, 0xff00ffff, 0x00220000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0xfffffff0, 0x00000009, 0x00000000, 0x00000001, + 0x000000a6, 0x00000314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000714, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00000914, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002314, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a3, 0x00002514, 0xfffffff8, 0x00000007, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xfffff3ff, 0x00000c00, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xffff00ff, 0x00009500, 0x00000000, 0x00000001, + 0x000000a6, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000654, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00000854, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002254, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002454, 0xff00ffff, 0x00950000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00002000, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xfffff3ff, 0x00000400, 0x00000000, 0x00000001, + 0x000000a6, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x000080c0, 0xffffdfff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000800, 0x00000000, 0x00000001, + 0x000000a6, 0x00000244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000644, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00000844, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002244, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00002444, 0xfffff7ff, 0x00000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002318, 0x0000ffff, 0x45140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002300, 0x80ffffff, 0x02000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002304, 0xff80ffff, 0x00020000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000231c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x000000a3, 0x00002518, 0x0000ffff, 0x47140000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002500, 0x80ffffff, 0x04000000, 0x00000000, 0x00000001, + 0x000000a3, 0x00002504, 0xff80ffff, 0x00040000, 0x00000000, 0x00000001, + 0x000000a3, 0x0000251c, 0xffffff00, 0x0000000d, 0x00000000, 0x00000001, + 0x00000043, 0x00007f04, 0xffff0000, 0x00004700, 0x00000006, 0x00000007, + 0x00000043, 0x00004100, 0xfff00000, 0x0004fa01, 0x00000006, 0x00000007, + 0x00000043, 0x00004200, 0xfff00000, 0x0004ea01, 0x00000006, 0x00000007, + 0x00000043, 0x00004300, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004400, 0xfff00000, 0x00049209, 0x00000006, 0x00000007, + 0x00000043, 0x00004122, 0x00000000, 0x00004011, 0x00000006, 0x00000007, + 0x00000043, 0x00004222, 0x00000000, 0x06004015, 0x00000006, 0x00000007, + 0x00000043, 0x00004500, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004600, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004700, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x00000043, 0x00004800, 0xffff7fff, 0x00000000, 0x00000006, 0x00000007, + 0x000000a6, 0x00008014, 0xf8ffffff, 0x05000000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffe0ffff, 0x00100000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008048, 0xffffff0f, 0x00000000, 0x00000000, 0x00000001, + 0x000000a6, 0x0000801c, 0xff3fffff, 0x00c00000, 0x00000000, 0x00000001, + 0x000000a6, 0x00008040, 0xefffffff, 0x00000000, 0x00000000, 0x00000001, +}; + +#define BAYTRAIL_MODPHY_ENTRY_LEN 6 + +#define BAYTRAIL_MODPHY_REVB_OFFSET 0 +#define BAYTRAIL_MODPHY_REVB_ENTRIES 331 + +#define BAYTRAIL_MODPHY_REVA_OFFSET 1986 +#define BAYTRAIL_MODPHY_REVA_ENTRIES 218 + +#define BAYTRAIL_MODPHY_REVB_OFFSET2 3294 +#define BAYTRAIL_MODPHY_REVB_ENTRIES2 6 + +#endif diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 297ed9c..e99a9be 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -1,15 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpi.h> -#include <cbmem.h> #include <console/console.h> #include <console/streams.h> #include <cpu/x86/tsc.h> +#include <soc/ramstage.h> +#include <soc/modphy.h> + +#if 0 + +#include <acpi/acpi.h> +#include <cbmem.h> #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> - -#include <soc/ramstage.h> #include <soc/efi_wrapper.h> static void ABI_X86 send_to_console(unsigned char b) @@ -81,3 +84,206 @@ return; } } + +#endif + +static u8 mmio_read_8(u32 addr) +{ + return *(u8 *) addr; +} + +static u32 mmio_read_32(u32 addr) +{ + return *(u32 *) addr; +} + +static void mmio_write_32(u32 addr, u32 val) +{ + *(u32 *) addr = val; +} + +static void mmio_or_32(u32 addr, u32 val) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, tmp | val); +} + +static void mmio_and_32(u32 addr, u32 val) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, tmp & val); +} + +static void mmio_andor_32(u32 addr, u32 val1, u32 val2) +{ + u32 tmp; + + tmp = mmio_read_32(addr); + mmio_write_32(addr, (tmp & val1) | val2); +} + +static u8 soc_stepping_table[] = + { 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6 }; + +#define SOC_STEPPING_UNKNOWN 7 + +static int get_soc_stepping(void) +{ + u8 idx; + + idx = mmio_read_8(0xE00F8008) - 1; + return idx < ARRAY_SIZE(soc_stepping_table) ? + soc_stepping_table[idx] : SOC_STEPPING_UNKNOWN; +} + +static void program_modphy_table(u32 *table, u32 entries) +{ + u32 tmp; + + for (; entries; --entries, table += BAYTRAIL_MODPHY_ENTRY_LEN) { + mmio_write_32(0xE00000D8, table[1] & 0xffffff00); + mmio_write_32(0xE00000D0, 0xf0 + | ((table[1] & 0xff) << 8) + | ((table[0] & 0xff) << 16) + | ((table[4] & 0xff) << 24)); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, table[1] & 0xffffff00); + mmio_write_32(0xE00000D4, (tmp & table[2]) | table[3]); + mmio_write_32(0xE00000D0, 0xf0 + | ((table[1] & 0xff) << 8) + | ((table[0] & 0xff) << 16) + | ((table[5] & 0xff) << 24)); + } +} + +static inline u64 rdtsc64(void) +{ + struct tsc_struct tscval; + + tscval = rdtsc(); + return (u64) tscval.hi << 32 | (u64) tscval.lo; +} + +static void delay_usecs(u64 usecs) +{ + u64 needed_ticks, start_ticks; + + needed_ticks = usecs * tsc_freq_mhz(); + start_ticks = rdtsc64(); + while (start_ticks - rdtsc64() < needed_ticks) + ; +} + +static void do_magic_writes(void) +{ + mmio_or_32(0xFED0C698, 1); + mmio_or_32(0xFED0C698, 4); + mmio_and_32(0xFED0C698, 0xFFFFFFFD); + mmio_and_32(0xFED0C690, 0xFFFFFFF8); + delay_usecs(100); + mmio_and_32(0xFED0C698, 0xFFFFFFFE); + delay_usecs(100); + mmio_write_32(0xFED0C830, 0x78480); + delay_usecs(40); + mmio_write_32(0xFED0C830, 0x78080); + mmio_or_32(0xFED0C698, 1); + delay_usecs(100); + mmio_or_32(0xFED0C698, 2); + mmio_and_32(0xFED0C698, 0xFFFFFFFB); + mmio_andor_32(0xFED0C690, 0xFFFFFFF8, 1); +} + +static void do_magic_writes2(void) +{ + u32 tmp; + + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x10030BF0); + tmp = mmio_read_32(0x0E00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F); + + mmio_write_32(0xE00000D0, 0x11030BF0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100021F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x80000100); + + mmio_write_32(0xE00000D0, 0x110021F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100060F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); + + mmio_write_32(0xE00000D0, 0x110060F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100841F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x7FFFFFFF); + + mmio_write_32(0xE00000D0, 0x110841F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, 0x70008); + mmio_write_32(0xE00000D0, 0x110843F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x100203F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x110430); + + mmio_write_32(0xE00000D0, 0x110203F0); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D0, 0x110204F0); + tmp = mmio_read_32(0xE00000D4); + mmio_write_32(0xE00000D8, 0); + mmio_write_32(0xE00000D4, tmp | 0x40010); + mmio_write_32(0xE00000D0, 0x110204F0); +} + +/* + * Replacment for refcode.elf + */ +void baytrail_run_reference_code(void) +{ + int stepping, pollcnt; + u32 addr, val; + + printk(BIOS_DEBUG, "refcode entry\n"); + + stepping = get_soc_stepping(); + if (stepping > 1) { + printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n"); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVB_OFFSET2, + BAYTRAIL_MODPHY_REVB_ENTRIES2); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVB_OFFSET, + BAYTRAIL_MODPHY_REVB_ENTRIES); + } else { + printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n"); + program_modphy_table( + baytrail_modphy_table + BAYTRAIL_MODPHY_REVA_OFFSET, + BAYTRAIL_MODPHY_REVA_ENTRIES); + } + + addr = (mmio_read_32(0xE00F8044) & 0xFFFFFE00) + 0xB0; + mmio_or_32(addr, 8); + for (pollcnt = 0; pollcnt < 10; ++pollcnt) { + val = mmio_read_32(addr); + printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", val); + if (!(val & 8)) + break; + } + + do_magic_writes(); + do_magic_writes2(); + + printk(BIOS_DEBUG, "refcode exit\n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91977c509022b0078804dc151d27296260e24bc4 Gerrit-Change-Number: 43133 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri Gerrit-MessageType: newchange

6 41

Change in coreboot[master]: soc/intel/baytrail/northcluster.c: Rename variable
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43934 ) Change subject: soc/intel/baytrail/northcluster.c: Rename variable ...................................................................... soc/intel/baytrail/northcluster.c: Rename variable Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/northcluster.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/43934/1 diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 3cf7717..f4a5c7d 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -64,7 +64,7 @@ static void nc_read_resources(struct device *dev) { unsigned long mmconf; - unsigned long bmbound; + unsigned long bmbound_k; unsigned long bmbound_hi; unsigned long smmrrh; unsigned long smmrrl; @@ -98,8 +98,8 @@ reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); - mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, smmrrh, bmbound_k - smmrrh); /* The BMBOUND_HI register matches register bits of 31:24 with address * bits of 35:28. Therefore, shift register to align properly. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e74f342c0545f8d2a2128de4162581e5dc01e17 Gerrit-Change-Number: 43934 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/baytrail/northcluster.c: Tidy up long lines
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43933 ) Change subject: soc/intel/baytrail/northcluster.c: Tidy up long lines ...................................................................... soc/intel/baytrail/northcluster.c: Tidy up long lines These now fit in 96 characters. Tested with BUILD_TIMELESS=1, Google Ninja does not change. Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/northcluster.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/43933/1 diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index c5afa42..3cf7717 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -106,8 +106,7 @@ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) - ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); /* Reserve everything between A segment and 1MB: * @@ -115,8 +114,7 @@ * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); -- To view, visit https://review.coreboot.org/c/coreboot/+/43933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1dc0126fa4d64f75e686d68c4f70f7109c6da0 Gerrit-Change-Number: 43933 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/braswell/northcluster.c: Tidy up long lines
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43932 ) Change subject: soc/intel/braswell/northcluster.c: Tidy up long lines ...................................................................... soc/intel/braswell/northcluster.c: Tidy up long lines These now fit in 96 characters. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: I4275c81d22c03c461c184f26367db80b828033a9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43932/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 98e10fc..0b47e2f 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -91,8 +91,7 @@ /* Determine the base of the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); if (fsp_reserved_memory_area) { - fsp_res_base_k = - RES_IN_KiB((unsigned int)fsp_reserved_memory_area); + fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { /* If no FSP reserverd area */ fsp_res_base_k = tseg_base_k; @@ -128,8 +127,7 @@ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) - ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); /* * Reserve everything between A segment and 1MB: @@ -138,8 +136,7 @@ * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); /* * Reserve local APIC -- To view, visit https://review.coreboot.org/c/coreboot/+/43932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4275c81d22c03c461c184f26367db80b828033a9 Gerrit-Change-Number: 43932 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/braswell/northcluster.c: Rename macro
by Angel Pons (Code Review) 02 Aug '20

02 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43931 ) Change subject: soc/intel/braswell/northcluster.c: Rename macro ...................................................................... soc/intel/braswell/northcluster.c: Rename macro Spell `KiB` with lowercase `i`. Tested with BUILD_TIMELESS=1, Facebook fbg1701 remains identical. Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43931/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 1f310d4..98e10fc 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -51,7 +51,7 @@ * | Cacheable/Usable | * +--------------------------+ 0 */ -#define RES_IN_KIB(r) ((r) >> 10) +#define RES_IN_KiB(r) ((r) >> 10) uint32_t nc_read_top_of_low_memory(void) { @@ -85,14 +85,14 @@ /* Determine TSEG data */ smm_region(&smm_base, &smm_size); - tseg_base_k = RES_IN_KIB(smm_base); - tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); + tseg_base_k = RES_IN_KiB(smm_base); + tseg_top_k = tseg_base_k + RES_IN_KiB(smm_size); /* Determine the base of the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); if (fsp_reserved_memory_area) { fsp_res_base_k = - RES_IN_KIB((unsigned int)fsp_reserved_memory_area); + RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { /* If no FSP reserverd area */ fsp_res_base_k = tseg_base_k; @@ -100,15 +100,15 @@ /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ - base_k = RES_IN_KIB(0); - size_k = RES_IN_KIB(0xa0000) - base_k; + base_k = RES_IN_KiB(0); + size_k = RES_IN_KiB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); /* High memory -> fsp_res_base - cacheable and usable */ - base_k = RES_IN_KIB(0x100000); + base_k = RES_IN_KiB(0x100000); size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); @@ -118,7 +118,7 @@ reserved_ram_resource(dev, index++, base_k, size_k); /* TSEG TOP -> bmbound is memory backed mmio. */ - bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory()); + bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); /* @@ -126,7 +126,7 @@ * bits of 35:28. Therefore, shift register to align properly. */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); - bmbound_hi = RES_IN_KIB(bmbound_hi) << 4; + bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); @@ -144,8 +144,8 @@ /* * Reserve local APIC */ - base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE); - size_k = RES_IN_KIB(0x00100000); + base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE); + size_k = RES_IN_KiB(0x00100000); mmio_resource(dev, index++, base_k, size_k); if (CONFIG(CHROMEOS)) -- To view, visit https://review.coreboot.org/c/coreboot/+/43931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief606686ee3866a7ede75d097feb510418621fe8 Gerrit-Change-Number: 43931 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 02 Aug '20

02 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 16: > Patch Set 16: > > > Patch Set 16: > > […] > > > Do you have a strong objection against this gcc patch? And if yes, for what reason? > > If there is an alternative to patching, in my opinion that would be worthwhile, so older coreboot (crosgcc) tool chains and distribution tool chains could be used. Especially, if it’s hard to get the patch merged GCC upstream. If we skip this patch, we may be able to find a common shadow offset over multiple platforms in case of ramstage. But in other stages like romstage, bootblock where the available memory is limited and varies widely across different platforms, it is not possible to find a common shadow offset. Having this patch allows us to append the shadow buffer to the region already occupied. This is highly beneficial when using cache as ram as this way we make efficient use of the limited memory available and thus add ASan on a large number of platforms. Besides, I ran 'make what-jenkins-does' to check the boards on which ASAN_IN_ROMSTAGE can be enabled and only 19 out of 308 boards failed saying CAR area was full. These failed boards had either braswell or i440bx chipsets. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 16 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Sun, 02 Aug 2020 01:02:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020