coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/up/squared: rewrite GPIO config using intelp2m
by Maxim Polyakov (Code Review) 03 Aug '20

03 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42608 ) Change subject: mb/up/squared: rewrite GPIO config using intelp2m ...................................................................... mb/up/squared: rewrite GPIO config using intelp2m This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. This configuration was generated using the Intel Pad 2 Macro utility (intelp2m / pch-pads-parser) [1,2]. [1] https: //github.com/maxpoliak/pch-pads-parser [2] https: //review.coreboot.org/c/coreboot/+/35643 Tested with BUILD_TIMELESS=1 Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/up/squared/gpio.h 1 file changed, 878 insertions(+), 505 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42608/1 diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 894df8c..d31d094 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -2,759 +2,1132 @@ #include <soc/gpio.h> -#ifndef GPIO_H -#define GPIO_H +#ifndef CFG_GPIO_H +#define CFG_GPIO_H +#define PAD_RX(state) (state << 1) +#define PAD_TX(state) (state << 0) + +/* + * Pad configuration + * + * TODO: check HOSTSW_OWN_{NORTH, NORTHWEST, SOUTHWEST, WEST} to set DRIVER mode for the + * corresponding pads + */ static const struct pad_config gpio_table[] = { - // ******************************** - // ******* GPIO Group North ******* - // ******************************** - // *GPIO - _PAD_CFG_STRUCT(GPIO_0, 0x04000102, 0x00000000), + /* GPIO Group North */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_1, 0x04000102, 0x00000000), + /* GPIO_0 - *GPIO (DW0: 0x04000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_0, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_2, 0x04000100, 0x00000000), + /* GPIO_1 - *GPIO (DW0: 0x04000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_1, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_3, 0x04000100, 0x00000000), + /* GPIO_2 - *GPIO (DW0: 0x04000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_2, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_4, 0x04000100, 0x00000000), + /* GPIO_3 - *GPIO (DW0: 0x04000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_3, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_5, 0x44000100, 0x00000000), + /* GPIO_4 - *GPIO (DW0: 0x04000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_4, + PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_6, 0x44000201, 0x00000000), + /* GPIO_5 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_5, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_7, 0x44000201, 0x00000000), + /* GPIO_6 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_6, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_8, 0x44000201, 0x00000000), + /* GPIO_7 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_7, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_9, 0x44000201, 0x00000000), + /* GPIO_8 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_8, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_10, 0x44000201, 0x00000000), + /* GPIO_9 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_9, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_11, 0x44000201, 0x00000000), + /* GPIO_10 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_10, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_12, 0x44000201, 0x00000000), + /* GPIO_11 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_11, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_13, 0x44000100, 0x00000000), + /* GPIO_12 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_12, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_14, 0x44000102, 0x00000000), + /* GPIO_13 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_13, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_15, 0x44000102, 0x00000000), + /* GPIO_14 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_14, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_16, 0x40880102, 0x00024000), + /* GPIO_15 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_15, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_17, 0x44000201, 0x00000000), + /* GPIO_16 - *GPIO (DW0: 0x40880102, DW1: 0x00024000) */ + _PAD_CFG_STRUCT(GPIO_16, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_CFG(SCI, LEVEL, INVERT) | + PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_IOSSTATE(TxDRxE)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_18, 0x44000201, 0x00000000), + /* GPIO_17 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_17, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_19, 0x44000201, 0x00003000), + /* GPIO_18 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_18, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_20, 0x44000100, 0x00000000), + /* GPIO_19 - *GPIO (DW0: 0x44000201, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_19, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_21, 0x44000201, 0x00000000), + /* GPIO_20 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_20, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_22, 0x44000102, 0x00000000), + /* GPIO_21 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_21, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_23, 0x44000100, 0x00000000), + /* GPIO_22 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_22, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_24, 0x44000102, 0x00000000), + /* GPIO_23 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_23, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_25, 0x44000102, 0x00000000), + /* GPIO_24 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_24, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_26, 0x44000100, 0x00000000), + /* GPIO_25 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_25, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_27, 0x44000201, 0x00000000), + /* GPIO_26 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_26, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_28, 0x44000102, 0x00003000), + /* GPIO_27 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_27, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_29, 0x44000102, 0x00003000), + /* GPIO_28 - *GPIO (DW0: 0x44000102, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_28, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_30, 0x44000102, 0x00003000), + /* GPIO_29 - *GPIO (DW0: 0x44000102, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_29, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_31, 0x44000102, 0x00003000), + /* GPIO_30 - *GPIO (DW0: 0x44000102, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_30, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_32, 0x44000102, 0x00000000), + /* GPIO_31 - *GPIO (DW0: 0x44000102, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_31, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_33, 0x44000102, 0x00000000), + /* GPIO_32 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_32, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // PWM0 - _PAD_CFG_STRUCT(GPIO_34, 0x44000400, 0x00001000), + /* GPIO_33 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_33, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // PWM1 - _PAD_CFG_STRUCT(GPIO_35, 0x44000400, 0x00001000), + /* GPIO_34 - PWM0 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_34, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_36, 0x44000201, 0x00000000), + /* GPIO_35 - PWM1 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_35, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // PWM3 - _PAD_CFG_STRUCT(GPIO_37, 0x04000400, 0x00001000), + /* GPIO_36 - *GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_36, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // LPSS_UART0_RXD - _PAD_CFG_STRUCT(GPIO_38, 0x44000402, 0x00023100), + /* GPIO_37 - PWM3 (DW0: 0x04000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_37, + PAD_FUNC(NF1) | PAD_RESET(PWROK) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // LPSS_UART0_TXD - _PAD_CFG_STRUCT(GPIO_39, 0x44000400, 0x00003100), + /* GPIO_38 - LPSS_UART0_RXD (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(GPIO_38, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART0_RTS_N - _PAD_CFG_STRUCT(GPIO_40, 0x44000400, 0x00003100), + /* GPIO_39 - LPSS_UART0_TXD (DW0: 0x44000400, DW1: 0x00003100) */ + _PAD_CFG_STRUCT(GPIO_39, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART0_CTS_N - _PAD_CFG_STRUCT(GPIO_41, 0x44000402, 0x00023100), + /* GPIO_40 - LPSS_UART0_RTS_N (DW0: 0x44000400, DW1: 0x00003100) */ + _PAD_CFG_STRUCT(GPIO_40, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART1_RXD - _PAD_CFG_STRUCT(GPIO_42, 0x44000402, 0x00023100), + /* GPIO_41 - LPSS_UART0_CTS_N (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(GPIO_41, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART1_TXD - _PAD_CFG_STRUCT(GPIO_43, 0x44000400, 0x0001f100), + /* GPIO_42 - LPSS_UART1_RXD (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(GPIO_42, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART1_RTS_N - _PAD_CFG_STRUCT(GPIO_44, 0x44000400, 0x00003100), + /* GPIO_43 - LPSS_UART1_TXD (DW0: 0x44000400, DW1: 0x0001f100) */ + _PAD_CFG_STRUCT(GPIO_43, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)), - // LPSS_UART1_CTS_N - _PAD_CFG_STRUCT(GPIO_45, 0x44000402, 0x0001c100), + /* GPIO_44 - LPSS_UART1_RTS_N (DW0: 0x44000400, DW1: 0x00003100) */ + _PAD_CFG_STRUCT(GPIO_44, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_46, 0x44000100, 0x00000000), + /* GPIO_45 - LPSS_UART1_CTS_N (DW0: 0x44000402, DW1: 0x0001c100) */ + _PAD_CFG_STRUCT(GPIO_45, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_47, 0x44000100, 0x00000000), + /* GPIO_46 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_46, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_48, 0x44000100, 0x00000000), + /* GPIO_47 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_47, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_49, 0x44000100, 0x00000000), + /* GPIO_48 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_48, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_62, 0x44000100, 0x00000000), + /* GPIO_49 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_49, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_63, 0x44000100, 0x00000000), + /* GPIO_62 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_62, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_64, 0x44000100, 0x00000000), + /* GPIO_63 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_63, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_65, 0x44000100, 0x00000000), + /* GPIO_64 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_64, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_66, 0x44000100, 0x00000000), + /* GPIO_65 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_65, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_67, 0x44000100, 0x00000000), + /* GPIO_66 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_66, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_68, 0x44000100, 0x00000000), + /* GPIO_67 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_67, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_69, 0x44000100, 0x00000000), + /* GPIO_68 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_68, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_70, 0x44000100, 0x00000000), + /* GPIO_69 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_69, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_71, 0x44000100, 0x00000000), + /* GPIO_70 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_70, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_72, 0x44000200, 0x00001000), + /* GPIO_71 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_71, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_73, 0x44000200, 0x00001000), + /* GPIO_72 - *GPIO (DW0: 0x44000200, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_72, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), - // *JTAG_TCK - _PAD_CFG_STRUCT(TCK, 0x44000400, 0x00c3d000), + /* GPIO_73 - *GPIO (DW0: 0x44000200, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_73, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), - // *JTAG_TRST_N - _PAD_CFG_STRUCT(TRST_B, 0x44000400, 0x00c3d000), + /* TCK - *JTAG_TCK (DW0: 0x44000400, DW1: 0x00c3d000) */ + _PAD_CFG_STRUCT(TCK, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_TMS - _PAD_CFG_STRUCT(TMS, 0x44000400, 0x00c3f000), + /* TRST_B - *JTAG_TRST_N (DW0: 0x44000400, DW1: 0x00c3d000) */ + _PAD_CFG_STRUCT(TRST_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_TDI - _PAD_CFG_STRUCT(TDI, 0x44000400, 0x00c3f000), + /* TMS - *JTAG_TMS (DW0: 0x44000400, DW1: 0x00c3f000) */ + _PAD_CFG_STRUCT(TMS, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_PMODE - _PAD_CFG_STRUCT(CX_PMODE, 0x44000400, 0x00c3c000), + /* TDI - *JTAG_TDI (DW0: 0x44000400, DW1: 0x00c3f000) */ + _PAD_CFG_STRUCT(TDI, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_PREQ_N - _PAD_CFG_STRUCT(CX_PREQ_B, 0x44000402, 0x00c3f000), + /* CX_PMODE - *JTAG_PMODE (DW0: 0x44000400, DW1: 0x00c3c000) */ + _PAD_CFG_STRUCT(CX_PMODE, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAGX - _PAD_CFG_STRUCT(JTAGX, 0x44000402, 0x00c3f000), + /* CX_PREQ_B - *JTAG_PREQ_N (DW0: 0x44000402, DW1: 0x00c3f000) */ + _PAD_CFG_STRUCT(CX_PREQ_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_PRDY_N - _PAD_CFG_STRUCT(CX_PRDY_B, 0x44000402, 0x0043f000), + /* JTAGX - *JTAGX (DW0: 0x44000402, DW1: 0x00c3f000) */ + _PAD_CFG_STRUCT(JTAGX, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (3 << 22)), - // *JTAG_TDO - _PAD_CFG_STRUCT(TDO, 0x44000400, 0x0043f000), + /* CX_PRDY_B - *JTAG_PRDY_N (DW0: 0x44000402, DW1: 0x0043f000) */ + _PAD_CFG_STRUCT(CX_PRDY_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (1 << 22)), - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_DT, 0x44000201, 0x0003d000), + /* TDO - *JTAG_TDO (DW0: 0x44000400, DW1: 0x0043f000) */ + _PAD_CFG_STRUCT(TDO, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | (1 << 22)), - // GPIO - _PAD_CFG_STRUCT(CNV_BRI_RSP, 0x44000201, 0x00002400), + /* CNV_BRI_DT - GPIO (DW0: 0x44000201, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(CNV_BRI_DT, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // GPIO - _PAD_CFG_STRUCT(CNV_RGI_DT, 0x44000201, 0x00000000), + /* CNV_BRI_RSP - GPIO (DW0: 0x44000201, DW1: 0x00002400) */ + _PAD_CFG_STRUCT(CNV_BRI_RSP, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_1K)), - // RESERVED -// _PAD_CFG_STRUCT(CNV_RGI_RSP, 0xffffffff, 0xffffffff), + /* CNV_RGI_DT - GPIO (DW0: 0x44000201, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(CNV_RGI_DT, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), 0), - // GPIO - _PAD_CFG_STRUCT(SVID0_ALERT_B, 0x44000100, 0x00000000), + /* CNV_RGI_RSP - - RESERVED (DW0: 0xffffffff, DW1: 0xffffffff) */ - // GPIO - _PAD_CFG_STRUCT(SVID0_DATA, 0x44000100, 0x00000000), + /* SVID0_ALERT_B - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(SVID0_ALERT_B, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(SVID0_CLK, 0x44000100, 0x00000000), + /* SVID0_DATA - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(SVID0_DATA, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + /* SVID0_CLK - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(SVID0_CLK, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // ************************************ - // ******* GPIO Group NorthWest ******* - // ************************************ - // *DDI0_DDC_SDA - _PAD_CFG_STRUCT(GPIO_187, 0x44000400, 0x0001f000), - // *DDI0_DDC_SCL - _PAD_CFG_STRUCT(GPIO_188, 0x44000400, 0x0001f000), + /* GPIO Group North-West */ - // *DDI1_DDC_SDA - _PAD_CFG_STRUCT(GPIO_189, 0x44000400, 0x00002c00), + /* GPIO_187 - *DDI0_DDC_SDA (DW0: 0x44000400, DW1: 0x0001f000) */ + _PAD_CFG_STRUCT(GPIO_187, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0)), - // *DDI1_DDC_SCL - _PAD_CFG_STRUCT(GPIO_190, 0x44000400, 0x00002c00), + /* GPIO_188 - *DDI0_DDC_SCL (DW0: 0x44000400, DW1: 0x0001f000) */ + _PAD_CFG_STRUCT(GPIO_188, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0)), - // GPIO - _PAD_CFG_STRUCT(GPIO_191, 0x44000100, 0x00000000), + /* GPIO_189 - *DDI1_DDC_SDA (DW0: 0x44000400, DW1: 0x00002c00) */ + _PAD_CFG_STRUCT(GPIO_189, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_2K)), - // GPIO - _PAD_CFG_STRUCT(GPIO_192, 0x44000100, 0x00000000), + /* GPIO_190 - *DDI1_DDC_SCL (DW0: 0x44000400, DW1: 0x00002c00) */ + _PAD_CFG_STRUCT(GPIO_190, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_2K)), - // *PNL0_VDDEN - _PAD_CFG_STRUCT(GPIO_193, 0x44000400, 0x00005000), + /* GPIO_191 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_191, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *PNL0_BKLTEN - _PAD_CFG_STRUCT(GPIO_194, 0x44000400, 0x00005000), + /* GPIO_192 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_192, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *PNL0_BKLTCTL - _PAD_CFG_STRUCT(GPIO_195, 0x44000400, 0x00005000), + /* GPIO_193 - *PNL0_VDDEN (DW0: 0x44000400, DW1: 0x00005000) */ + _PAD_CFG_STRUCT(GPIO_193, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), - // GPIO - _PAD_CFG_STRUCT(GPIO_196, 0x44000100, 0x00000000), + /* GPIO_194 - *PNL0_BKLTEN (DW0: 0x44000400, DW1: 0x00005000) */ + _PAD_CFG_STRUCT(GPIO_194, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), - // GPIO - _PAD_CFG_STRUCT(GPIO_197, 0x44000100, 0x00000000), + /* GPIO_195 - *PNL0_BKLTCTL (DW0: 0x44000400, DW1: 0x00005000) */ + _PAD_CFG_STRUCT(GPIO_195, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), - // GPIO - _PAD_CFG_STRUCT(GPIO_198, 0x44000100, 0x00000000), + /* GPIO_196 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_196, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // DDI1_HPD - _PAD_CFG_STRUCT(GPIO_199, 0x44000800, 0x00003000), + /* GPIO_197 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_197, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // DDI0_HPD - _PAD_CFG_STRUCT(GPIO_200, 0x44000802, 0x00003000), + /* GPIO_198 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_198, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(GPIO_201, 0x44000100, 0x00000000), + /* GPIO_199 - DDI1_HPD (DW0: 0x44000800, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_199, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K)), - // GPIO - _PAD_CFG_STRUCT(GPIO_202, 0x44000100, 0x00000000), + /* GPIO_200 - DDI0_HPD (DW0: 0x44000802, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_200, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), PAD_PULL(UP_20K)), - // GPIO - _PAD_CFG_STRUCT(GPIO_203, 0x44000102, 0x00000000), + /* GPIO_201 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_201, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(GPIO_204, 0x44000102, 0x00000000), + /* GPIO_202 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_202, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS0, 0x44000102, 0x00000000), + /* GPIO_203 - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_203, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // DDI2_HPD - _PAD_CFG_STRUCT(PMC_SPI_FS1, 0x44000802, 0x00003000), + /* GPIO_204 - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_204, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_FS2, 0x44000102, 0x00000000), + /* PMC_SPI_FS0 - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMC_SPI_FS0, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_RXD, 0x44000100, 0x00000000), + /* PMC_SPI_FS1 - DDI2_HPD (DW0: 0x44000802, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(PMC_SPI_FS1, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), PAD_PULL(UP_20K)), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_TXD, 0x44000100, 0x00000000), + /* PMC_SPI_FS2 - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMC_SPI_FS2, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // GPIO - _PAD_CFG_STRUCT(PMC_SPI_CLK, 0x44000100, 0x00000000), + /* PMC_SPI_RXD - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMC_SPI_RXD, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(PMIC_PWRGOOD, 0x44000203, 0x00002400), + /* PMC_SPI_TXD - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMC_SPI_TXD, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(PMIC_RESET_B, 0x44000102, 0x0003c000), + /* PMC_SPI_CLK - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMC_SPI_CLK, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(GPIO_213, 0x44000201, 0x00003000), + /* PMIC_PWRGOOD - GPIO (DW0: 0x44000203, DW1: 0x00002400) */ + _PAD_CFG_STRUCT(PMIC_PWRGOOD, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | + PAD_RX(1) | PAD_TX(1), + PAD_PULL(UP_1K)), - // GPIO - _PAD_CFG_STRUCT(GPIO_214, 0x44000102, 0x00003300), + /* PMIC_RESET_B - GPIO (DW0: 0x44000102, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMIC_RESET_B, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_IOSSTATE(IGNORE)), - // GPIO - _PAD_CFG_STRUCT(GPIO_215, 0x44000100, 0x00003300), + /* GPIO_213 - GPIO (DW0: 0x44000201, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_213, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_20K)), - // *THERMTRIP_N - _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, 0x44000400, 0x00003000), + /* GPIO_214 - GPIO (DW0: 0x44000102, DW1: 0x00003300) */ + _PAD_CFG_STRUCT(GPIO_214, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)), - // GPIO - _PAD_CFG_STRUCT(PMIC_STDBY, 0x44000201, 0x00001000), + /* GPIO_215 - GPIO (DW0: 0x44000100, DW1: 0x00003300) */ + _PAD_CFG_STRUCT(GPIO_215, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)), - // *PROCHOT_N - _PAD_CFG_STRUCT(PROCHOT_B, 0x44000402, 0x00023000), + /* PMIC_THERMTRIP_B - *THERMTRIP_N (DW0: 0x44000400, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(PMIC_THERMTRIP_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K)), - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SCL, 0xffffffff, 0xffffffff), + /* PMIC_STDBY - GPIO (DW0: 0x44000201, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(PMIC_STDBY, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(DN_20K)), - // RESERVED -// _PAD_CFG_STRUCT(PMIC_I2C_SDA, 0xffffffff, 0xffffffff), + /* PROCHOT_B - *PROCHOT_N (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(PROCHOT_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_74, 0x44000100, 0x00000000), + /* PMIC_I2C_SCL - RESERVED (DW0: 0xffffffff, DW1: 0xffffffff) */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_75, 0x44000100, 0x00000000), + /* PMIC_I2C_SDA - RESERVED (DW0: 0xffffffff, DW1: 0xffffffff) */ - // *GPIO - _PAD_CFG_STRUCT(GPIO_76, 0x44000100, 0x00000000), + /* GPIO_74 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_74, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_77, 0x44000100, 0x00000000), + /* GPIO_75 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_75, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_78, 0x44000100, 0x00000000), + /* GPIO_76 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_76, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // AVS_DMIC_CLK_A1 - _PAD_CFG_STRUCT(GPIO_79, 0x44000400, 0x0003d000), + /* GPIO_77 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_77, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // AVS_DMIC_CLK_B1 - _PAD_CFG_STRUCT(GPIO_80, 0x44000400, 0x0003d000), + /* GPIO_78 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_78, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // AVS_DMIC_DATA_1 - _PAD_CFG_STRUCT(GPIO_81, 0x44000400, 0x00025200), + /* GPIO_79 - AVS_DMIC_CLK_A1 (DW0: 0x44000400, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_79, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_DMIC_CLK_AB2 - _PAD_CFG_STRUCT(GPIO_82, 0x44000400, 0x0003d000), + /* GPIO_80 - AVS_DMIC_CLK_B1 (DW0: 0x44000400, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_80, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_DMIC_DATA_2 - _PAD_CFG_STRUCT(GPIO_83, 0x44000400, 0x00025200), + /* GPIO_81 - AVS_DMIC_DATA_1 (DW0: 0x44000400, DW1: 0x00025200) */ + _PAD_CFG_STRUCT(GPIO_81, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)), - // AVS_I2S2_MCLK - _PAD_CFG_STRUCT(GPIO_84, 0x44000400, 0x00001000), + /* GPIO_82 - AVS_DMIC_CLK_AB2 (DW0: 0x44000400, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_82, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_I2S2_BCLK - _PAD_CFG_STRUCT(GPIO_85, 0x44000400, 0x0001d200), + /* GPIO_83 - AVS_DMIC_DATA_2 (DW0: 0x44000400, DW1: 0x00025200) */ + _PAD_CFG_STRUCT(GPIO_83, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)), - // AVS_I2S2_WS_SYNC - _PAD_CFG_STRUCT(GPIO_86, 0x44000402, 0x0001d200), + /* GPIO_84 - AVS_I2S2_MCLK (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_84, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), + + /* GPIO_85 - AVS_I2S2_BCLK (DW0: 0x44000400, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_85, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), + + /* GPIO_86 - AVS_I2S2_WS_SYNC (DW0: 0x44000402, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_86, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), + + /* GPIO_87 - AVS_I2S2_SDI (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_87, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), + + /* GPIO_88 - AVS_I2S2_SDO (DW0: 0x44000400, DW1: 0x0001c200) */ + _PAD_CFG_STRUCT(GPIO_88, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // AVS_I2S2_SDI - _PAD_CFG_STRUCT(GPIO_87, 0x44000402, 0x0001f200), + /* GPIO_89 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_89, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // AVS_I2S2_SDO - _PAD_CFG_STRUCT(GPIO_88, 0x44000400, 0x0001c200), + /* GPIO_90 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_90, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_89, 0x44000100, 0x00000000), + /* GPIO_91 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_91, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_90, 0x44000100, 0x00000000), + /* GPIO_92 - *GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_92, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_91, 0x44000100, 0x00000000), + /* GPIO_97 - *FST_SPI_CS0_N (DW0: 0x44000402, DW1: 0x0003fc00) */ + _PAD_CFG_STRUCT(GPIO_97, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_92, 0x44000100, 0x00000000), + /* GPIO_98 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_98, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *FST_SPI_CS0_N - _PAD_CFG_STRUCT(GPIO_97, 0x44000402, 0x0003fc00), + /* GPIO_99 - *FST_SPI_MOSI_IO0 (DW0: 0x44000400, DW1: 0x0003fc00) */ + _PAD_CFG_STRUCT(GPIO_99, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), - // GPIO - _PAD_CFG_STRUCT(GPIO_98, 0x44000100, 0x00000000), + /* GPIO_100 - *FST_SPI_MISO_IO1 (DW0: 0x44000402, DW1: 0x0003fc00) */ + _PAD_CFG_STRUCT(GPIO_100, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), - // *FST_SPI_MOSI_IO0 - _PAD_CFG_STRUCT(GPIO_99, 0x44000400, 0x0003fc00), + /* GPIO_101 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_101, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // *FST_SPI_MISO_IO1 - _PAD_CFG_STRUCT(GPIO_100, 0x44000402, 0x0003fc00), + /* GPIO_102 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_102, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(GPIO_101, 0x44000100, 0x00000000), + /* GPIO_103 - *FST_SPI_CLK (DW0: 0x44000400, DW1: 0x0003fc00) */ + _PAD_CFG_STRUCT(GPIO_103, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), - // GPIO - _PAD_CFG_STRUCT(GPIO_102, 0x44000100, 0x00000000), + /* FST_SPI_CLK_FB - *n/a (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(FST_SPI_CLK_FB, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *FST_SPI_CLK - _PAD_CFG_STRUCT(GPIO_103, 0x44000400, 0x0003fc00), + /* GPIO_104 - SIO_SPI_0_CLK (DW0: 0x44000400, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_104, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // *n/a - _PAD_CFG_STRUCT(FST_SPI_CLK_FB, 0x44000400, 0x0003c000), + /* GPIO_105 - SIO_SPI_0_FS0 (DW0: 0x44000400, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_105, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // SIO_SPI_0_CLK - _PAD_CFG_STRUCT(GPIO_104, 0x44000400, 0x0001d200), + /* GPIO_106 - SIO_SPI_0_FS1 (DW0: 0x44000400, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_106, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // SIO_SPI_0_FS0 - _PAD_CFG_STRUCT(GPIO_105, 0x44000400, 0x0001f200), + /* GPIO_109 - SIO_SPI_0_RXD (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_109, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // SIO_SPI_0_FS1 - _PAD_CFG_STRUCT(GPIO_106, 0x44000400, 0x0001f200), + /* GPIO_110 - SIO_SPI_0_TXD (DW0: 0x44000400, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_110, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // SIO_SPI_0_RXD - _PAD_CFG_STRUCT(GPIO_109, 0x44000402, 0x0001f200), + /* GPIO_111 - SIO_SPI_1_CLK (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_111, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_0_TXD - _PAD_CFG_STRUCT(GPIO_110, 0x44000400, 0x0001f200), + /* GPIO_112 - SIO_SPI_1_FS0 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_112, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_1_CLK - _PAD_CFG_STRUCT(GPIO_111, 0x44000400, 0x00001000), + /* GPIO_113 - SIO_SPI_1_FS1 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_113, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_1_FS0 - _PAD_CFG_STRUCT(GPIO_112, 0x44000400, 0x00001000), + /* GPIO_116 - SIO_SPI_1_RXD (DW0: 0x44000402, DW1: 0x0001d000) */ + _PAD_CFG_STRUCT(GPIO_116, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)), - // SIO_SPI_1_FS1 - _PAD_CFG_STRUCT(GPIO_113, 0x44000400, 0x00001000), + /* GPIO_117 - SIO_SPI_1_TXD (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_117, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_1_RXD - _PAD_CFG_STRUCT(GPIO_116, 0x44000402, 0x0001d000), + /* GPIO_118 - SIO_SPI_2_CLK (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_118, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_1_TXD - _PAD_CFG_STRUCT(GPIO_117, 0x44000400, 0x00001000), + /* GPIO_119 - SIO_SPI_2_FS0 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_119, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_2_CLK - _PAD_CFG_STRUCT(GPIO_118, 0x44000400, 0x00001000), + /* GPIO_120 - SIO_SPI_2_FS1 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_120, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_2_FS0 - _PAD_CFG_STRUCT(GPIO_119, 0x44000400, 0x00001000), + /* GPIO_121 - SIO_SPI_2_FS2 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_121, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_2_FS1 - _PAD_CFG_STRUCT(GPIO_120, 0x44000400, 0x00001000), + /* GPIO_122 - SIO_SPI_2_RXD (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_122, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_2_FS2 - _PAD_CFG_STRUCT(GPIO_121, 0x44000400, 0x00001000), + /* GPIO_123 - SIO_SPI_2_TXD (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_123, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SIO_SPI_2_RXD - _PAD_CFG_STRUCT(GPIO_122, 0x44000400, 0x00001000), - // SIO_SPI_2_TXD - _PAD_CFG_STRUCT(GPIO_123, 0x44000400, 0x00001000), + /* GPIO Group West */ + /* GPIO_124 - LPSS_I2C0_SDA (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_124, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // ******************************* - // ******* GPIO Group West ******* - // ******************************* - // LPSS_I2C0_SDA - _PAD_CFG_STRUCT(GPIO_124, 0x44000402, 0x00012700), + /* GPIO_125 - LPSS_I2C0_SCL (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_125, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C0_SCL - _PAD_CFG_STRUCT(GPIO_125, 0x44000402, 0x00012700), + /* GPIO_126 - LPSS_I2C1_SDA (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_126, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C1_SDA - _PAD_CFG_STRUCT(GPIO_126, 0x44000402, 0x00012700), + /* GPIO_127 - LPSS_I2C1_SCL (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_127, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C1_SCL - _PAD_CFG_STRUCT(GPIO_127, 0x44000402, 0x00012700), + /* GPIO_128 - LPSS_I2C2_SDA (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_128, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C2_SDA - _PAD_CFG_STRUCT(GPIO_128, 0x44000402, 0x00012700), + /* GPIO_129 - LPSS_I2C2_SCL (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_129, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C2_SCL - _PAD_CFG_STRUCT(GPIO_129, 0x44000402, 0x00012700), + /* GPIO_130 - LPSS_I2C3_SDA (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_130, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C3_SDA - _PAD_CFG_STRUCT(GPIO_130, 0x44000402, 0x00012700), + /* GPIO_131 - LPSS_I2C3_SCL (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_131, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C3_SCL - _PAD_CFG_STRUCT(GPIO_131, 0x44000402, 0x00012700), + /* GPIO_132 - LPSS_I2C4_SDA (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_132, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C4_SDA - _PAD_CFG_STRUCT(GPIO_132, 0x44000402, 0x00012700), + /* GPIO_133 - LPSS_I2C4_SCL (DW0: 0x44000402, DW1: 0x00012700) */ + _PAD_CFG_STRUCT(GPIO_133, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(ENPU)), - // LPSS_I2C4_SCL - _PAD_CFG_STRUCT(GPIO_133, 0x44000402, 0x00012700), + /* GPIO_134 - LPSS_I2C5_SDA (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_134, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // LPSS_I2C5_SDA - _PAD_CFG_STRUCT(GPIO_134, 0x44000402, 0x0001f200), + /* GPIO_135 - LPSS_I2C5_SCL (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_135, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // LPSS_I2C5_SCL - _PAD_CFG_STRUCT(GPIO_135, 0x44000402, 0x0001f200), + /* GPIO_136 - LPSS_I2C6_SDA (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_136, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // LPSS_I2C6_SDA - _PAD_CFG_STRUCT(GPIO_136, 0x44000402, 0x0001f200), + /* GPIO_137 - LPSS_I2C6_SCL (DW0: 0x44000402, DW1: 0x0001f200) */ + _PAD_CFG_STRUCT(GPIO_137, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // LPSS_I2C6_SCL - _PAD_CFG_STRUCT(GPIO_137, 0x44000402, 0x0001f200), + /* GPIO_138 - LPSS_I2C7_SDA (DW0: 0x44000402, DW1: 0x00006700) */ + _PAD_CFG_STRUCT(GPIO_138, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), - // LPSS_I2C7_SDA - _PAD_CFG_STRUCT(GPIO_138, 0x44000402, 0x00006700), + /* GPIO_139 - LPSS_I2C7_SCL (DW0: 0x44000402, DW1: 0x00006700) */ + _PAD_CFG_STRUCT(GPIO_139, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_1K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPU)), - // LPSS_I2C7_SCL - _PAD_CFG_STRUCT(GPIO_139, 0x44000402, 0x00006700), + /* GPIO_146 - AVS_I2S6_BCLK (DW0: 0x44000800, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_146, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_I2S6_BCLK - _PAD_CFG_STRUCT(GPIO_146, 0x44000800, 0x0003d000), + /* GPIO_147 - AVS_I2S6_WS_SYNC (DW0: 0x44000800, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_147, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_I2S6_WS_SYNC - _PAD_CFG_STRUCT(GPIO_147, 0x44000800, 0x0003d000), + /* GPIO_148 - AVS_I2S6_SDI (DW0: 0x44000802, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_148, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_I2S6_SDI - _PAD_CFG_STRUCT(GPIO_148, 0x44000802, 0x0003d000), + /* GPIO_149 - AVS_I2S6_SDO (DW0: 0x44000800, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_149, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // AVS_I2S6_SDO - _PAD_CFG_STRUCT(GPIO_149, 0x44000800, 0x0003d000), + /* GPIO_150 - AVS_I2S5_BCLK (DW0: 0x44000800, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_150, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // AVS_I2S5_BCLK - _PAD_CFG_STRUCT(GPIO_150, 0x44000800, 0x0001d200), + /* GPIO_151 - AVS_I2S5_WS_SYNC (DW0: 0x44000800, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_151, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // AVS_I2S5_WS_SYNC - _PAD_CFG_STRUCT(GPIO_151, 0x44000800, 0x0001d200), + /* GPIO_152 - AVS_I2S5_SDI (DW0: 0x44000802, DW1: 0x0001d200) */ + _PAD_CFG_STRUCT(GPIO_152, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // AVS_I2S5_SDI - _PAD_CFG_STRUCT(GPIO_152, 0x44000802, 0x0001d200), + /* GPIO_153 - AVS_I2S5_SDO (DW0: 0x44000800, DW1: 0x0001c200) */ + _PAD_CFG_STRUCT(GPIO_153, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPD)), - // AVS_I2S5_SDO - _PAD_CFG_STRUCT(GPIO_153, 0x44000800, 0x0001c200), + /* GPIO_154 - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_154, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(GPIO_154, 0x44000102, 0x00000000), + /* GPIO_155 - SPKR (DW0: 0x44000800, DW1: 0x0003d000) */ + _PAD_CFG_STRUCT(GPIO_155, + PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), - // SPKR - _PAD_CFG_STRUCT(GPIO_155, 0x44000800, 0x0003d000), + /* GPIO_209 - *PCIE_CLKREQ0_N (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_209, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *PCIE_CLKREQ0_N - _PAD_CFG_STRUCT(GPIO_209, 0x44000400, 0x00001000), + /* GPIO_210 - *PCIE_CLKREQ1_N (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_210, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *PCIE_CLKREQ1_N - _PAD_CFG_STRUCT(GPIO_210, 0x44000400, 0x00001000), + /* GPIO_211 - *PCIE_CLKREQ2_N (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_211, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *PCIE_CLKREQ2_N - _PAD_CFG_STRUCT(GPIO_211, 0x44000400, 0x00001000), + /* GPIO_212 - *PCIE_CLKREQ3_N (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_212, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *PCIE_CLKREQ3_N - _PAD_CFG_STRUCT(GPIO_212, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_0 - *OSC_CLK_OUT_0 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(OSC_CLK_OUT_0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *OSC_CLK_OUT_0 - _PAD_CFG_STRUCT(OSC_CLK_OUT_0, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_1 - *OSC_CLK_OUT_1 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(OSC_CLK_OUT_1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *OSC_CLK_OUT_1 - _PAD_CFG_STRUCT(OSC_CLK_OUT_1, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_2 - *OSC_CLK_OUT_2 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(OSC_CLK_OUT_2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *OSC_CLK_OUT_2 - _PAD_CFG_STRUCT(OSC_CLK_OUT_2, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_3 - *OSC_CLK_OUT_3 (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(OSC_CLK_OUT_3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // *OSC_CLK_OUT_3 - _PAD_CFG_STRUCT(OSC_CLK_OUT_3, 0x44000400, 0x00001000), + /* OSC_CLK_OUT_4 - GPIO (DW0: 0x44000100, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(OSC_CLK_OUT_4, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), - // GPIO - _PAD_CFG_STRUCT(OSC_CLK_OUT_4, 0x44000100, 0x00000000), + /* PMU_AC_PRESENT - *GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMU_AC_PRESENT, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // *GPIO - _PAD_CFG_STRUCT(PMU_AC_PRESENT, 0x44000102, 0x00000000), + /* PMU_BATLOW_B - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(PMU_BATLOW_B, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // GPIO - _PAD_CFG_STRUCT(PMU_BATLOW_B, 0x44000102, 0x00000000), + /* PMU_PLTRST_B - *PMU_PLTRST_N (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_PLTRST_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *PMU_PLTRST_N - _PAD_CFG_STRUCT(PMU_PLTRST_B, 0x44000400, 0x0003c000), + /* PMU_PWRBTN_B - *PMU_PWRBTN_N (DW0: 0x44000402, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(PMU_PWRBTN_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // *PMU_PWRBTN_N - _PAD_CFG_STRUCT(PMU_PWRBTN_B, 0x44000402, 0x0003f000), + /* PMU_RESETBUTTON_B - *PMU_RSTBTN_N (DW0: 0x44000402, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), PAD_IOSSTATE(IGNORE)), - // *PMU_RSTBTN_N - _PAD_CFG_STRUCT(PMU_RESETBUTTON_B, 0x44000402, 0x0003c000), + /* PMU_SLP_S0_B - *PMU_SLP_S0_N (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_SLP_S0_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *PMU_SLP_S0_N - _PAD_CFG_STRUCT(PMU_SLP_S0_B, 0x44000400, 0x0003c000), + /* PMU_SLP_S3_B - *PMU_SLP_S3_N (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_SLP_S3_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *PMU_SLP_S3_N - _PAD_CFG_STRUCT(PMU_SLP_S3_B, 0x44000400, 0x0003c000), + /* PMU_SLP_S4_B - *PMU_SLP_S4_N (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_SLP_S4_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *PMU_SLP_S4_N - _PAD_CFG_STRUCT(PMU_SLP_S4_B, 0x44000400, 0x0003c000), + /* PMU_SUSCLK - *PMU_SUSCLK (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(PMU_SUSCLK, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), - // *PMU_SUSCLK - _PAD_CFG_STRUCT(PMU_SUSCLK, 0x44000400, 0x0003c000), + /* PMU_WAKE_B - *GPIO (DW0: 0x44000201, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(PMU_WAKE_B, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // *GPIO - _PAD_CFG_STRUCT(PMU_WAKE_B, 0x44000201, 0x0003f000), + /* SUS_STAT_B - *SUS_STAT_B (DW0: 0x44000400, DW1: 0x0003c000) */ + _PAD_CFG_STRUCT(SUS_STAT_B, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), - // *SUS_STAT_B - _PAD_CFG_STRUCT(SUS_STAT_B, 0x44000400, 0x0003c000), + /* SUSPWRDNACK - GPIO (DW0: 0x44000102, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(SUSPWRDNACK, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), 0), - // GPIO - _PAD_CFG_STRUCT(SUSPWRDNACK, 0x44000102, 0x00000000), + /* GPIO Group South-West */ - // ************************************ - // ******* GPIO Group SouthWest ******* - // ************************************ - // PCIE_WAKE0_N - _PAD_CFG_STRUCT(GPIO_205, 0x44000402, 0x00000000), + /* GPIO_205 - PCIE_WAKE0_N (DW0: 0x44000402, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_205, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), 0), - // PCIE_WAKE1_N - _PAD_CFG_STRUCT(GPIO_206, 0x44000402, 0x00000000), + /* GPIO_206 - PCIE_WAKE1_N (DW0: 0x44000402, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_206, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), 0), - // PCIE_WAKE2_N - _PAD_CFG_STRUCT(GPIO_207, 0x44000402, 0x00000000), + /* GPIO_207 - PCIE_WAKE2_N (DW0: 0x44000402, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_207, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), 0), - // PCIE_WAKE3_N - _PAD_CFG_STRUCT(GPIO_208, 0x44000402, 0x00000000), + /* GPIO_208 - PCIE_WAKE3_N (DW0: 0x44000402, DW1: 0x00000000) */ + _PAD_CFG_STRUCT(GPIO_208, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), 0), - // *EMMC_CLK - _PAD_CFG_STRUCT(GPIO_156, 0x44000402, 0x00005000), + /* GPIO_156 - *EMMC_CLK (DW0: 0x44000402, DW1: 0x00005000) */ + _PAD_CFG_STRUCT(GPIO_156, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0)), - // *EMMC_D0 - _PAD_CFG_STRUCT(GPIO_157, 0x44000402, 0x00023000), + /* GPIO_157 - *EMMC_D0 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_157, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D1 - _PAD_CFG_STRUCT(GPIO_158, 0x44000402, 0x00023000), + /* GPIO_158 - *EMMC_D1 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_158, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D2 - _PAD_CFG_STRUCT(GPIO_159, 0x44000402, 0x00023000), + /* GPIO_159 - *EMMC_D2 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_159, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D3 - _PAD_CFG_STRUCT(GPIO_160, 0x44000402, 0x00023000), + /* GPIO_160 - *EMMC_D3 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_160, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D4 - _PAD_CFG_STRUCT(GPIO_161, 0x44000402, 0x00023000), + /* GPIO_161 - *EMMC_D4 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_161, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D5 - _PAD_CFG_STRUCT(GPIO_162, 0x44000402, 0x00023000), + /* GPIO_162 - *EMMC_D5 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_162, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D6 - _PAD_CFG_STRUCT(GPIO_163, 0x44000402, 0x00023000), + /* GPIO_163 - *EMMC_D6 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_163, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_D7 - _PAD_CFG_STRUCT(GPIO_164, 0x44000402, 0x00023000), + /* GPIO_164 - *EMMC_D7 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_164, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *EMMC_CMD - _PAD_CFG_STRUCT(GPIO_165, 0x44000402, 0x00023000), + /* GPIO_165 - *EMMC_CMD (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_165, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_166, 0x44000300, 0x00001000), + /* GPIO_166 - *GPIO (DW0: 0x44000300, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_166, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + PAD_PULL(DN_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_167, 0x44000102, 0x00023000), + /* GPIO_167 - *GPIO (DW0: 0x44000102, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_167, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_168, 0x44000100, 0x00023000), + /* GPIO_168 - *GPIO (DW0: 0x44000100, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_168, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_169, 0x44000200, 0x00003000), + /* GPIO_169 - *GPIO (DW0: 0x44000200, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_169, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_170, 0x44000201, 0x00003000), + /* GPIO_170 - *GPIO (DW0: 0x44000201, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_170, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_20K)), - // *GPIO - _PAD_CFG_STRUCT(GPIO_171, 0x44000201, 0x00003000), + /* GPIO_171 - *GPIO (DW0: 0x44000201, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_171, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | PAD_TX(1), + PAD_PULL(UP_20K)), - // SDCARD_CLK - _PAD_CFG_STRUCT(GPIO_172, 0x44000400, 0x00021100), + /* GPIO_172 - SDCARD_CLK (DW0: 0x44000400, DW1: 0x00021100) */ + _PAD_CFG_STRUCT(GPIO_172, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // n/a - _PAD_CFG_STRUCT(GPIO_179, 0x44000400, 0x00001000), + /* GPIO_179 - n/a (DW0: 0x44000400, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_179, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)), - // SDCARD_D0 - _PAD_CFG_STRUCT(GPIO_173, 0x44000402, 0x00023100), + /* GPIO_173 - SDCARD_D0 (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(GPIO_173, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // SDCARD_D1 - _PAD_CFG_STRUCT(GPIO_174, 0x44000402, 0x00023000), + /* GPIO_174 - SDCARD_D1 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_174, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // SDCARD_D2 - _PAD_CFG_STRUCT(GPIO_175, 0x44000402, 0x00023000), + /* GPIO_175 - SDCARD_D2 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_175, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // SDCARD_D3 - _PAD_CFG_STRUCT(GPIO_176, 0x44000402, 0x00023000), + /* GPIO_176 - SDCARD_D3 (DW0: 0x44000402, DW1: 0x00023000) */ + _PAD_CFG_STRUCT(GPIO_176, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1)), - // SDCARD_CD_B - _PAD_CFG_STRUCT(GPIO_177, 0x44000402, 0x00003000), + /* GPIO_177 - SDCARD_CD_B (DW0: 0x44000402, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_177, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K)), - // SDCARD_CMD - _PAD_CFG_STRUCT(GPIO_178, 0x44000402, 0x00023100), + /* GPIO_178 - SDCARD_CMD (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(GPIO_178, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // SDCARD_LVL_WP - _PAD_CFG_STRUCT(GPIO_186, 0x44000402, 0x00003000), + /* GPIO_186 - SDCARD_LVL_WP (DW0: 0x44000402, DW1: 0x00003000) */ + _PAD_CFG_STRUCT(GPIO_186, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K)), - // *EMMC_RCLK - _PAD_CFG_STRUCT(GPIO_182, 0x44000400, 0x0001d000), + /* GPIO_182 - *EMMC_RCLK (DW0: 0x44000400, DW1: 0x0001d000) */ + _PAD_CFG_STRUCT(GPIO_182, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)), - // GPIO - _PAD_CFG_STRUCT(GPIO_183, 0x44000200, 0x00001000), + /* GPIO_183 - GPIO (DW0: 0x44000200, DW1: 0x00001000) */ + _PAD_CFG_STRUCT(GPIO_183, + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), + PAD_PULL(DN_20K)), - // SMB_ALERT_N - _PAD_CFG_STRUCT(SMB_ALERTB, 0x44000402, 0x0003f000), + /* SMB_ALERTB - SMB_ALERT_N (DW0: 0x44000402, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(SMB_ALERTB, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // SMB_CLK - _PAD_CFG_STRUCT(SMB_CLK, 0x44000402, 0x0003f000), + /* SMB_CLK - SMB_CLK (DW0: 0x44000402, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(SMB_CLK, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // SMB_DATA - _PAD_CFG_STRUCT(SMB_DATA, 0x44000402, 0x0003f000), + /* SMB_DATA - SMB_DATA (DW0: 0x44000402, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(SMB_DATA, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // LPC_ILB_SERIRQ - _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, 0x44000402, 0x0003f000), + /* LPC_ILB_SERIRQ - LPC_ILB_SERIRQ (DW0: 0x44000402, DW1: 0x0003f000) */ + _PAD_CFG_STRUCT(LPC_ILB_SERIRQ, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), - // LPC_CLKOUT0 - _PAD_CFG_STRUCT(LPC_CLKOUT0, 0x44000400, 0x00020100), + /* LPC_CLKOUT0 - LPC_CLKOUT0 (DW0: 0x44000400, DW1: 0x00020100) */ + _PAD_CFG_STRUCT(LPC_CLKOUT0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_CLKOUT1 - _PAD_CFG_STRUCT(LPC_CLKOUT1, 0x44000400, 0x00020100), + /* LPC_CLKOUT1 - LPC_CLKOUT1 (DW0: 0x44000400, DW1: 0x00020100) */ + _PAD_CFG_STRUCT(LPC_CLKOUT1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_AD0 - _PAD_CFG_STRUCT(LPC_AD0, 0x44000402, 0x00023100), + /* LPC_AD0 - LPC_AD0 (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_AD0, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_AD1 - _PAD_CFG_STRUCT(LPC_AD1, 0x44000402, 0x00023100), + /* LPC_AD1 - LPC_AD1 (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_AD1, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_AD2 - _PAD_CFG_STRUCT(LPC_AD2, 0x44000402, 0x00023100), + /* LPC_AD2 - LPC_AD2 (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_AD2, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_AD3 - _PAD_CFG_STRUCT(LPC_AD3, 0x44000402, 0x00023100), + /* LPC_AD3 - LPC_AD3 (DW0: 0x44000402, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_AD3, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX(1), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_CLKRUNB - _PAD_CFG_STRUCT(LPC_CLKRUNB, 0x44000400, 0x00023100), + /* LPC_CLKRUNB - LPC_CLKRUNB (DW0: 0x44000400, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_CLKRUNB, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), - // LPC_FRAMEB - _PAD_CFG_STRUCT(LPC_FRAMEB, 0x44000400, 0x00023100), + /* LPC_FRAMEB - LPC_FRAMEB (DW0: 0x44000400, DW1: 0x00023100) */ + _PAD_CFG_STRUCT(LPC_FRAMEB, + PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)), }; -#endif +#endif /* CFG_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2523439af8842365c7de901bdfad85ad16d25dcf Gerrit-Change-Number: 42608 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 23

Change in coreboot[master]: nb/intel/haswell: Add Crystal Well PCI IDs
by Iru Cai (vimacs) (Code Review) 03 Aug '20

03 Aug '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/41658 to review the following change. Change subject: nb/intel/haswell: Add Crystal Well PCI IDs ...................................................................... nb/intel/haswell: Add Crystal Well PCI IDs From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs use some new PCI IDs. Without this patch, the Crystal Well northbridge cannot be initialized in ramstage, thus the machine cannot boot. The PCI IDs of Crystal Well related devices can be found online [2]. Not tested on real hardware yet. [1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHL… [2] https://pci-ids.ucw.cz/read/PC/8086 Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/pcie.c 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41658/1 diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index f8a16e2..0a0a861 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -97,7 +97,7 @@ .ops_pci = &minihd_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; +static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 }; static const struct pci_driver haswell_minihd __pci_driver = { .ops = &minihd_ops, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e..c1bc245 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -466,6 +466,7 @@ 0x0c04, /* Mobile */ 0x0a04, /* ULT */ 0x0c08, /* Server */ + 0x0d00, 0x0d04, /* Crystal Well */ 0 }; diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index 74f11dd..73e909e 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -65,7 +65,10 @@ #endif }; -static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 }; +static const unsigned short pci_device_ids[] = { + 0x0c01, 0x0c05, 0x0c09, 0x0c0d, + 0x0d01, 0x0d05, 0x0d09, /* Crystal Well */ + 0 }; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/41658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3 Gerrit-Change-Number: 41658 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: cpu/intel/common/fsb.c: add Crystal Well support
by Iru Cai (vimacs) (Code Review) 03 Aug '20

03 Aug '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44065 to review the following change. Change subject: cpu/intel/common/fsb.c: add Crystal Well support ...................................................................... cpu/intel/common/fsb.c: add Crystal Well support Without this change, there will be no console output when using a Crystal Well CPU. Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/cpu/intel/common/fsb.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44065/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 7772171..3d46bbc 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -45,6 +45,7 @@ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ + case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/44065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18645c52d9c4a4ea7acb602bcb39b796d9e24b9 Gerrit-Change-Number: 44065 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: assert.h: Try to evaluate assertions at compile time
by Julius Werner (Code Review) 03 Aug '20

03 Aug '20

Hello Shelley Chen, Furquan Shaikh, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44044 to review the following change. Change subject: assert.h: Try to evaluate assertions at compile time ...................................................................... assert.h: Try to evaluate assertions at compile time Many places in coreboot seem to like to do things like assert(CONFIG(SOME_KCONFIG)); This is somewhat suboptimal since assert() is a runtime check, so you don't see that this fails until someone actually tries to boot it even though the compiler is totally aware of it already. We already have the dead_code() macro to do this better: if (CONFIG(SOME_KCONFIG)) dead_code(); Rather than fixing all these and trying to carefully educate people about which type of check is more appropriate in what situation, we can just employ the magic of __builtin_constant_p() to automatically make the former statement behave like the latter. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I06691b732598eb2a847a17167a1cb92149710916 --- M src/include/assert.h 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/44044/1 diff --git a/src/include/assert.h b/src/include/assert.h index 0463175..d9883fd 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -22,9 +22,12 @@ #define __ASSERT_LINE__ __LINE__ #endif +#define __build_time_assert(x) (__builtin_constant_p(x) ? \ + ((x) ? 1 : dead_code_t(int)) : 0) + /* GCC and CAR versions */ #define ASSERT(x) { \ - if (!(x)) { \ + if (!__build_time_assert(x) && !(x)) { \ printk(BIOS_EMERG, \ "ASSERTION ERROR: file '%s', line %d\n", \ __ASSERT_FILE__, __ASSERT_LINE__); \ @@ -33,7 +36,7 @@ } \ } #define ASSERT_MSG(x, msg) { \ - if (!(x)) { \ + if (!__build_time_assert(x) && !(x)) { \ printk(BIOS_EMERG, \ "ASSERTION ERROR: file '%s', line %d\n", \ __ASSERT_FILE__, __ASSERT_LINE__); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/44044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06691b732598eb2a847a17167a1cb92149710916 Gerrit-Change-Number: 44044 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: Change all assert(0) to BUG()
by Julius Werner (Code Review) 03 Aug '20

03 Aug '20

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44047 ) Change subject: Change all assert(0) to BUG() ...................................................................... Change all assert(0) to BUG() I would like to make assertions evaluate at compile time where possible, but sometimes people used a literal assert(0) to force an assertion in a certain code path. We already have BUG() for that so let's just replace those instances with that. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32 --- M src/device/device_const.c M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/picasso/reset.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/mediatek/mt8183/mt6358.c M src/southbridge/amd/pi/hudson/early_setup.c 6 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44047/1 diff --git a/src/device/device_const.c b/src/device/device_const.c index 79f025d..2dc583c 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -184,7 +184,7 @@ DEVTREE_CONST struct device *child; if (!parent) { - assert(0); + BUG(); /* Return NULL in case asserts are considered non-fatal. */ return NULL; } @@ -282,7 +282,7 @@ pci_devfn_t devfn) { if (!bridge || (bridge->path.type != DEVICE_PATH_PCI)) { - assert(0); + BUG(); /* Return NULL in case asserts are non-fatal. */ return NULL; } diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index b9646b9..4f1b842 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -28,7 +28,7 @@ if (!is_gpio_event_level_triggered(flags)) { printk(BIOS_ERR, "ERROR: %s - Only level trigger allowed for SMI!\n", __func__); - assert(0); + BUG(); return; } diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index b6aeb1f..902538ff 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -49,6 +49,6 @@ { printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", __func__, status); - assert(0); + BUG(); do_cold_reset(); } diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index ee91aa6..d6958b1 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -78,7 +78,7 @@ } printk(BIOS_ERR, "%s: pad %d is not found in community %s!\n", __func__, relative_pad, comm->name); - assert(0); + BUG(); return i; } diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7b4febc..6e6e43a 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -831,7 +831,7 @@ break; default: - assert(0); + BUG(); return; }; diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 14bb5e2..f43dbb9 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -187,7 +187,7 @@ pci_write_config32(dev, LPC_WIDEIO2_GENERIC_PORT, tmp); enable_wideio(2, size); } else { /* All WIDEIO locations used*/ - assert(0); + BUG(); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32 Gerrit-Change-Number: 44047 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
by Julius Werner (Code Review) 03 Aug '20

03 Aug '20

Hello Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43983 to review the following change. Change subject: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 ...................................................................... qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space. BUG=b:160115694 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If9c03ac890a7975855394c2e08b8433472df204d --- M src/soc/qualcomm/sc7180/include/soc/gpio.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43983/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index e28d808..8bfa36e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -159,10 +159,10 @@ RES_7), PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), -- To view, visit https://review.coreboot.org/c/coreboot/+/43983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9c03ac890a7975855394c2e08b8433472df204d Gerrit-Change-Number: 43983 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/string: Add standard strstr() function
by Jes Klinke (Code Review) 03 Aug '20

03 Aug '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44085 to review the following change. Change subject: lib/string: Add standard strstr() function ...................................................................... lib/string: Add standard strstr() function Adding implementation of standard library strstr() See https://review.coreboot.org/c/coreboot/+/43741 for context. Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350 Signed-off-by: jbk(a)chromium.org --- M src/include/string.h M src/lib/string.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44085/1 diff --git a/src/include/string.h b/src/include/string.h index 8eef068..3cfa18d 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -29,6 +29,7 @@ int strncmp(const char *s1, const char *s2, int maxlen); int strspn(const char *str, const char *spn); int strcspn(const char *str, const char *spn); +char *strstr(const char *haystack, const char *needle); char *strtok_r(char *str, const char *delim, char **ptr); char *strtok(char *str, const char *delim); long atol(const char *str); diff --git a/src/lib/string.c b/src/lib/string.c index e8f72a2..9677520 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -163,6 +163,16 @@ return ret; } +char *strstr(const char *haystack, const char *needle) +{ + size_t needle_len = strlen(needle); + for (; *haystack; haystack++) { + if (!strncmp(haystack, needle, needle_len)) + return (char *)haystack; + } + return NULL; +} + char *strtok_r(char *str, const char *delim, char **ptr) { char *start; -- To view, visit https://review.coreboot.org/c/coreboot/+/44085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63e26e98ed2dd15542f81c0a3a5e353bb93b7350 Gerrit-Change-Number: 44085 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Change wake to be triggered on a raising edge
by Alex Levin (Code Review) 03 Aug '20

03 Aug '20

Hello Alex Levin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44089 to review the following change. Change subject: mb/google/volteer: Change wake to be triggered on a raising edge ...................................................................... mb/google/volteer: Change wake to be triggered on a raising edge ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW. Fixing for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44089/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index c7350cb..d4bd7f4 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -114,7 +114,7 @@ chip drivers/generic/gpio_keys register "name" = ""PENH"" # GPP_B3 is the IRQ source, and GPP_E1 is the wake source - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_B3)" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" register "key.wake_gpe" = "GPE0_DW2_01" register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 8e5985e..62749fc 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -70,7 +70,7 @@ chip drivers/generic/gpio_keys register "name" = ""PENH"" # GPP_B3 is the IRQ source, and GPP_E1 is the wake source - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_B3)" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_B3)" register "key.wake_gpe" = "GPE0_DW2_01" register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" -- To view, visit https://review.coreboot.org/c/coreboot/+/44089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9 Gerrit-Change-Number: 44089 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Alex Levin <levinale(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-armv7: Fix board
by Patrick Rudolph (Code Review) 03 Aug '20

03 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39187 ) Change subject: mb/emulation/qemu-armv7: Fix board ...................................................................... mb/emulation/qemu-armv7: Fix board Fix multiple issues allowing to boot until "Payload not loaded": * The FMAP_CACHE was placed in memory mapped flash - Place the FMAP_CACHE in DRAM. * The FMAP_CACHE was overlapping the BOOTBLOCK, which has a default size of 128KiB. - Increase the bootblock size in memlayout to 128KiB to match the FMAP. * The heap in bootblock wasn't usable. - Move the bootblock to DRAM and add custom relocation code. * A FIT payload couldn't be compiled in as the POSTRAM_CBFS_CACHE was missing. - Add the POSTRAM_CBFS_CACHE to memlayout. * The coreboot log is spammed with missing timestamp table error messages - Add TIMESTAMP table to memlayout. Tested on QEMU armv7 vexpress. Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-armv7/Kconfig M src/mainboard/emulation/qemu-armv7/Makefile.inc A src/mainboard/emulation/qemu-armv7/bootblock_asm.S M src/mainboard/emulation/qemu-armv7/memlayout.ld 4 files changed, 117 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/39187/1 diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 181f9a4..8c7551f 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -36,6 +36,7 @@ select BOOT_DEVICE_NOT_SPI_FLASH select MISSING_BOARD_RESET select NO_MONOTONIC_TIMER + select BOOTBLOCK_CUSTOM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index c62915b..8b350af 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -12,6 +12,8 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. +bootblock-y += bootblock_asm.S + romstage-y += romstage.c romstage-y += cbmem.c diff --git a/src/mainboard/emulation/qemu-armv7/bootblock_asm.S b/src/mainboard/emulation/qemu-armv7/bootblock_asm.S new file mode 100644 index 0000000..d2c8b75 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/bootblock_asm.S @@ -0,0 +1,106 @@ +/* + * Early initialization code for ARM architecture. + * + * This file is based off of the OMAP3530/ARM Cortex start.S file from Das + * U-Boot, which itself got the file from armboot. + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * Copyright (c) 2013 The Chromium OS Authors + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> +.arm + +ENTRY(_start) + /* + * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr_cxf, #0xdf + + /* + * From Cortex-A Series Programmer's Guide: + * Only CPU 0 performs initialization. Other CPUs go into WFI + * to do this, first work out which CPU this is + * this code typically is run before any other initialization step + */ + mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + and r1, r1, #0x3 @ Extract CPU ID bits + cmp r1, #0 + bne wait_for_interrupt @ If this is not core0, wait + + ldr r0, =_bootblock + ldr r1, =_ebootblock + adr r2, _start + + cmp r0, r2 + beq relocated + +relocate_program: + ldmia r2!, {r9-r10} + stmia r0!, {r9-r10} + cmp r0, r1 + bne relocate_program + + /* Jump to it... */ + ldr r0, =_bootblock + adr r1, _start + add lr, r0, r1 + mov pc, lr + +relocated: + /* + * Initialize the stack to a known value. This is used to check for + * stack overflow later in the boot process. + */ + ldr r0, =_stack + ldr r1, =_estack + ldr r2, =0xdeadbeef +init_stack_loop: + str r2, [r0] + add r0, #4 + cmp r0, r1 + bne init_stack_loop + +/* Set stackpointer in internal RAM to call bootblock main() */ +call_bootblock: + ldr sp, =_estack /* Set up stack pointer */ + ldr r0,=0x00000000 + /* + * The current design of cpu_info places the + * struct at the top of the stack. The number of + * words pushed must be at least as large as that + * struct. + */ + push {r0-r2} + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + /* + * Use "bl" instead of "b" even though we do not intend to return. + * "bl" gets compiled to "blx" if we're transitioning from ARM to + * Thumb. However, "b" will not and GCC may attempt to create a + * wrapper which is currently broken. + */ + bl main + +wait_for_interrupt: + wfi + mov pc, lr @ back to my caller +ENDPROC(_start) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb3..3fa2234 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -41,14 +41,16 @@ { /* TODO: does this thing emulate SRAM? */ - BOOTBLOCK(0x00000, 64K) - FMAP_CACHE(0x10000, 2K) + REGION(flash, 0, CONFIG_ROM_SIZE, 4K) DRAM_START(0x60000000) STACK(0x60000000, 64K) - ROMSTAGE(0x60010000, 128K) - RAMSTAGE(0x60030000, 16M) - + BOOTBLOCK(0x60010000, 128K) + FMAP_CACHE(0x60030000, 4K) + TIMESTAMP(0x60031000, 1K) /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x61030000, 16K) + TTB(0x60034000, 16K) + ROMSTAGE(0x60038000, 128K) + RAMSTAGE(0x60060000, 16M) + POSTRAM_CBFS_CACHE(0x61060000, 8M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/39187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9357a5c059ca179826c5a7e7616a5c688ec2e95 Gerrit-Change-Number: 39187 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: indent config names for burnet and esche
by Hung-Te Lin (Code Review) 03 Aug '20

03 Aug '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43986 ) Change subject: mb/google/kukui: indent config names for burnet and esche ...................................................................... mb/google/kukui: indent config names for burnet and esche The 'burnet' and 'esche' in Kcofig.name should have two spaces after the arrow. BUG=None TEST=make menuconfig BRANCH=kukui Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig.name 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/43986/1 diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 77cdc67..ecfb86e 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -51,9 +51,9 @@ select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_ESCHE - bool "-> Esche" + bool "-> Esche" select BOARD_GOOGLE_JACUZZI_COMMON config BOARD_GOOGLE_BURNET - bool "-> Burnet" + bool "-> Burnet" select BOARD_GOOGLE_JACUZZI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/43986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7cc31cf459082a797445fb8223b3d9cbde72901 Gerrit-Change-Number: 43986 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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