Change in coreboot[master]: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
Hello Philip Chen, mturney mturney,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/43983
to review the following change.
Change subject: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 ......................................................................
qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space.
BUG=b:160115694
Signed-off-by: Julius Werner jwerner@chromium.org Change-Id: If9c03ac890a7975855394c2e08b8433472df204d --- M src/soc/qualcomm/sc7180/include/soc/gpio.h 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/43983/1
diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index e28d808..8bfa36e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -159,10 +159,10 @@ RES_7), PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43983 )
Change subject: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43983 )
Change subject: qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 ......................................................................
qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space.
BUG=b:160115694
Signed-off-by: Julius Werner jwerner@chromium.org Change-Id: If9c03ac890a7975855394c2e08b8433472df204d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/soc/qualcomm/sc7180/include/soc/gpio.h 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved
diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index e28d808..8bfa36e 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -159,10 +159,10 @@ RES_7), PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), - PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), + PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
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EricR Lai (Code Review) -
Julius Werner (Code Review)
-
Patrick Georgi (Code Review)