coreboot-gerrit August 2020

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Change in coreboot[master]: mb/**/{devicetree,overridetree}.cb: Indent with tabs
by Tim Wawrzynczak (Code Review) 03 Aug '20

03 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44113 ) Change subject: mb/**/{devicetree,overridetree}.cb: Indent with tabs ...................................................................... Patch Set 3: Code-Review+2 could we also add indent-checking (linting) for *.cb files too to help prevent this in the future? I don't know much about how jenkins is set up. -- To view, visit https://review.coreboot.org/c/coreboot/+/44113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Gerrit-Change-Number: 44113 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 18:15:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 03 Aug '20

03 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: > Patch Set 2: Code-Review+1 > > Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be > somewhere between FSP 2.0 and 2.1. > > Subrata, do you know what the lack of SkipMpInit for CNL implies? SkipMpInit wasn't removed but moved from FSP-S to FSP-M. I checked the FSP binary. It does only set the lock if SkipMpInit=0. -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Aug 2020 18:14:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[refs/meta/config]: Do not copy Jenkins scores on rebase
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42744 ) Change subject: Do not copy Jenkins scores on rebase ...................................................................... Patch Set 5: Hello? -- To view, visit https://review.coreboot.org/c/coreboot/+/42744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: refs/meta/config Gerrit-Change-Id: Ic37406b95e997a202972cf3813122e91cc1a2f9b Gerrit-Change-Number: 42744 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 17:42:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Michael Niewöhner (Code Review) 03 Aug '20

03 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44137 ) Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST ...................................................................... Patch Set 3: Matt, thanks for sharing your thoughts! > Patch Set 3: > > (1 comment) > > The basis of the change (i.e., that the chip features are independent) is valid, though I'm not clear on the benefit/need unless there's some Intel chips that now support HWP but not EIST. Most of the Intel-based systems that don't set "eist_enable" in their devicetree are probably doing it by accidental oversight, e.g.: > > https://review.coreboot.org/c/coreboot/+/29664 > > particularly since coreboot is most often used by Linux (where the pstate driver typical forces on EIST or HWP) vs Windows (which expects the features to be advertised/enable by the firmware before the OS attempts to use them). In the past there's been some informal chats before about whether eist_enable should be enabled by default or disappear entirely. The current code does force an unnecessary relationship between HWP and EIST though it does help to force people to remember to enable EIST. IMHO we shouldn't force people to do the right thing by establishing technically wrong dependencies, which lead to even more confusion. > > What I describe here is mostly trying to provide some background/content on the situation rather than be an argument against the change. IMO, the the current way these features are structured in coreboot aren't ideal but addressing them would be a much bigger change that's probably outside the scope of what anyone wants to do right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/44137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Gerrit-Change-Number: 44137 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 17:38:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview: Use `MiB` definition
by Arthur Heymans (Code Review) 03 Aug '20

03 Aug '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44124 ) Change subject: nb/intel/pineview: Use `MiB` definition ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd Gerrit-Change-Number: 44124 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 17:35:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview: Remove dead assignments
by Arthur Heymans (Code Review) 03 Aug '20

03 Aug '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44119 ) Change subject: nb/intel/pineview: Remove dead assignments ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide45e1e5e8b8d6cfebd2fc4e272b1971b0a9b346 Gerrit-Change-Number: 44119 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 17:34:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Michael Niewöhner (Code Review) 03 Aug '20

03 Aug '20

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Change in coreboot[master]: nb/intel/ironlake: Update to ASL 2.0 syntax
by Angel Pons (Code Review) 03 Aug '20

03 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43154 ) Change subject: nb/intel/ironlake: Update to ASL 2.0 syntax ...................................................................... nb/intel/ironlake: Update to ASL 2.0 syntax Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I2771407e5fa2dec5d2b554e53f7ad14cb4a4a4aa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/acpi/hostbridge.asl 1 file changed, 28 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43154/1 diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index 6a59fb5..324fb35 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -92,17 +91,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -122,23 +120,23 @@ Store ("Set TDP Down", Debug) /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDD, 125), 100, , PL2V) + PL2V = (CTDD * 125) / 100 /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -158,23 +156,23 @@ Store ("Set TDP Nominal", Debug) /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 to 1.25 * PL1 */ - Divide (Multiply (CTDN, 125), 100, , PL2V) + PL2V = (CTDN * 125) / 100 /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -305,20 +303,20 @@ // Fix up PCI memory region // Start with Top of Lower Usable DRAM - Store (^MCHC.TLUD, Local0) - ShiftRight (Local0, 4, Local0) - Store (^MCHC.TUUD, Local1) + Local0 = ^MCHC.TLUD + Local0 >>= 4 + Local1 = ^MCHC.TUUD // Check if ME base is equal - If (LEqual (Local0, Local1)) { + If (Local0 == Local1) { // Use Top Of Memory instead - Store (^MCHC.TOM, Local0) - ShiftRight (Local0, 6, Local0) + Local0 = ^MCHC.TOM + Local0 >>= 6 } - ShiftLeft (Local0, 20, Local0) - Store (Local0, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) + Local0 <<= 20 + PMIN = Local0 + PLEN = PMAX - PMIN + 1 Return (MCRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/43154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2771407e5fa2dec5d2b554e53f7ad14cb4a4a4aa Gerrit-Change-Number: 43154 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mbgizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay'
by HAOUAS Elyes (Code Review) 03 Aug '20

03 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44094 ) Change subject: mbgizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay' ...................................................................... mbgizmosphere/gizmo/mainboard.c: Remove white space after 'mdelay' Change-Id: Ib7c6ab0a2e5a03f30b70c4bbb1091fa9c689c23b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44094/1 diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 8046be6..f24c9e9 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -40,7 +40,7 @@ ABAR &= 0xFFFFFC00; memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ *memptr = 0x21; /* force to GEN2 and start re-negotiate */ - mdelay (1); + mdelay(1); *memptr = 0x20; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7c6ab0a2e5a03f30b70c4bbb1091fa9c689c23b Gerrit-Change-Number: 44094 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/gm45/northbridge.c: Use `MiB` definition
by HAOUAS Elyes (Code Review) 03 Aug '20

03 Aug '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44123 ) Change subject: nb/intel/gm45/northbridge.c: Use `MiB` definition ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3 Gerrit-Change-Number: 44123 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 17:12:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit August 2020