coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 04 Aug '20

04 Aug '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36357 ) Change subject: soc/intel/icelake: set LT_LOCK_MEMORY at end of POST ...................................................................... Abandoned SkipMpInit is deprecated from ICL onwards, so the lock gets set by fsp already -- To view, visit https://review.coreboot.org/c/coreboot/+/36357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib728e61bc874acf505348e72c00a99e0a6efd2cb Gerrit-Change-Number: 36357 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 04 Aug '20

04 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: > Patch Set 2: > > > Patch Set 2: Code-Review+1 > > > > Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be > > somewhere between FSP 2.0 and 2.1. > > > > Subrata, do you know what the lack of SkipMpInit for CNL implies? > > SkipMpInit wasn't removed but moved from FSP-S to FSP-M. I checked the FSP binary. It does only set the lock if SkipMpInit=0. I got confirmation from Nate that the FSP-M SkipMpInit does "more or less" the same, as it did before. I should get my CML device by end of the week, so I can do a test on hardware -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nate DeSimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 01:34:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
by Michael Niewöhner (Code Review) 04 Aug '20

04 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 ) Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… File src/soc/intel/cannonlake/finalize.c: https://review.coreboot.org/c/coreboot/+/36356/2/src/soc/intel/cannonlake/f… PS2, Line 116: mp_run_on_all_cpus > given the scope of LT_LOCK_MEMORY (package), this seems unnecessary There is no official/public documentation on this. Multiple leaks set it per-thread, FSP sets it once per package. Experiments at time of writing the patches showed, that setting it per package does not lock TSEGMB and PAVPC properly but only settig it per-thread does. I'd be more than happy to find out what the reason for this behaviour is, but atm this seems to be a valid workaround, that doesn't hurt much. -- To view, visit https://review.coreboot.org/c/coreboot/+/36356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912 Gerrit-Change-Number: 36356 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nate DeSimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 01:33:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Disable TBT DMA1 for TGL UP4
by Bernardo Perez Priego (Code Review) 04 Aug '20

04 Aug '20

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44008 ) Change subject: mb/intel/tglrvp: Disable TBT DMA1 for TGL UP4 ...................................................................... mb/intel/tglrvp: Disable TBT DMA1 for TGL UP4 This device is not enabled for UP4 Change-Id: Icc1bb8b73f499fc5eef06741ab900df71502e1c9 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/44008/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 097ae68..8e0910be 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -164,7 +164,7 @@ device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 on end # USB xDCI (OTG) 0x9A15 device pci 0d.2 on end # TBT DMA0 0x9A1B - device pci 0d.3 on end # TBT DMA1 0x9A1D + device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) -- To view, visit https://review.coreboot.org/c/coreboot/+/44008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1bb8b73f499fc5eef06741ab900df71502e1c9 Gerrit-Change-Number: 44008 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE] mb/asrock/b85m_pro4/devicetree.cb: Make Windows 10 boot
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43763 ) Change subject: [NOTFORMERGE] mb/asrock/b85m_pro4/devicetree.cb: Make Windows 10 boot ...................................................................... [NOTFORMERGE] mb/asrock/b85m_pro4/devicetree.cb: Make Windows 10 boot Magic. Change-Id: I729d24402a14e45e4e1abb87e58e83fb72da9844 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 13 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43763/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index a044d0a..7039be6 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -5,12 +5,12 @@ device cpu_cluster 0 on chip cpu/intel/haswell - register "c1_acpower" = "1" - register "c1_battery" = "1" - register "c2_acpower" = "3" - register "c2_battery" = "3" - register "c3_acpower" = "5" - register "c3_battery" = "5" + register "c1_acpower" = "0" + register "c1_battery" = "0" + register "c2_acpower" = "0" + register "c2_battery" = "0" + register "c3_acpower" = "0" + register "c3_battery" = "0" device lapic 0 on end device lapic 0xacac off end @@ -21,39 +21,30 @@ subsystemid 0x1849 0x0c00 inherit device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe graphics + device pci 01.0 off end # PCIe graphics device pci 02.0 on end # iGPU - device pci 03.0 on end # Mini-HD audio + device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x80" - register "pirqc_routing" = "0x83" - register "pirqd_routing" = "0x8a" - register "pirqe_routing" = "0x83" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x8b" - register "pirqh_routing" = "0x8a" register "sata_ahci" = "1" register "sata_port_map" = "0x3f" device pci 14.0 on end # xHCI controller - device pci 16.0 on end # MEI #1 + device pci 16.0 off end # MEI #1 device pci 16.1 off end # MEI #2 device pci 16.2 off end # ME IDE-R - device pci 16.3 on end # ME KT + device pci 16.3 off end # ME KT device pci 19.0 on end # Intel GbE through I217-V PHY device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio - device pci 1c.0 on end # RP #1: ASM1083 PCI bridge + device pci 1b.0 off end # HD Audio + device pci 1c.0 off end # RP #1: ASM1083 PCI bridge device pci 1c.1 off end # RP #2 device pci 1c.2 off end # RP #3 device pci 1c.3 off end # RP #4 - device pci 1c.4 on end # RP #5: PCIe x16 (electrical x4) + device pci 1c.4 off end # RP #5: PCIe x16 (electrical x4) device pci 1d.0 on end # EHCI #1 device pci 1f.0 on # LPC bridge - chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel -- To view, visit https://review.coreboot.org/c/coreboot/+/43763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I729d24402a14e45e4e1abb87e58e83fb72da9844 Gerrit-Change-Number: 43763 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Add debug print
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43778 ) Change subject: sb/intel/lynxpoint: Add debug print ...................................................................... sb/intel/lynxpoint: Add debug print Sometimes, `root_port_commit_config` may not get called, leaving the PCH PCIe root ports partially initialized. Windows 10 BSODs with a rather unhelpful message when this happens. To ease debugging, always print an easily-greppable message when the problematic function gets called. Change-Id: Icf53c17a207755b1d8d3e9e895e06c95a4f47b6a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/43778/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d2950e7..9d4dc19 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -267,6 +267,8 @@ { int i; + printk(BIOS_DEBUG, "%s: Finishing PCIe initialization\n", __func__); + /* If the first root port is disabled the coalesce ports. */ if (!is_rp_enabled(1)) rpc.coalesce = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/43778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf53c17a207755b1d8d3e9e895e06c95a4f47b6a Gerrit-Change-Number: 43778 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Michael Niewöhner (Code Review) 04 Aug '20

04 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44137 ) Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/44137/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44137/3//COMMIT_MSG@14 PS3, Line 14: it's > its Done https://review.coreboot.org/c/coreboot/+/44137/3//COMMIT_MSG@21 PS3, Line 21: relation to the current workload. > On what device? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Gerrit-Change-Number: 44137 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 22:41:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: acpi: drop HWP's dependency on EIST
by Michael Niewöhner (Code Review) 04 Aug '20

04 Aug '20

Hello Felix Singer, Matt Delco, build bot (Jenkins), Nico Huber, Paul Menzel, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44137 to look at the new patch set (#4). Change subject: soc/intel/skylake: acpi: drop HWP's dependency on EIST ...................................................................... soc/intel/skylake: acpi: drop HWP's dependency on EIST Enhanced Intel SpeedStep Technology (EIST) and Intel Speed Shift Technology (ISST) - also know as HWP - are two independent mechanisms for controlling voltage and frequency based on performance hints. When HWP is enabled, it overrides the software-based EIST. It does not depend on EIST, though, but can be enabled on its own. Break up that currently existing dependency in ACPI generation code. It was tested that HWP can be enabled and gets used by the Linux pstate cpufreq driver. With HWP disabled, the frequency does not decrease, even not in powersave mode. After enabling HWP the frequency changed in relation to the current workload. (Test device: Acer ES1-572) Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/acpi.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44137/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d888ddce7b54e91b54e5b4fdd4d9cf16630eda Gerrit-Change-Number: 44137 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Include Alderlake device IDs
by Paul Menzel (Code Review) 04 Aug '20

04 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alderlake device IDs ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/44108/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44108/1//COMMIT_MSG@9 PS1, Line 9: Alderlake Alder Lake -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 03 Aug 2020 22:18:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Alderlake device IDs
by Tim Wawrzynczak (Code Review) 04 Aug '20

04 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44108 ) Change subject: soc/intel/common: Include Alderlake device IDs ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/44108/1/src/include/device/pci_ids… File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/44108/1/src/include/device/pci_ids… PS1, Line 3627: #define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff : #define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_1 0x4601 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_2 0x4602 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_3 0x4603 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_4 0x4610 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_5 0x4611 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_6 0x4612 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_7 0x4613 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_8 0x4618 : #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 Does the lack of _P_ or _S_ mean these could belong to either an ADL-P or an ADL-S ? https://review.coreboot.org/c/coreboot/+/44108/1/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/44108/1/src/soc/intel/common/block… PS1, Line 78: } same here 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/44108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2 Gerrit-Change-Number: 44108 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Aug 2020 22:18:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020