Hello build bot (Jenkins), Tim Wawrzynczak, Duncan Laurie, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/volteer: Pull up GPP_D16 instead of driving it
......................................................................
mb/google/volteer: Pull up GPP_D16 instead of driving it
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh(a)chromium.org>
---
M src/mainboard/google/volteer/variants/volteer/gpio.c
M src/mainboard/google/volteer/variants/volteer2/gpio.c
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44116/2
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Gerrit-Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Gerrit-Change-Number: 44116
Gerrit-PatchSet: 2
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Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44117 )
Change subject: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table
......................................................................
Patch Set 1:
> Patch Set 1:
>
> This is missing changes for baseboard, Halvor, and Trondo. They each export their own early_gpio_table under certain conditions.
what changes would you like to see for those boards?
if GPP_D16 is not listed in gpio_table[] or a no-connect,
then it should not need to be in early_gpio_table[].
trondo GPIO definitions are still WIP,
to there's nothing to update.
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43071 )
Change subject: device/pci_rom: Fix rom_header structure
......................................................................
Patch Set 2:
This change is ready for review.
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Gerrit-Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584
Gerrit-Change-Number: 43071
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Gerrit-Comment-Date: Tue, 04 Aug 2020 06:41:08 +0000
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43070
to look at the new patch set (#2).
Change subject: device/pci_rom: DISPLAY_3D class is also valid
......................................................................
device/pci_rom: DISPLAY_3D class is also valid
The DISPLAY_3D class is for graphics devices that are not connected to displays.
This includes GPUs implementing muxless Nvidia Optimus.
Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4
Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com>
---
M src/device/pci_rom.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43070/2
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43070 )
Change subject: device/pci_rom: DISPLAY_3D class is also valid
......................................................................
Patch Set 1:
This change is ready for review.
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Gerrit-Comment-Date: Tue, 04 Aug 2020 06:31:20 +0000
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Balaji Manigandan, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44108
to look at the new patch set (#2).
Change subject: soc/intel/common: Include Alder Lake device IDs
......................................................................
soc/intel/common: Include Alder Lake device IDs
Add Alder Lake specific CPU, System Agent, PCH, IGD device IDs.
Document Number: 619501, 619362
Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/include/intelblocks/mp_init.h
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
19 files changed, 447 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/44108/2
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Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44058 )
Change subject: soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
......................................................................
soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated
FSP default UPD for SkipMpInit is set to 0 which refers to run CPU
feature programming on all cores (BSP + APs).
Setting SkipMpInit=1 is not recommended as it will only limit CPU
feature programming on BSP.
TEST=Able to perform CPU feature programming by FSP on all cores
using external MP PPI services.
Change-Id: I22e70f5f15e53c5fabd78cc3698c4d718b607af6
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/jasperlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
3 files changed, 2 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/44058/1
diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c
index e3d355d..d4485c6 100644
--- a/src/soc/intel/icelake/fsp_params.c
+++ b/src/soc/intel/icelake/fsp_params.c
@@ -73,8 +73,6 @@
/* Mandatory to make use of CpuMpPpi implementation from ICL onwards */
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
- /* TODO: Remove me as SkipMpInit is getting deprecated */
- params->SkipMpInit = 0;
mainboard_silicon_init_params(params);
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 204364b..92ac5b8 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -96,12 +96,8 @@
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Use coreboot MP PPI services if Kconfig is enabled */
- if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
- params->SkipMpInit = 0;
- } else {
- params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
- }
/* Chipset Lockdown */
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 517d771..a61a025 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -104,12 +104,8 @@
params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
/* Use coreboot MP PPI services if Kconfig is enabled */
- if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
- params->SkipMpInit = 0;
- } else {
- params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
- }
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = !config->TcssD3HotDisable;
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