coreboot-gerrit August 2020

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Change in coreboot[master]: device/pci_rom.c: Treat BASE_DISPLAY class as GPU
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43070 ) Change subject: device/pci_rom.c: Treat BASE_DISPLAY class as GPU ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Gerrit-Change-Number: 43070 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Aug 2020 09:53:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_rom.c: Treat BASE_DISPLAY class as GPU
by Benjamin Doron (Code Review) 04 Aug '20

04 Aug '20

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43070 to look at the new patch set (#3). Change subject: device/pci_rom.c: Treat BASE_DISPLAY class as GPU ...................................................................... device/pci_rom.c: Treat BASE_DISPLAY class as GPU The DISPLAY_3D class is for graphics devices that are not connected to displays. This includes GPUs implementing muxless Nvidia Optimus. According to CB:31502, some AMD GPUs are identified as DISPLAY_OTHER. Therefore, consider the entire DISPLAY class as GPUs. Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/device/pci_rom.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/43070/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/43070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Gerrit-Change-Number: 43070 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Benjamin Doron (Code Review) 04 Aug '20

04 Aug '20

Hello build bot (Jenkins), Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38318 to look at the new patch set (#9). Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... soc/intel/skylake: Call mainboard ACPI sleep methods Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on a Skylake-U laptop. Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/platform.asl 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38318/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device/pci_rom: DISPLAY_3D class is also valid
by Patrick Rudolph (Code Review) 04 Aug '20

04 Aug '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43070 ) Change subject: device/pci_rom: DISPLAY_3D class is also valid ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Gerrit-Change-Number: 43070 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Aug 2020 08:28:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40625 ) Change subject: [WIP] skl: PEG for Optimus ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/40625/9/src/soc/intel/skylake/acpi… File src/soc/intel/skylake/acpi/peg.asl: https://review.coreboot.org/c/coreboot/+/40625/9/src/soc/intel/skylake/acpi… PS9, Line 14: PCIe Root Port *PCH* PCIe Root Port -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 9 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 07:58:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_rom: DISPLAY_3D class is also valid
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43070 ) Change subject: device/pci_rom: DISPLAY_3D class is also valid ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/43070/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43070/2//COMMIT_MSG@7 PS2, Line 7: device/pci_rom: DISPLAY_3D class is also valid device/pci_rom.c: Also treat DISPLAY_3D class as GPU -- To view, visit https://review.coreboot.org/c/coreboot/+/43070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4 Gerrit-Change-Number: 43070 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Aug 2020 07:56:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Benjamin Doron (Code Review) 04 Aug '20

04 Aug '20

Hello build bot (Jenkins), Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/38318 to look at the new patch set (#7). Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... soc/intel/skylake: Call mainboard ACPI sleep methods Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on a Skylake-U laptop. Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/platform.asl 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38318/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Angel Pons (Code Review) 04 Aug '20

04 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Aug 2020 07:31:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/i440bx: Avoid ROM area
by Keith Hui (Code Review) 04 Aug '20

04 Aug '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41091 ) Change subject: nb/intel/i440bx: Avoid ROM area ...................................................................... nb/intel/i440bx: Avoid ROM area Declare the ROM area to be read only in ACPI, and excludes it from ranges available for MMIO. Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/acpi/i440bx.asl M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 2 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41091/1 diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl index e1e4e61..70c3aaa 100644 --- a/src/northbridge/intel/i440bx/acpi/i440bx.asl +++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl @@ -26,10 +26,26 @@ 0x00100000, // Address Base 0x00000000, // Address Length _Y00) + /* Reserved for firmware flash */ + Memory32Fixed (ReadOnly, + 0x100000000 - CONFIG_ROM_SIZE, // Address Base + CONFIG_ROM_SIZE, // Address Length + _Y01) }) CreateDWordField (BUF1, _Y00._LEN, EMLN) // _LEN: Length + CreateDWordField (BUF1, _Y01._BAS, FLSB) // _BAS: Base + /* + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + + /* Top of 4GB */ + ShiftLeft(0x10000000, 4, Local0) + FLSB = Local0 - CONFIG_ROM_SIZE; EMLN = \_SB.PCI0.NB.TOM1 - 0x100000; - Return (BUF1) + Return (BUF1) /* \_SB_.MEM1._CRS.BUF1 */ } } diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index e40b1fc..fa5948f 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -61,6 +61,7 @@ */ MM1B = \_SB.PCI0.NB.TOM1 ShiftLeft(0x10000000, 4, Local0) + Local0 -= CONFIG_ROM_SIZE MM1L = Local0 - MM1B Return(TMP) -- To view, visit https://review.coreboot.org/c/coreboot/+/41091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Gerrit-Change-Number: 41091 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/lib: Remove unused function parameter in imd.c
by Anna Karaś (Code Review) 04 Aug '20

04 Aug '20

Anna Karaś has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43999 ) Change subject: src/lib: Remove unused function parameter in imd.c ...................................................................... src/lib: Remove unused function parameter in imd.c Remove const struct imdr *imdr parameter from the prototypes of imdr_entry_size(), imd_entry_size() and imd_entry_id() functions since it is not used anywhere. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 --- M src/include/imd.h M src/lib/ext_stage_cache.c M src/lib/imd.c M src/lib/imd_cbmem.c 4 files changed, 14 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43999/1 diff --git a/src/include/imd.h b/src/include/imd.h index 314d223..7abbb98 100644 --- a/src/include/imd.h +++ b/src/include/imd.h @@ -102,13 +102,13 @@ uint32_t id, size_t size); /* Returns size of entry or 0 on failure. */ -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); +size_t imd_entry_size(const struct imd_entry *entry); /* Returns pointer to region described by entry or NULL on failure. */ void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); /* Returns id for the imd entry. */ -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry); +uint32_t imd_entry_id(const struct imd_entry *entry); /* Attempt to remove entry from imd. */ int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2fb1e9e..d498597 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -111,7 +111,7 @@ } *base = imd_entry_at(imd, e); - *size = imd_entry_size(imd, e); + *size = imd_entry_size(e); } void stage_cache_load_stage(int stage_id, struct prog *stage) @@ -141,7 +141,7 @@ } c = imd_entry_at(imd, e); - size = imd_entry_size(imd, e); + size = imd_entry_size(e); memcpy((void *)(uintptr_t)meta->load_addr, c, size); diff --git a/src/lib/imd.c b/src/lib/imd.c index e19c03d..be4a786 100644 --- a/src/lib/imd.c +++ b/src/lib/imd.c @@ -288,8 +288,7 @@ return 0; } -static size_t imdr_entry_size(const struct imdr *imdr, - const struct imd_entry *e) +static size_t imdr_entry_size(const struct imd_entry *e) { return e->size; } @@ -409,7 +408,7 @@ return; imd->sm.limit = (uintptr_t)imdr_entry_at(imdr, e); - imd->sm.limit += imdr_entry_size(imdr, e); + imd->sm.limit += imdr_entry_size(e); imdr = &imd->sm; rp = imdr_get_root_pointer(imdr); imdr->r = relative_pointer(rp, rp->root_offset); @@ -474,7 +473,7 @@ return 0; small_upper_limit = (uintptr_t)imdr_entry_at(imdr, e); - small_upper_limit += imdr_entry_size(imdr, e); + small_upper_limit += imdr_entry_size(e); imd->sm.limit = small_upper_limit; @@ -592,9 +591,9 @@ return imd_entry_add(imd, id, size); } -size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry) +size_t imd_entry_size(const struct imd_entry *entry) { - return imdr_entry_size(NULL, entry); + return imdr_entry_size(entry); } void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) @@ -609,7 +608,7 @@ return imdr_entry_at(imdr, entry); } -uint32_t imd_entry_id(const struct imd *imd, const struct imd_entry *entry) +uint32_t imd_entry_id(const struct imd_entry *entry) { return entry->id; } @@ -671,7 +670,7 @@ printk(BIOS_DEBUG, "%s", name); printk(BIOS_DEBUG, "%2zu. ", i); printk(BIOS_DEBUG, "%p ", imdr_entry_at(imdr, e)); - printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(imdr, e)); + printk(BIOS_DEBUG, "0x%08zx\n", imdr_entry_size(e)); } } diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index cb66c3b..7638e0e 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -178,7 +178,7 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry) { - return imd_entry_size(&imd, cbmem_to_imd(entry)); + return imd_entry_size(cbmem_to_imd(entry)); } void *cbmem_entry_start(const struct cbmem_entry *entry) @@ -232,7 +232,7 @@ if (e == NULL) break; - id = imd_entry_id(&imd, e); + id = imd_entry_id(e); /* Don't add these metadata entries. */ if (id == CBMEM_ID_IMD_ROOT || id == CBMEM_ID_IMD_SMALL) continue; @@ -241,7 +241,7 @@ lbe->tag = LB_TAG_CBMEM_ENTRY; lbe->size = sizeof(*lbe); lbe->address = (uintptr_t)imd_entry_at(&imd, e); - lbe->entry_size = imd_entry_size(&imd, e); + lbe->entry_size = imd_entry_size(e); lbe->id = id; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/43999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b43e9a5ae1f1d108024b4060a04c57f5d77fb55 Gerrit-Change-Number: 43999 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karaś <aka(a)semihalf.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020