Change in coreboot[master]: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44069 )
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.
Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44069/1
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 9c0e3e9..12e52fc 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -123,7 +123,16 @@ * GPP[5:4] | [1:0] | PCIe, XGBE * GPP[7:6] | [3:2] | PCIe, SATA * - * Dali has less DXIO connectivity than Picasso: + * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port + * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 + * ports. The ports can only start at logical lane numbers that are integer multiples of the + * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. + * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the + * same width the one with a higher start logical lane number needs to be assigned to a higher + * PCIe root port number; ports of the same size don't have to be assigned to continious PCIe + * root ports though. + * + * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: * * physical | logical | protocol * ---------|---------|-----------
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44069 )
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44069/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44069/1/src/vendorcode/amd/fsp/pica... PS1, Line 132: continious `continous`? You probably want `consecutive` though
Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Angel Pons, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44069
to look at the new patch set (#2).
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.
Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44069/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44069 )
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44069/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/44069/1/src/vendorcode/amd/fsp/pica... PS1, Line 132: continious
`continous`? You probably want `consecutive` though
good. point. Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44069 )
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
Patch Set 2: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44069 )
Change subject: vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments ......................................................................
vc/amd/fsp/picasso: document requirements for DXIO PCIe port assignments
Also document the maximum nuber of lanes for the different platforms.
Change-Id: I52356d4bbb407ee8a36fce18ad94d73f39c01345 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44069 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 10 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 9c0e3e9..d5977ef 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -123,7 +123,16 @@ * GPP[5:4] | [1:0] | PCIe, XGBE * GPP[7:6] | [3:2] | PCIe, SATA * - * Dali has less DXIO connectivity than Picasso: + * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port + * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 + * ports. The ports can only start at logical lane numbers that are integer multiples of the + * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. + * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the + * same width the one with a higher start logical lane number needs to be assigned to a higher + * PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe + * root ports though. + * + * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: * * physical | logical | protocol * ---------|---------|-----------
-
Angel Pons (Code Review) -
Felix Held (Code Review)