coreboot-gerrit July 2020

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Change in coreboot[master]: mb/lenovo/t60: Fix override devicetrees
by Nico Huber (Code Review) 07 Jul '20

07 Jul '20

Hello Peter Lemenkov, Angel Pons, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43150 to review the following change. Change subject: mb/lenovo/t60: Fix override devicetrees ...................................................................... mb/lenovo/t60: Fix override devicetrees When converting to override trees in c1dc2d5e68 (mb/lenovo/t60: Switch to override tree), some device nodes were missed. These are essential, as `chip` configuration data is always tied to device nodes. The resulting `static.c` contained multiple copies of the `chip` configuration structs, but the wrong ones were hooked up. Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/lenovo/t60/variants/t60/overridetree.cb M src/mainboard/lenovo/t60/variants/z61t/overridetree.cb 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/43150/1 diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb index dc6abfb..c58884a 100644 --- a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -29,6 +29,7 @@ register "has_bdc_detection" = "1" register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" + device pnp ff.2 on end end chip superio/nsc/pc87384 device pnp 2e.2 off # Serial Port / IR @@ -47,6 +48,7 @@ register "regs" = "{ 0x2e, 0xf7, 0x3c, 0x20, 0x01, 0x00, 0x1b, 0x01, 0x54, 0xff, 0xff, 0x07 }" + device i2c 69 on end end end end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb index 9bac582..00f3f19 100644 --- a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -42,6 +42,7 @@ # vendor clockgen setup register "regs" = "{ 0x6d, 0xff, 0xff, 0x20, 0x41, 0x7f, 0x18, 0x00 }" + device i2c 69 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/43150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad Gerrit-Change-Number: 43150 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service
by John Zhao (Code Review) 07 Jul '20

07 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40968 ) Change subject: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service ...................................................................... soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service Vt-d based security platform requires the system firmware to clear bus master enable(BME) bit for all Thunderbolt PCIe root ports, bridges and devices at exit boot service. In this state with BME bit cleared, the PCI root ports would be considered as trusted to not forward any DMA transaction to download endpoint devices. BUG=141609884 TEST=built image and booted to kernel successfully. Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/tigerlake/chip.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/40968/1 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 073c8d2..a0007f3 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/acpi.h> @@ -15,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -114,6 +116,48 @@ gpio_pm_configure(value, TOTAL_GPIO_COMM); } +static void clear_tbt_pcie_rp_bme(struct device *dev, uint16_t device_id) +{ + uint16_t reg16; + + if (dev) { + if ((pci_read_config16(dev, PCI_DEVICE_ID) == device_id)) { + reg16 = pci_read_config16(dev, PCI_COMMAND); + + /* Check if BME bit is enabled before */ + if ((reg16 & PCI_COMMAND_MASTER) == PCI_COMMAND_MASTER) { + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + } + } + } +} + +void platform_fsp_notify_status(enum fsp_notify_phase phase) +{ + if (phase == END_OF_FIRMWARE) { + struct device *dev; + + /* Check if VT-d is enabled */ + dev = pcidev_path_on_root(SA_DEVFN_ROOT); + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + /* Clear Thunderbolt PCIe root ports Bus Master Enable(BME) bit */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP0); + + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP1); + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP2); + + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP3); + } +} + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a -- To view, visit https://review.coreboot.org/c/coreboot/+/40968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b Gerrit-Change-Number: 40968 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

15 68

Change in coreboot[4.11_branch]: mb/facebook/watson: select VPD_SMBIOS_VERSION
by Jonathan Zhang (Code Review) 07 Jul '20

07 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42942 ) Change subject: mb/facebook/watson: select VPD_SMBIOS_VERSION ...................................................................... mb/facebook/watson: select VPD_SMBIOS_VERSION Select VPD, GENERATE_SMBIOS_TABLES, VPD_SMBIOS_VERSION so that "firmware_version" key value in RO_VPD is reported in smbios type 0 as BIOS version. TEST=Build coreboot image for WatsonV2, run "vpd -s firmware_version=FB_OSF_1.2 -i RO_VPD -f build/coreboot.rom" command to add firmware_version key value pair in RO_VPD, flash the image to WatsonV2 and reboot it, run dmidecode to verify: [root@localhost ~]# dmidecode -t 0 ... BIOS Information Vendor: coreboot Version: FB_OSF_1.2 ... Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Id559904bfc0afec0668cfaa28303242da4fccf5c temp Change-Id: I31fb2cef01161175a0c01094c5445f7fa340f2d0 --- M src/mainboard/facebook/watson/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42942/1 diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index f8f93df..2ebc020 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -12,6 +12,7 @@ def_bool y select SOC_INTEL_FSP_BROADWELL_DE select BOARD_ROMSIZE_KB_16384 + select GENERATE_SMBIOS_TABLES select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEGRATED_UART @@ -24,6 +25,8 @@ select VBOOT if BOARD_FACEBOOK_WATSON_V2 select VBOOT_MEASURED_BOOT if BOARD_FACEBOOK_WATSON_V2 select VBOOT_STARTS_IN_ROMSTAGE if BOARD_FACEBOOK_WATSON_V2 + select VPD + select VPD_SMBIOS_VERSION config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/42942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I31fb2cef01161175a0c01094c5445f7fa340f2d0 Gerrit-Change-Number: 42942 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: src/include: improve the description of hexstrtobin
by Anna Karaś (Code Review) 07 Jul '20

07 Jul '20

Anna Karaś has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43089 ) Change subject: src/include: improve the description of hexstrtobin ...................................................................... src/include: improve the description of hexstrtobin Specify how hexstrtobin.c processes the strings of odd length. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a --- M src/include/lib.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/43089/1 diff --git a/src/include/lib.h b/src/include/lib.h index 0d6fdb1..46d8b02 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -40,6 +40,8 @@ * * Defined in src/lib/hexstrtobin.c * Ignores non-hex characters in the string. + * Ignores the last hex character if the number of hex characters in the string + * is odd. * Returns the number of bytes that have been put in the buffer. */ size_t hexstrtobin(const char *str, uint8_t *buf, size_t len); -- To view, visit https://review.coreboot.org/c/coreboot/+/43089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8cd8fb93d7dab08c5e7f28fc511b6381f5ad13a Gerrit-Change-Number: 43089 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karaś <aka(a)semihalf.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: tests: Add lib/hexstrtobin-test test case
by Anna Karaś (Code Review) 07 Jul '20

07 Jul '20

Anna Karaś has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43088 ) Change subject: tests: Add lib/hexstrtobin-test test case ...................................................................... tests: Add lib/hexstrtobin-test test case Implement unit tests for lib/hexstrtobin module. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: Id929b07936ea180a798309e5acb1dacf1b396e32 --- M tests/lib/Makefile.inc A tests/lib/hexstrtobin-test.c 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/43088/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 5d47fea..594c68e 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -2,9 +2,13 @@ tests-y += string-test tests-y += b64_decode-test +tests-y += hexstrtobin-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c b64_decode-test-srcs += tests/lib/b64_decode-test.c b64_decode-test-srcs += src/lib/b64_decode.c + +hexstrtobin-test-srcs += tests/lib/hexstrtobin-test.c +hexstrtobin-test-srcs += src/lib/hexstrtobin.c diff --git a/tests/lib/hexstrtobin-test.c b/tests/lib/hexstrtobin-test.c new file mode 100644 index 0000000..419ffe9 --- /dev/null +++ b/tests/lib/hexstrtobin-test.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <string.h> +#include <lib.h> +#include <stdint.h> +#include <tests/test.h> + +struct hexstr_t { + char *str; + int val[2]; + size_t res; +} hexstr[] = { + {"277a", {39, 122}, 2}, + + /* This example should give us similar result as the one above, + although it is one hex character longer. */ + {"277ab", {39, 122}, 2}, + {"\nB*e/ef-", {190, 239}, 2}, +}; + +static void test_hexstrtobin(void **state) +{ + uint8_t *buf; + size_t res, len; + + for (int i = 0; i < ARRAY_SIZE(hexstr); i++) { + len = strlen(hexstr[i].str) / 2 + 1; + buf = malloc(len); + res = hexstrtobin(hexstr[i].str, buf, len); + + assert_int_equal(hexstr[i].res, res); + + for (int j = 0; j < res; j++) { + assert_int_equal(hexstr[i].val[j], buf[j]); + } + + free(buf); + } +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_hexstrtobin), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id929b07936ea180a798309e5acb1dacf1b396e32 Gerrit-Change-Number: 43088 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karaś <aka(a)semihalf.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/google/vilboz: update GPIOs, gpio.c is unnecessary
by Peichao Li (Code Review) 07 Jul '20

07 Jul '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42986 ) Change subject: mb/google/vilboz: update GPIOs, gpio.c is unnecessary ...................................................................... mb/google/vilboz: update GPIOs, gpio.c is unnecessary Vilboz is completely new design so gpio.c is unnecessary Delcare: --AGPIO6 for EN_PWR_TOUCHPAD --EGPIO67 for DMIC_SEL BUG=b:157744136 BRANCH=NONE TEST=flash the bios to vilboz DUT and test thest functions Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801 --- M src/mainboard/google/zork/variants/vilboz/Makefile.inc D src/mainboard/google/zork/variants/vilboz/gpio.c 2 files changed, 0 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/42986/1 diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index af38c88..dc1e411 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -3,4 +3,3 @@ subdirs-y += ./spd ramstage-y += variant.c -ramstage-y += gpio.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c deleted file mode 100644 index 44d3f89..0000000 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/gpio.h> -#include <baseboard/variants.h> -#include <boardid.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <ec/google/chromeec/ec.h> - -/* This table is used by dalboz variant with board version < 2. */ -static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { - /* DMIC_SEL */ - PAD_GPO(GPIO_6, LOW), // Select Camera 1 DMIC - /* EN_PWR_TOUCHPAD_PS2 */ - PAD_GPO(GPIO_67, HIGH), -}; - -const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) -{ - uint32_t board_version; - - /* - * If board version cannot be read, assume that this is an older revision of the board - * and so apply overrides. If board version is provided by the EC, then apply overrides - * if version < 2. - */ - if (google_chromeec_cbi_get_board_version(&board_version)) - board_version = 1; - - if (board_version < 2) { - *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram); - return bid_1_gpio_set_stage_ram; - } - - *size = 0; - return NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801 Gerrit-Change-Number: 42986 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: b/google/vilboz: enable wifi module
by Peichao Li (Code Review) 07 Jul '20

07 Jul '20

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43161 ) Change subject: b/google/vilboz: enable wifi module ...................................................................... b/google/vilboz: enable wifi module At this moment Vilboz board version is 1, so we need to configure it BUG=b:160547115 BRANCH=None TEST=flash the bios to vilboz DUT and test WIFI module Signed-off-by: peichao.wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997 --- M src/mainboard/google/zork/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/43161/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index e24f78a..19225d7 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -142,13 +142,13 @@ default 3 if BOARD_GOOGLE_MORPHIUS default 2 if BOARD_GOOGLE_BERKNIP default 3 if BOARD_GOOGLE_DALBOZ - default 2 if BOARD_GOOGLE_VILBOZ + default 1 if BOARD_GOOGLE_VILBOZ default 256 config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW int default 3 if BOARD_GOOGLE_BERKNIP - default 3 if BOARD_GOOGLE_VILBOZ + default 2 if BOARD_GOOGLE_VILBOZ default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ -- To view, visit https://review.coreboot.org/c/coreboot/+/43161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997 Gerrit-Change-Number: 43161 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
by John Zhao (Code Review) 07 Jul '20

07 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42953 ) Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ...................................................................... mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42953/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index e4d605e..cfebc6b 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..4a7698c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -254,7 +254,27 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 + device pci 1f.2 hidden # PMC 0xA0A1 + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "6" + register "usb3_port_number" = "3" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "7" + register "usb3_port_number" = "4" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4 -- To view, visit https://review.coreboot.org/c/coreboot/+/42953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 Gerrit-Change-Number: 42953 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: mb/google/volteer: Change ov2740 HID to match with Windows definition
by Daniel Kang (Code Review) 07 Jul '20

07 Jul '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43006 ) Change subject: mb/google/volteer: Change ov2740 HID to match with Windows definition ...................................................................... mb/google/volteer: Change ov2740 HID to match with Windows definition Change HID of ov2740 to INT3474 so that it matches with the Windows defintion. BUG=b:160334865 BRANCH=none TEST=User-facing camera should work with the driver which set the HID as INT3474 Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43006/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index 9f7b3e0..dad762a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -495,7 +495,7 @@ Device (CAM1) { - Name (_HID, "OVTI2740") /* _HID: Hardware ID */ + Name (_HID, "INT3474") /* _HID: Hardware ID */ Name (_UID, Zero) /* _UID: Unique ID */ Name (_DDN, "Ov 2740 Camera") /* _DDN: DOS Device Name */ Method (_STA, 0, NotSerialized) /* _STA: Status */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37 Gerrit-Change-Number: 43006 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Fix world-facing camera LED is alway on issue
by Daniel Kang (Code Review) 07 Jul '20

07 Jul '20

Daniel Kang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42985 ) Change subject: mb/google/volteer: Fix world-facing camera LED is alway on issue ...................................................................... mb/google/volteer: Fix world-facing camera LED is alway on issue Volteer world-facing camera has a privacy LED and it is supposed to be turned on only when the camera is being used. But the LED is always on and this is to fix the issue. BUG=b:160341981 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check the world-facing camera LED is only turned on only when the camera is working. Signed-off-by: Daniel Kang <daniel.h.kang(a)intel.com> Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02 --- M src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/42985/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl index a5756626..9f7b3e0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/mipi_camera.asl @@ -163,6 +163,9 @@ CTXS(GPP_D4) #endif + /* Pull SNRPWR_EN high */ + STXS(GPP_H14) + /* Pull PWREN high */ STXS(GPP_H20) Sleep(2) /* reset pulse width */ @@ -196,6 +199,9 @@ /* Pull PWREN low */ CTXS(GPP_H20) + /* Pull SNRPWR_EN low */ + CTXS(GPP_H14) + Store(0,STA) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02 Gerrit-Change-Number: 42985 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-MessageType: newchange

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