Change in coreboot[master]: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 22 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42953/1
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index e4d605e..cfebc6b 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..4a7698c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -254,7 +254,27 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 + device pci 1f.2 hidden # PMC 0xA0A1 + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "6" + register "usb3_port_number" = "3" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/con + register "usb2_port_number" = "7" + register "usb3_port_number" = "4" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4
Hello build bot (Jenkins), Wonkyu Kim, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42953
to look at the new patch set (#2).
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 22 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42953/2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/2/src/mainboard/intel/tglrvp/... PS2, Line 265: SBU & HSL follow CC i'm not sure how the tglrvp is configured, but shouldn't this be the same as port 1? i.e. the BB "fixes" the SBU orientation?
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42953
to look at the new patch set (#3).
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42953/3
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/2/src/mainboard/intel/tglrvp/... PS2, Line 265: SBU & HSL follow CC
i'm not sure how the tglrvp is configured, […]
Ack
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/3/src/mainboard/intel/tglrvp/... PS3, Line 262: con jenkins is complaining because we renamed this to "conn" 😊
Hello build bot (Jenkins), Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Duncan Laurie, Shamile Khan, Brandon Breitenstein, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42953
to look at the new patch set (#4).
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42953/4
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/3/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/3/src/mainboard/intel/tglrvp/... PS3, Line 262: con
jenkins is complaining because we renamed this to "conn" 😊
Thanks a lot. I was totally confused.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 4: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/4/src/mainboard/intel/tglrvp/... PS4, Line 266: TYPEC_ORIENTATION_NORMAL just to check, this board has retimers that fix the orientation of the SBU signals?
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42953/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42953/4/src/mainboard/intel/tglrvp/... PS4, Line 266: TYPEC_ORIENTATION_NORMAL
just to check, this board has retimers that fix the orientation of the SBU signals?
yes, it has retimers for all ports.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42953 )
Change subject: mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3 ......................................................................
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953 Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 2 files changed, 23 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index e4d605e..cfebc6b 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_INTEL_PMC select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4550815..4010772 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -254,7 +254,28 @@ device pci 1e.3 off end # GSPI1 0xA0AB device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.1 on end # P2SB 0xA0A0 - device pci 1f.2 hidden end # PMC 0xA0A1 + device pci 1f.2 hidden # PMC 0xA0A1 + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "6" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "7" + register "usb3_port_number" = "4" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.5 on end # SPI 0xA0A4
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Caveh Jalali (Code Review) -
John Zhao (Code Review)
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Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)