coreboot-gerrit July 2020

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Hung-Te Lin (Code Review) 08 Jul '20

08 Jul '20

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 16 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 04:19:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 08 Jul '20

08 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 16: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 16 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 04:11:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: support elan touchpad
by Chen Wisley (Code Review) 08 Jul '20

08 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42922 ) Change subject: mb/google/dedede/var/drawcia: support elan touchpad ...................................................................... mb/google/dedede/var/drawcia: support elan touchpad BUG=155002811 TEST=build drawcia, and check touchpad can work. Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 8 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/42922/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee1abc9..a92dbdb 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -38,15 +38,14 @@ device domain 0 on device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" - register "generic.desc" = ""Synaptics Touchpad"" - register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" - register "generic.wake" = "GPE0_DW0_03" - register "generic.probed" = "1" - register "hid_desc_reg_offset" = "0x20" - device i2c 0x2c on end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW0_03" + register "probed" = "1" + device i2c 15 on end end - end + end #I2C 0 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c Gerrit-Change-Number: 42922 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failu...
by Johnny Lin (Code Review) 08 Jul '20

08 Jul '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43005 ) Change subject: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failure is detected ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/43005/6/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ipmi.h: https://review.coreboot.org/c/coreboot/+/43005/6/src/mainboard/ocp/deltalak… PS6, Line 15: Please remove the space for better alignment. -- To view, visit https://review.coreboot.org/c/coreboot/+/43005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Gerrit-Change-Number: 43005 Gerrit-PatchSet: 6 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Comment-Date: Wed, 08 Jul 2020 00:20:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Determine # of I2C controllers at runtime
by Felix Held (Code Review) 08 Jul '20

08 Jul '20

Hello Raul Rangel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40247 to review the following change. Change subject: soc/amd/common: Determine # of I2C controllers at runtime ...................................................................... soc/amd/common: Determine # of I2C controllers at runtime Dali only has 3 I2C controllers, while Pollock has 5. Both boards use the same socket. So we determine at runtime how many I2C controllers are available. I2C0 and I2C1 are not documented in the PPR, so I took a guess at the addressed. BUG=b:149572620 BRANCH=none TEST=Booted dalboz firmware on trembyle. Saw only three controllers initialized. Touchscreen was still working. Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 --- A src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/iomap.h 6 files changed, 63 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/40247/1 diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h new file mode 100644 index 0000000..f1ffa71 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_I2C_H__ +#define __AMDBLOCKS_I2C_H__ + +#include <device/resource.h> + +/* Some systems can only determine the number of i2c controllers at runtime. */ +void soc_update_i2c_resource(struct resource *res); + +#endif /* __AMDBLOCKS_I2C_H__ */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5346356..e84594b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,6 +16,7 @@ #include <pc80/i8259.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> +#include <amdblocks/i2c.h> #include <soc/acpi.h> #include <soc/southbridge.h> #include <soc/nvs.h> @@ -24,6 +25,8 @@ /* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } +void __weak soc_update_i2c_resource(struct resource *res) { } + static void lpc_init(struct device *dev) { u8 byte; @@ -118,12 +121,14 @@ res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* I2C devices (all 4 devices) */ + /* I2C devices */ res = new_resource(dev, 4); res->base = I2C_BASE_ADDRESS; res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + soc_update_i2c_resource(res); + compact_resources(dev); /* Allocate ACPI NVS in CBMEM */ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5cef9ba..0ded6dd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -42,6 +42,7 @@ bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c +bootblock-y += soc_util.c romstage-y += i2c.c romstage-y += romstage.c diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index b2ff9d8..adc9160 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -9,11 +9,10 @@ #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <arch/acpi_device.h> #include <FspsUpd.h> -#define PICASSO_I2C_DEV_MAX 4 - struct soc_amd_picasso_config { /* * If sb_reset_i2c_slaves() is called, this devicetree register @@ -24,7 +23,7 @@ * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ u8 i2c_scl_reset; - struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; + struct dw_i2c_bus_config i2c[I2C_DEVICE_COUNT]; enum { I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 6bbc7a7..2bd3116 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -7,34 +7,41 @@ #include <delay.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> +#include <soc/i2c.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> -#include <soc/i2c.h> #include "chip.h" /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); static const uintptr_t i2c_bus_address[] = { + APU_I2C0_BASE, + APU_I2C1_BASE, APU_I2C2_BASE, APU_I2C3_BASE, APU_I2C4_BASE, /* slave device only */ }; +_Static_assert(ARRAY_SIZE(i2c_bus_address) == I2C_DEVICE_COUNT, + "ARRAY_SIZE(i2c_bus_address) must equal I2C_DEVICE_COUNT"); + uintptr_t dw_i2c_base_address(unsigned int bus) { - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(i2c_bus_address)) return 0; - return i2c_bus_address[bus - APU_I2C_MIN_BUS]; + return i2c_bus_address[bus]; } const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(config->i2c)) return NULL; config = get_soc_config(); @@ -47,6 +54,10 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + return "I2C0"; + case APU_I2C1_BASE: + return "I2C1"; case APU_I2C2_BASE: return "I2C2"; case APU_I2C3_BASE: @@ -61,6 +72,10 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + return 0; + case APU_I2C1_BASE: + return 1; case APU_I2C2_BASE: return 2; case APU_I2C3_BASE: @@ -73,6 +88,14 @@ __weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } +/* Pollock has access to I2C0 and I2C1. */ +static unsigned int i2c_start_index(void) +{ + if (soc_is_pollock()) + return 0; + return 2; +} + static void dw_i2c_soc_init(bool is_early_init) { size_t i; @@ -85,7 +108,7 @@ if (config == NULL) return; - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { + for (i = i2c_start_index(); i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; if (cfg->early_init != is_early_init) @@ -126,6 +149,15 @@ dw_i2c_soc_init(false); } +void soc_update_i2c_resource(struct resource *res) +{ + unsigned int index = i2c_start_index(); + unsigned int count = ARRAY_SIZE(i2c_bus_address) - index; + + res->base = dw_i2c_base_address(index); + res->size = I2C_DEVICE_SIZE * count; +} + struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 0a6e1a1..3f539a2 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,15 +18,15 @@ /* Reserved 0xfecd1000-0xfedc3fff */ +/* I2C0 and I2C1 are only available on Pollock */ +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_BASE_ADDRESS APU_I2C0_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 +#define I2C_DEVICE_COUNT 5 #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 -- To view, visit https://review.coreboot.org/c/coreboot/+/40247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Gerrit-Change-Number: 40247 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: google/trogdor: Add new variant Pompom
by Julius Werner (Code Review) 08 Jul '20

08 Jul '20

Hello Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43147 to review the following change. Change subject: google/trogdor: Add new variant Pompom ...................................................................... google/trogdor: Add new variant Pompom This patch adds a new variant called Pompom that is identical to Lazor for now. Also reorder variants alphabetically while we're here. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c --- M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/Kconfig.name 2 files changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/43147/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index dfd98f0..5feee22 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -49,8 +49,9 @@ config MAINBOARD_PART_NUMBER string - default "Trogdor" if BOARD_GOOGLE_TROGDOR - default "Lazor" if BOARD_GOOGLE_LAZOR default "Bubs" if BOARD_GOOGLE_BUBS + default "Lazor" if BOARD_GOOGLE_LAZOR + default "Pompom" if BOARD_GOOGLE_POMPOM + default "Trogdor" if BOARD_GOOGLE_TROGDOR endif # BOARD_GOOGLE_TROGDOR_COMMON diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index 7be1a2d..b7c03f9 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -1,13 +1,17 @@ comment "Trogdor" -config BOARD_GOOGLE_TROGDOR - bool "Trogdor" +config BOARD_GOOGLE_BUBS + bool "Bubs" select BOARD_GOOGLE_TROGDOR_COMMON config BOARD_GOOGLE_LAZOR bool "Lazor" select BOARD_GOOGLE_TROGDOR_COMMON -config BOARD_GOOGLE_BUBS - bool "Bubs" +config BOARD_GOOGLE_POMPOM + bool "Pompom" + select BOARD_GOOGLE_TROGDOR_COMMON + +config BOARD_GOOGLE_TROGDOR + bool "Trogdor" select BOARD_GOOGLE_TROGDOR_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/43147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c Gerrit-Change-Number: 43147 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/samsung/exynos5250: Drop dead code
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43253 ) Change subject: soc/samsung/exynos5250: Drop dead code ...................................................................... soc/samsung/exynos5250: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I0a3a0c7453753c069f1106067fc12547da842d66 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/uart.c 2 files changed, 0 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43253/1 diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index 029171ef..f415020 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -19,20 +19,6 @@ write32(&exynos_clock->lpddr3phy_ctrl, LPDDR3PHY_CTRL_PHY_RESET_DISABLE); -#if 0 - /* - * For proper memory initialization there should be a minimum delay of - * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal. - * The below value is an approximate value whose calculation in done - * considering that sdelay takes 2 instruction for every 1 delay cycle. - * And assuming each instruction takes 1 clock cycle i.e 1/(1.7 Ghz)sec - * So for 500 usec, the number of delay cycle should be - * (500 * 10^-6) * (1.7 * 10^9) / 2 = 425000 - * - * TODO(hatim.rv(a)samsung.com): Implement the delay using timer/counter - */ - sdelay(425000); -#endif udelay(500); } diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index b3dd37e..3263125 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -13,34 +13,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -#if 0 -/* - * The coefficient, used to calculate the baudrate on S5P UARTs is - * calculated as - * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT - * however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1, - * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: - */ -static const int udivslot[] = { - 0, - 0x0080, - 0x0808, - 0x0888, - 0x2222, - 0x4924, - 0x4a52, - 0x54aa, - 0x5555, - 0xd555, - 0xd5d5, - 0xddd5, - 0xdddd, - 0xdfdd, - 0xdfdf, - 0xffdf, -}; -#endif - static void serial_setbrg_dev(struct s5p_uart *uart) { u32 uclk; @@ -51,18 +23,6 @@ val = uclk / get_uart_baudrate(); write32(&uart->ubrdiv, val / 16 - 1); - - /* - * FIXME(dhendrix): the original uart.h had a "br_rest" value which - * does not seem relevant to the exynos5250... not entirely sure - * where/if we need to worry about it here - */ -#if 0 - if (s5p_uart_divslot()) - writel(udivslot[val % 16], &uart->rest.slot); - else - writeb(val % 16, &uart->rest.value); -#endif } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/43253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a3a0c7453753c069f1106067fc12547da842d66 Gerrit-Change-Number: 43253 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by build bot (Jenkins) (Code Review) 08 Jul '20

08 Jul '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/42792/16/payloads/libpayload/drive… File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/42792/16/payloads/libpayload/drive… PS16, Line 751: if (equals++ >= (SSZ * SSZ)) Too many leading tabs - consider code refactoring -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 16 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 22:41:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and ad...
by Jonathan Zhang (Code Review) 08 Jul '20

08 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42840 ) Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ...................................................................... vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc CPX-SP FSP ww26 release added UPD to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf --- M src/mainboard/ocp/deltalake/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 27 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42840/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index b6ea3ec..ebe2c80 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -14,6 +14,10 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { + /* Send FSP log message to SOL */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + /* Enable only PCH: PCIE[8:11] */ for (uint8_t i = 0; i < 20; i++) { if (i >= 8 && i <= 11) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index fd84f1a..18f8167 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -594,7 +594,7 @@ **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0100 - PchAdrEn +/** Offset 0x0100 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; @@ -633,7 +633,23 @@ **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0140 +/** Offset 0x0140 - SerialIoUartDebugEnable + Enable SerialIo Uart debug library in FSP. + 0:Disable, 1:Enable +**/ + UINT8 SerialIoUartDebugEnable; + +/** Offset 0x0141 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x0142 - ISA Serial Base selection + Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 + 0x3F8, 0x2F8 +**/ + UINT16 SerialIoUartDebugIoBase; + +/** Offset 0x0144 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -654,9 +670,9 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0150 +/** Offset 0x0154 **/ - UINT8 UnusedUpdSpace3[6]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x0156 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index e9c7dbf..ee86a6d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -85,7 +85,7 @@ /* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { - UINT8 reserved1[61]; + UINT8 reserved1[58]; UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. @@ -99,11 +99,11 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; - UINT8 reserved3[24417]; + UINT8 reserved3[24514]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved4[10]; + UINT8 reserved4[2]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/42840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Gerrit-Change-Number: 42840 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Enable eSPI capability for Picasso
by Furquan Shaikh (Code Review) 08 Jul '20

08 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41075 ) Change subject: soc/amd/picasso: Enable eSPI capability for Picasso ...................................................................... soc/amd/picasso: Enable eSPI capability for Picasso This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/41075/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3d69966..a304819 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ select UDELAY_TSC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS -- To view, visit https://review.coreboot.org/c/coreboot/+/41075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Gerrit-Change-Number: 41075 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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