coreboot-gerrit July 2020

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Hello build bot (Jenkins), Bao Zheng, Raul Rangel, Furquan Shaikh, Patrick Georgi, Julius Werner, Eric Peers, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41816 to look at the new patch set (#12). Change subject: soc/amd/picasso: add psp_verstage ...................................................................... soc/amd/picasso: add psp_verstage This is the main code for building coreboot's verstage as a userspace application to run on the PSP. It does a minimal setup of hardware, then runs verstage_main. It uses hardware hashing to increase the speed and will directly reboot into recovery mode if there are any failures. BUG=b:158124527 TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/memlayout_psp_verstage.ld A src/soc/amd/picasso/memlayout_x86.ld A src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/delay.c A src/soc/amd/picasso/psp_verstage/fch.c A src/soc/amd/picasso/psp_verstage/include/arch/io.h A src/soc/amd/picasso/psp_verstage/pmutil.c A src/soc/amd/picasso/psp_verstage/post.c A src/soc/amd/picasso/psp_verstage/printk.c A src/soc/amd/picasso/psp_verstage/psp.c A src/soc/amd/picasso/psp_verstage/psp_verstage.c A src/soc/amd/picasso/psp_verstage/psp_verstage.h A src/soc/amd/picasso/psp_verstage/reset.c A src/soc/amd/picasso/psp_verstage/svc.c A src/soc/amd/picasso/psp_verstage/svc.h A src/soc/amd/picasso/psp_verstage/timer.c A src/soc/amd/picasso/psp_verstage/timestamp.c A src/soc/amd/picasso/psp_verstage/vboot_crypto.c 22 files changed, 1,125 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41816/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 12 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/mipi_camera: Add guard to protect camera resources
by Sugnan Prabhu S (Code Review) 08 Jul '20

08 Jul '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43003 ) Change subject: drivers/intel/mipi_camera: Add guard to protect camera resources ...................................................................... Patch Set 6: (14 comments) https://review.coreboot.org/c/coreboot/+/43003/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43003/5//COMMIT_MSG@7 PS5, Line 7: drivers/intel/mipi_camera: Add guard variables to protect shared resource : : This change updates the mipi_camera driver to handle shared power resource : between multiple cameras. This is achieved by adding a guard variable and : methods manipulate the guard variable and guard the call to actual method : while enables or disables the resource. This protects the shared lines : from being enabled or disabled multiple times while the resources are : being used by multiple cameras. : > reflow for 72 characters wide Done. https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… File src/drivers/intel/mipi_camera/camera.c: https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 26: .cnt = 0 > it should get initialized to 0 as it's a file-level static variable, so . […] Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 477: printk(BIOS_ERR, "Unsupported power operation: %x\n", type); : printk(BIOS_ERR, "OS camera driver will likely not work"); > nit: this can be combined into one printk call: […] Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 485: if (action == ENABLE) { : snprintf(method_name, sizeof(method_name), ENABLE_METHOD_FORMAT, : res_index); : } else if (action == DISABLE) { : snprintf(method_name, sizeof(method_name), DISABLE_METHOD_FORMAT, : res_index); : } else { : snprintf(method_name, sizeof(method_name), UNKNOWN_METHOD_FORMAT, : res_index); : acpigen_write_debug_string("Unsupported action"); : printk(BIOS_ERR, "Unsupported resource action: %x\n", action); : } > a switch statement may be more clear on intention here. […] Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 502: uint8_t > enum action_type Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 502: uint8_t > enum ctrl_type Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 502: void *res_config > Sugnan, I'm not a big fan of the void* for res_config... […] Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 569: printk(BIOS_ERR, "Unsupported power operation: %x\n", seq->ops[i].type); : printk(BIOS_ERR, "OS camera driver will likely not work\n"); > nit: you can squash this into one printk call Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 571: res_config = NULL; : break; : } : : if (res_config == NULL) : continue; > just return from within the `default:` block, I think it's easier to see the intent. Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 582: printk(BIOS_ERR, "Unable to add guarded camera resource\n"); : printk(BIOS_ERR, "OS camera driver will likely not work\n"); > nit: you can squash this into one printk call Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 596: acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_namestring(varname); : acpigen_write_integer(0); > acpigen_write_if_lequal_namestr_int Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 602: : acpigen_emit_byte(ADD_OP); : acpigen_emit_namestring(varname); : acpigen_emit_byte(0x01); : acpigen_emit_namestring(varname); : acpigen_pop_len(); /* _ON */ > there is an INCREMENT_OP 😊 Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 612: acpigen_emit_byte(SUBTRACT_OP); : acpigen_emit_namestring(varname); : acpigen_emit_byte(0x01); : acpigen_emit_namestring(varname); > DECREMENT_OP Done https://review.coreboot.org/c/coreboot/+/43003/5/src/drivers/intel/mipi_cam… PS5, Line 616: acpigen_write_if(); : acpigen_emit_byte(LEQUAL_OP); : acpigen_emit_namestring(varname); : acpigen_write_integer(0); > acpigen_write_if_lequal_namestr_int Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 6 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 08 Jul 2020 15:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add guard to protect camera resources
by Sugnan Prabhu S (Code Review) 08 Jul '20

08 Jul '20

Hello Varshit B Pandya, build bot (Jenkins), Matt Delco, Furquan Shaikh, Tim Wawrzynczak, Rizwan Qureshi, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43003 to look at the new patch set (#6). Change subject: drivers/intel/mipi_camera: Add guard to protect camera resources ...................................................................... drivers/intel/mipi_camera: Add guard to protect camera resources This change updates the mipi_camera driver to handle shared power resource between multiple cameras. This is achieved by adding a guard variable and methods to manipulate the guard variable before calling the actual method which enables or disables the resource. This protects the shared resources from being enabled or disabled multiple times while the resources are being used by multiple cameras. Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 316 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43003/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 6 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/memla… File src/soc/amd/picasso/memlayout_psp_verstage.ld: https://review.coreboot.org/c/coreboot/+/41816/10/src/soc/amd/picasso/memla… PS10, Line 55: VERSTAGE_START + VERSTAGE_SIZE > Don't you want VBOOT_WORK_START? Or if you don't really care where it's located you can just use `. […] Sorry, I missed this comment until just now. This actually gives the same value as VBOOT_WORK_START. I'll update it in a follow-on patch and merge that with this patch if I need to repush this. 60K = 0xF000 0xF000 + 0x15000 = 0x24000 -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 15:31:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by build bot (Jenkins) (Code Review) 08 Jul '20

08 Jul '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41816 ) Change subject: soc/amd/picasso: add psp_verstage ...................................................................... Patch Set 11: (10 comments) https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… File src/soc/amd/picasso/psp_verstage/svc.h: https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 6: #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 6: #define SVC_CALL4(SVC_ID, R0, R1, R2, R3, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 19: #define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 19: #define SVC_CALL3(SVC_ID, R0, R1, R2, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 30: #define SVC_CALL2(SVC_ID, R0, R1, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 30: #define SVC_CALL2(SVC_ID, R0, R1, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 40: #define SVC_CALL1(SVC_ID, R0, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 40: #define SVC_CALL1(SVC_ID, R0, Ret) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 49: #define SVC_CALL0(SVC_ID, Ret) \ Macros with multiple statements should be enclosed in a do - while loop https://review.coreboot.org/c/coreboot/+/41816/11/src/soc/amd/picasso/psp_v… PS11, Line 49: #define SVC_CALL0(SVC_ID, Ret) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 14:26:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add psp_verstage
by Martin Roth (Code Review) 08 Jul '20

08 Jul '20

Hello Bao Zheng, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Patrick Georgi, Julius Werner, Eric Peers, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41816 to look at the new patch set (#11). Change subject: soc/amd/picasso: add psp_verstage ...................................................................... soc/amd/picasso: add psp_verstage This is the main code for building coreboot's verstage as a userspace application to run on the PSP. It does a minimal setup of hardware, then runs verstage_main. It uses hardware hashing to increase the speed and will directly reboot into recovery mode if there are any failures. BUG=b:158124527 TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/memlayout.ld A src/soc/amd/picasso/memlayout_psp_verstage.ld A src/soc/amd/picasso/memlayout_x86.ld A src/soc/amd/picasso/psp_verstage/Makefile.inc A src/soc/amd/picasso/psp_verstage/delay.c A src/soc/amd/picasso/psp_verstage/fch.c A src/soc/amd/picasso/psp_verstage/include/arch/io.h A src/soc/amd/picasso/psp_verstage/pmutil.c A src/soc/amd/picasso/psp_verstage/post.c A src/soc/amd/picasso/psp_verstage/printk.c A src/soc/amd/picasso/psp_verstage/psp.c A src/soc/amd/picasso/psp_verstage/psp_verstage.c A src/soc/amd/picasso/psp_verstage/psp_verstage.h A src/soc/amd/picasso/psp_verstage/reset.c A src/soc/amd/picasso/psp_verstage/svc.c A src/soc/amd/picasso/psp_verstage/svc.h A src/soc/amd/picasso/psp_verstage/timer.c A src/soc/amd/picasso/psp_verstage/timestamp.c A src/soc/amd/picasso/psp_verstage/vboot_crypto.c 22 files changed, 1,125 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/41816/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/41816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Gerrit-Change-Number: 41816 Gerrit-PatchSet: 11 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ACPI: Bump STRAT revision to 3
by KOUAM Ledoux (Code Review) 08 Jul '20

08 Jul '20

KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43296 ) Change subject: ACPI: Bump STRAT revision to 3 ...................................................................... ACPI: Bump STRAT revision to 3 This adds SRAT processor local x2APIC, GICC, GIC, ITS and Generic Initiator affinity structures.Current revision is 1.Regarding ACPI v6.3 specs, SRAT revision is 3. Change-Id: I5a32ffe6f0c5e2491eac29d4ec09a6aa55ff3627 Signed-off-by: kouamdo <kouamdoux(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/43296/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 96919c7..6dae0d8 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -544,10 +544,10 @@ return gicc->length; } -int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu) +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struct_t *gen, u8 node, u8 cpu) { gen->type = 5; - gen->length = sizeof(acpi_srat_gen_init_struc_t); + gen->length = sizeof(acpi_srat_gen_init_struct_t); gen->resv1 = 0; /* TODO: Device Handle type: gen->device_hdle_type*/ diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 3dfb238..aa6bfa1 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -199,7 +199,7 @@ } __packed acpi_mcfg_mmconfig_t; /* SRAT (System Resource Affinity Table) */ -typedef struct { +typedef struct acpi_srat { acpi_header_t header; u32 resv; u64 resv1; @@ -267,7 +267,7 @@ } __packed acpi_srat_its_t; /*SRAT: Generic Initiator Affinity Structure*/ -typedef struct acpi_srat_gen_init_struc { +typedef struct acpi_srat_gen_init_struct { u8 type; /* Type (5) */ u8 length; /* Length in bytes (32) */ u16 resv1; /* Reserved */ @@ -276,7 +276,7 @@ u32 device_hdle[4]; /* Device Handle of the Generic Initiator */ u32 flags; /* */ u32 resv2; -} __packed acpi_srat_gen_init_struc_t; +} __packed acpi_srat_gen_init_struct_t; /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { @@ -952,7 +952,7 @@ int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic); int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu); int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu); -int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu); +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struct_t *gen, u8 node, u8 cpu); int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); -- To view, visit https://review.coreboot.org/c/coreboot/+/43296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a32ffe6f0c5e2491eac29d4ec09a6aa55ff3627 Gerrit-Change-Number: 43296 Gerrit-PatchSet: 1 Gerrit-Owner: KOUAM Ledoux <kouamdoux(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Bump SRAT revision to 3
by KOUAM Ledoux (Code Review) 08 Jul '20

08 Jul '20

KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43293 ) Change subject: Bump SRAT revision to 3 ...................................................................... Bump SRAT revision to 3 This adds SRAT processor local x2APIC, GICC, GIC, ITS and Generic Initiator affinity structures. Current revision is 1.Regarding ACPI v6.3 specs, SRAT revision is 3. Change-Id: Ibf845d38b979bd70c4715c5a374845ebb4b52937 Signed-off-by: kouamdo <kouamdoux(a)gmail.com> --- M src/include/acpi/acpi.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43293/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 42d3cef..3dfb238 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -953,7 +953,6 @@ int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu); int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu); int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu); - int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); -- To view, visit https://review.coreboot.org/c/coreboot/+/43293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf845d38b979bd70c4715c5a374845ebb4b52937 Gerrit-Change-Number: 43293 Gerrit-PatchSet: 1 Gerrit-Owner: KOUAM Ledoux <kouamdoux(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: SRAT revision to 3
by KOUAM Ledoux (Code Review) 08 Jul '20

08 Jul '20

KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43292 ) Change subject: SRAT revision to 3 ...................................................................... SRAT revision to 3 Bump SRAT revision to 3. This adds SRAT processor local x2APIC,GICC,GIC ITS and Generic Initiator affinity structures. Current revision is 1. Regarding ACPI v6.3 specs, SRAT revision is 3. Change-Id: I40928c63626b4edde4952452827b20e0dd843735 Signed-off-by: kouamdo <kouamdoux(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43292/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 354af8e..96919c7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -559,6 +559,7 @@ return gen->length; } + /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e6c0a8a..42d3cef 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -949,6 +949,11 @@ int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags); +int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic); +int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu); +int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu); +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu); + int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); -- To view, visit https://review.coreboot.org/c/coreboot/+/43292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40928c63626b4edde4952452827b20e0dd843735 Gerrit-Change-Number: 43292 Gerrit-PatchSet: 1 Gerrit-Owner: KOUAM Ledoux <kouamdoux(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: SRAT revision to 3
by KOUAM Ledoux (Code Review) 08 Jul '20

08 Jul '20

KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43286 ) Change subject: SRAT revision to 3 ...................................................................... SRAT revision to 3 Bump SRAT revision to 3. This adds have take all the type of ACPI STRAT table (1 - 5 ) Change-Id: Ia4bd5f97be1abf1b2de005d7c26c86665ecb8c5e Signed-off-by: kouamdo <kouamdoux(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 96 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/43286/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 47f03c8..354af8e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -507,6 +507,58 @@ return mem->length; } +int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic) +{ + lx2apic->type = 2; + lx2apic->length = sizeof(acpi_srat_lx2apic_t); + lx2apic->proximity_domain = node; + lx2apic->lx2apic_id = x2apic; + lx2apic->flags = (1 << 0); + /* TODO: clock domain: lx2apic->clock_domain */ + lx2apic->resv1 = 0; + lx2apic->resv2 = 0; + + return lx2apic->length; +} + +int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu) +{ + gicc->type = 3; + gicc->length = sizeof(acpi_srat_gicc_t); + gicc->proximity_domain = node; + gicc->processor_id = cpu; + gicc->flags = (1 << 0); + /* TODO: clock domain: gicc->clock_domain */ + + return gicc->length; +} + +int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu) +{ + gicc->type = 4; + gicc->length = sizeof(acpi_srat_its_t); + gicc->proximity_domain = node; + gicc->resv = 0; + gicc->its_id = cpu; + + return gicc->length; +} + +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu) +{ + gen->type = 5; + gen->length = sizeof(acpi_srat_gen_init_struc_t); + gen->resv1 = 0; + /* TODO: Device Handle type: gen->device_hdle_type*/ + + gen->proximity_domain = node; + /* TODO: Device handle for the generic Initiator*/ + + gen->flags = (1 << 0); + gen->resv2 = 0; + + return gen->length; +} /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index cd99899..e6c0a8a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -199,7 +199,7 @@ } __packed acpi_mcfg_mmconfig_t; /* SRAT (System Resource Affinity Table) */ -typedef struct acpi_srat { +typedef struct { acpi_header_t header; u32 resv; u64 resv1; @@ -235,6 +235,49 @@ u32 resv2[2]; } __packed acpi_srat_mem_t; +/* SRAT: x2APIC Affinity Structure */ +typedef struct acpi_srat_lx2apic { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (24) */ + u16 resv1; /* Reserved */ + u32 proximity_domain; /* Proximity Domain */ + u32 lx2apic_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ + u32 resv2; +} __packed acpi_srat_lx2apic_t; + +/* SRAT: GICC Affinity Structure*/ +typedef struct acpi_srat_gicc { + u8 type; /* Type (3) */ + u8 length; /* Length in bytes (18) */ + u32 proximity_domain; /* Proximity Domain */ + u32 processor_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ +} __packed acpi_srat_gicc_t; + +/* SRAT: Architecture Specific Affinity Structure */ +typedef struct acpi_srat_its { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (12) */ + u32 proximity_domain; /* Proximity Domain */ + u16 resv; + u32 its_id; /* ITS ID matching a GIC ITS entry in the MADT */ +} __packed acpi_srat_its_t; + +/*SRAT: Generic Initiator Affinity Structure*/ +typedef struct acpi_srat_gen_init_struc { + u8 type; /* Type (5) */ + u8 length; /* Length in bytes (32) */ + u16 resv1; /* Reserved */ + u8 device_hdle_type; /* Device Handle Type */ + u32 proximity_domain; /* Proximity Domain */ + u32 device_hdle[4]; /* Device Handle of the Generic Initiator */ + u32 flags; /* */ + u32 resv2; +} __packed acpi_srat_gen_init_struc_t; + /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { acpi_header_t header; -- To view, visit https://review.coreboot.org/c/coreboot/+/43286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd5f97be1abf1b2de005d7c26c86665ecb8c5e Gerrit-Change-Number: 43286 Gerrit-PatchSet: 1 Gerrit-Owner: KOUAM Ledoux <kouamdoux(a)gmail.com> Gerrit-MessageType: newchange

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