coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3167 discussions

Change in coreboot[master]: SRAT revision to 3
by KOUAM Ledoux (Code Review) 08 Jul '20

08 Jul '20

KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43286 ) Change subject: SRAT revision to 3 ...................................................................... SRAT revision to 3 Bump SRAT revision to 3. This adds have take all the type of ACPI STRAT table (1 - 5 ) Change-Id: Ia4bd5f97be1abf1b2de005d7c26c86665ecb8c5e Signed-off-by: kouamdo <kouamdoux(a)gmail.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 96 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/43286/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 47f03c8..354af8e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -507,6 +507,58 @@ return mem->length; } +int acpi_create_srat_lx2apic(acpi_srat_lx2apic_t *lx2apic, u8 node, u8 x2apic) +{ + lx2apic->type = 2; + lx2apic->length = sizeof(acpi_srat_lx2apic_t); + lx2apic->proximity_domain = node; + lx2apic->lx2apic_id = x2apic; + lx2apic->flags = (1 << 0); + /* TODO: clock domain: lx2apic->clock_domain */ + lx2apic->resv1 = 0; + lx2apic->resv2 = 0; + + return lx2apic->length; +} + +int acpi_create_srat_gicc(acpi_srat_gicc_t *gicc, u8 node, u8 cpu) +{ + gicc->type = 3; + gicc->length = sizeof(acpi_srat_gicc_t); + gicc->proximity_domain = node; + gicc->processor_id = cpu; + gicc->flags = (1 << 0); + /* TODO: clock domain: gicc->clock_domain */ + + return gicc->length; +} + +int acpi_create_srat_its(acpi_srat_its_t *gicc, u8 node, u8 cpu) +{ + gicc->type = 4; + gicc->length = sizeof(acpi_srat_its_t); + gicc->proximity_domain = node; + gicc->resv = 0; + gicc->its_id = cpu; + + return gicc->length; +} + +int acpi_create_srat_gen_init_struct_(acpi_srat_gen_init_struc_t *gen, u8 node, u8 cpu) +{ + gen->type = 5; + gen->length = sizeof(acpi_srat_gen_init_struc_t); + gen->resv1 = 0; + /* TODO: Device Handle type: gen->device_hdle_type*/ + + gen->proximity_domain = node; + /* TODO: Device handle for the generic Initiator*/ + + gen->flags = (1 << 0); + gen->resv2 = 0; + + return gen->length; +} /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index cd99899..e6c0a8a 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -199,7 +199,7 @@ } __packed acpi_mcfg_mmconfig_t; /* SRAT (System Resource Affinity Table) */ -typedef struct acpi_srat { +typedef struct { acpi_header_t header; u32 resv; u64 resv1; @@ -235,6 +235,49 @@ u32 resv2[2]; } __packed acpi_srat_mem_t; +/* SRAT: x2APIC Affinity Structure */ +typedef struct acpi_srat_lx2apic { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (24) */ + u16 resv1; /* Reserved */ + u32 proximity_domain; /* Proximity Domain */ + u32 lx2apic_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ + u32 resv2; +} __packed acpi_srat_lx2apic_t; + +/* SRAT: GICC Affinity Structure*/ +typedef struct acpi_srat_gicc { + u8 type; /* Type (3) */ + u8 length; /* Length in bytes (18) */ + u32 proximity_domain; /* Proximity Domain */ + u32 processor_id; /* Local APIC Id */ + u32 flags; /* */ + u32 clock_domain; /**/ +} __packed acpi_srat_gicc_t; + +/* SRAT: Architecture Specific Affinity Structure */ +typedef struct acpi_srat_its { + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (12) */ + u32 proximity_domain; /* Proximity Domain */ + u16 resv; + u32 its_id; /* ITS ID matching a GIC ITS entry in the MADT */ +} __packed acpi_srat_its_t; + +/*SRAT: Generic Initiator Affinity Structure*/ +typedef struct acpi_srat_gen_init_struc { + u8 type; /* Type (5) */ + u8 length; /* Length in bytes (32) */ + u16 resv1; /* Reserved */ + u8 device_hdle_type; /* Device Handle Type */ + u32 proximity_domain; /* Proximity Domain */ + u32 device_hdle[4]; /* Device Handle of the Generic Initiator */ + u32 flags; /* */ + u32 resv2; +} __packed acpi_srat_gen_init_struc_t; + /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { acpi_header_t header; -- To view, visit https://review.coreboot.org/c/coreboot/+/43286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd5f97be1abf1b2de005d7c26c86665ecb8c5e Gerrit-Change-Number: 43286 Gerrit-PatchSet: 1 Gerrit-Owner: KOUAM Ledoux <kouamdoux(a)gmail.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failu...
by Paul Menzel (Code Review) 08 Jul '20

08 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43005 ) Change subject: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failure is detected ...................................................................... Patch Set 7: (8 comments) https://review.coreboot.org/c/coreboot/+/43005/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43005/7//COMMIT_MSG@7 PS7, Line 7: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failure is detected Maybe below summary is shorter: > mb/ocp/deltalake: Send OEM IPMI command for CMOS clear on RTC failure https://review.coreboot.org/c/coreboot/+/43005/7//COMMIT_MSG@9 PS7, Line 9: When RTC failure is detected, : send IPMI OEM command to issue CMOS clear. : This is to let the payload (LinuxBoot) do some handling. Please re-flow for 75 characters per line. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ipmi.h: https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 16: #define VALID_BIT (1 << 7) Please align the values with spaces to the column of the block above. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 19: #define IS_CMOS_AND_VALID_BIT(x) ((x)&CMOS_BIT && (x)&VALID_BIT) I’d left align the names. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ipmi.c: https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 122: the CMOS clear bit are both set from the response BootMode byte. */ Please align to the word *IPMI* above. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 136: Pleas remove the blank line. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 150: printk(BIOS_INFO, "IPMI CMOS clear requested\n"); Maybe elaborate: … because CMOS data is invalid. https://review.coreboot.org/c/coreboot/+/43005/7/src/mainboard/ocp/deltalak… PS7, Line 151: return CB_SUCCESS; Please add a blank line above. -- To view, visit https://review.coreboot.org/c/coreboot/+/43005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Gerrit-Change-Number: 43005 Gerrit-PatchSet: 7 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 10:52:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/xeon_sp: Add RTC failure checking
by Paul Menzel (Code Review) 08 Jul '20

08 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43004 ) Change subject: soc/intel/xeon_sp: Add RTC failure checking ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/43004/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43004/3//COMMIT_MSG@9 PS3, Line 9: Add a weak function mainboard_rtc_failed() : for mainboard customization. : : Check RTC_PWR_STS bit for RTC battery removal : or CMOS clear jumper triggered event. Please re-flow for 75 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/43004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Gerrit-Change-Number: 43004 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rocky Phagura Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 10:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/jslvp: Skip Cpu Replacement Check for jslrvp
by Paul Menzel (Code Review) 08 Jul '20

08 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43146 ) Change subject: mb/intel/jslvp: Skip Cpu Replacement Check for jslrvp ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/43146/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43146/1//COMMIT_MSG@7 PS1, Line 7: Cpu CPU https://review.coreboot.org/c/coreboot/+/43146/1//COMMIT_MSG@10 PS1, Line 10: MRC training on jslrvp. That sounds like a bad design. Why is the replacement check force a retrain? -- To view, visit https://review.coreboot.org/c/coreboot/+/43146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Gerrit-Change-Number: 43146 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 Jul 2020 10:45:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/lippert/frontrunner-af: Make it a variant of itself
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43273 ) Change subject: mb/lippert/frontrunner-af: Make it a variant of itself ...................................................................... mb/lippert/frontrunner-af: Make it a variant of itself Change-Id: I5f0f1b0f0b22b1bd53f15f43c91fbffe944112ac Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/lippert/frontrunner-af/Kconfig M src/mainboard/lippert/frontrunner-af/Makefile.inc R src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43273/1 diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 80b5172..5504851 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -22,6 +22,10 @@ string default "lippert/frontrunner-af" +config VARIANT_DIR + string + default "frontrunner-af" if BOARD_LIPPERT_FRONTRUNNER_AF + config MAINBOARD_PART_NUMBER string default "FrontRunner-AF" diff --git a/src/mainboard/lippert/frontrunner-af/Makefile.inc b/src/mainboard/lippert/frontrunner-af/Makefile.inc index 9b9e5ae..1ae7939 100644 --- a/src/mainboard/lippert/frontrunner-af/Makefile.inc +++ b/src/mainboard/lippert/frontrunner-af/Makefile.inc @@ -17,6 +17,8 @@ ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c +ramstage-y += variants/$(VARIANT_DIR)/mainboard.c + # Minimal SEMA watchdog support romstage-y += sema.c ramstage-y += sema.c diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c similarity index 100% rename from src/mainboard/lippert/frontrunner-af/mainboard.c rename to src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0f1b0f0b22b1bd53f15f43c91fbffe944112ac Gerrit-Change-Number: 43273 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/xeon_sp: Add RTC failure checking
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43004 ) Change subject: soc/intel/xeon_sp: Add RTC failure checking ...................................................................... Patch Set 3: Code-Review+1 (4 comments) https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/incl… File src/soc/intel/xeon_sp/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/incl… PS3, Line 28: nit: two spaces here (it's a bit inside a register) https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/pmut… File src/soc/intel/xeon_sp/pmutil.c: https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/pmut… PS3, Line 14: int bool https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/pmut… PS3, Line 16: RTC_BATTERY_DEAD Instead of masking here, I'd read the register as-is inside a variable and mask the desired bit elsewhere. This should make the lines fit within 96 characters. https://review.coreboot.org/c/coreboot/+/43004/3/src/soc/intel/xeon_sp/pmut… PS3, Line 16: PCH_DEVFN_PMC<<12 huh? Why this shift? -- To view, visit https://review.coreboot.org/c/coreboot/+/43004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Gerrit-Change-Number: 43004 Gerrit-PatchSet: 3 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Comment-Date: Wed, 08 Jul 2020 10:02:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: build system: Rely on xcompile for HOSTCC and HOSTCXX
by Patrick Georgi (Code Review) 08 Jul '20

08 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43145 ) Change subject: build system: Rely on xcompile for HOSTCC and HOSTCXX ...................................................................... build system: Rely on xcompile for HOSTCC and HOSTCXX It already looks for them, so let's use the result instead of blindly defaulting to gcc/g++. Change-Id: I3e50c70a609f1903a925610928f8779c191040d8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/43145/1 diff --git a/Makefile b/Makefile index 6a96f9d..ba1e280 100644 --- a/Makefile +++ b/Makefile @@ -61,8 +61,6 @@ # Disable implicit/built-in rules to make Makefile errors fail fast. .SUFFIXES: -HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc) -HOSTCXX = g++ HOSTCFLAGS := -g HOSTCXXFLAGS := -g -- To view, visit https://review.coreboot.org/c/coreboot/+/43145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e50c70a609f1903a925610928f8779c191040d8 Gerrit-Change-Number: 43145 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: util/xcompile: Look for the host compiler in XGCCPATH, too (and first)
by Patrick Georgi (Code Review) 08 Jul '20

08 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43144 ) Change subject: util/xcompile: Look for the host compiler in XGCCPATH, too (and first) ...................................................................... util/xcompile: Look for the host compiler in XGCCPATH, too (and first) If there's a host compiler in XGCCPATH, it's likely the same relatively-current version we use for coreboot, and it's a well-known quantity, so let's prefer that over alternatives by default. Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/xcompile/xcompile 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/43144/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 6629546..388f878 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -56,7 +56,9 @@ IASL=iasl fi -if program_exists gcc; then +if program_exists "${XGCCPATH}/gcc"; then + HOSTCC="${XGCCPATH}/gcc" +elif program_exists gcc; then HOSTCC=gcc elif program_exists cc; then HOSTCC=cc -- To view, visit https://review.coreboot.org/c/coreboot/+/43144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If50341df169a476899b5a5ffd4c4fb6d21c3f4ac Gerrit-Change-Number: 43144 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
by Patrick Georgi (Code Review) 08 Jul '20

08 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42426 ) Change subject: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine ...................................................................... sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine The smm_setup_structures() calls placed GNVS address into register %ebx. Old code on i82801dx used these low memory addresses. Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42426 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c 3 files changed, 9 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 7aee63b..562dae3 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,11 +21,9 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(struct global_nvs **)0x500; - *smm_done = 1; -} +/* This implementation was removed since it was invalid. There will be one shared + approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index c352e5d..699f51f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -14,8 +14,9 @@ struct global_nvs *gnvs; #endif -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +/* This implementation was removed since it was invalid. There will be one shared + approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { @@ -34,14 +35,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(struct global_nvs **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index b6161e9..16ec025 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -15,8 +15,9 @@ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -void *tcg = (void *)0x0; -void *smi1 = (void *)0x0; +/* This implementation was removed since it was invalid. There will be one shared + approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */ +void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { } int southbridge_io_trap_handler(int smif) { @@ -35,14 +36,6 @@ return 0; } -void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) -{ - gnvs = *(struct global_nvs **)0x500; - tcg = *(void **)0x504; - smi1 = *(void **)0x508; - *smm_done = 1; -} - void southbridge_smi_monitor(void) { #define IOTRAP(x) (trap_sts & (1 << x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/42426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Gerrit-Change-Number: 42426 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: ACPI: Add and fill gnvs_ptr for smm_runtime
by Kyösti Mälkki (Code Review) 08 Jul '20

08 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42464 ) Change subject: ACPI: Add and fill gnvs_ptr for smm_runtime ...................................................................... ACPI: Add and fill gnvs_ptr for smm_runtime Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/42464/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6e9781a..c195979 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> +#include <acpi/acpi_gnvs.h> #include <rmodule.h> #include <cpu/x86/smm.h> #include <commonlib/helpers.h> @@ -261,6 +262,7 @@ stub_params->runtime.smm_size = smm_size; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; stub_params->runtime.num_cpus = params->num_concurrent_stacks; + stub_params->runtime.gnvs_ptr = acpi_get_gnvs(); /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 8086b75..425724d 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -36,6 +36,8 @@ .long 0 num_cpus: .long 0 +gnvs_ptr: +.long 0 /* allows the STM to bring up SMM in 32-bit mode */ start32_offset: .long smm_trampoline32 - _start diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 9c4d227..72b9dd5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -59,6 +59,7 @@ u32 smm_size; u32 save_state_size; u32 num_cpus; + u32 gnvs_ptr; /* STM's 32bit entry into SMI handler */ u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. -- To view, visit https://review.coreboot.org/c/coreboot/+/42464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I823d04a4851437b4267a60886e5ab205bb2e1b10 Gerrit-Change-Number: 42464 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020