coreboot-gerrit July 2020

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Change in coreboot[master]: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
by Bryant Ou (Code Review) 08 Jul '20

08 Jul '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42856 ) Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ...................................................................... mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC BIC use LPCflash utility to flash FW, it use LPC to send the bridge IC image form host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42856/1 diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 031d11a..5682ca7 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -37,6 +37,7 @@ register "coherency_support" = "0" register "ats_support" = "0" + register "gen1_dec" = "0x00FC0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/42856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Gerrit-Change-Number: 42856 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: add elan touchscreen
by Chen Wisley (Code Review) 08 Jul '20

08 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42923 ) Change subject: mb/google/dedede/var/drawcia: add elan touchscreen ...................................................................... mb/google/dedede/var/drawcia: add elan touchscreen BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42923/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index a92dbdb..3b67510 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -47,5 +47,19 @@ device i2c 15 on end end end #I2C 0 + device pci 15.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D4_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # I2C 2 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Gerrit-Change-Number: 42923 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Add support for long mode
by Patrick Rudolph (Code Review) 08 Jul '20

08 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35681 ) Change subject: cpu/x86/smm: Add support for long mode ...................................................................... cpu/x86/smm: Add support for long mode Enable long mode in SMM handler. x86_32 isn't affected from this change. As the rsm instruction used to leave SMM doesn't restore MSR registers, drop back to protected mode after running the smi_handler and restore IA32_EFER MSR to previous value. Tested on Qemu Q35. Needs tests on real hardware. Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/cpu/x86/smm/smmhandler.S 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35681/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 462e7e6..b02b879 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -45,6 +45,7 @@ * Add x86_64 exception handlers - *TODO* * Setup page tables for long mode - *DONE* * Add assembly code for long mode - *DONE* +* Add assembly code for SMM - *DONE* * Add assembly code for postcar stage - *TODO* * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2..fd8af79 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -20,6 +20,7 @@ */ #include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> /* * +--------------------------------+ 0xaffff @@ -171,15 +172,104 @@ /* Get SMM revision */ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ + +#if defined(__x86_64__) + /* Backup IA32_EFER. Preserves ebx. */ + movl $(IA32_EFER), %ecx + rdmsr + movl %eax, ia32efer_backup + + /* Enable long mode if required. Preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + + mov (%ebx), %rdi + +#else movl (%ebx), %eax pushl %eax +#endif - /* Call 32bit C handler */ + /* Call C handler */ call smi_handler +#if defined(__x86_64__) + /* + * The only reason to go back to protected mode is that rsm doesn't restore + * MSR registers and IA32_EFER was modified. + * To restore IA32_EFER go back to protected mode. + */ + + /* Ensure cache is clean. */ + invd + + /* Set 32-bit code segment and ss */ + mov $0x08, %rcx + call SetCodeSelector32 + +.code32 + /* Running in 32-bit compatibility mode */ + + /* Use flat data segment */ + movl $0x10, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* Disable paging */ + movl %cr0, %eax + andl $0x7FFFFFFF, %eax + movl %eax, %cr0 + + /* Disable long mode */ + movl $(IA32_EFER), %ecx + rdmsr + andl $(~EFER_LME), %eax + wrmsr + + /* Disable PAE */ + movl %cr4, %eax + andl $(~0x20), %eax + movl %eax, %cr4 + + /* Restore IA32_EFER */ + movl $(IA32_EFER), %ecx + rdmsr + movl ia32efer_backup, %eax + wrmsr +#endif + /* To return, just do rsm. It will "clean up" protected mode */ rsm +#if defined(__x86_64__) +ia32efer_backup: +.long + +.align 8 +.code64 +SetCodeSelector32: + # pop the return address from stack + pop %rbx + + # save rsp because we need to push it after ss + mov %rsp, %rdx + + # use iret to jump to a 32-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rdx # the rsp to load + pushfq # push rflags + push %rcx # cx is code segment selector from caller + push %rbx # push the IP for the next instruction + + # the iretq will behave like ret, with the new cs/ss value loaded + iretq +#endif + .code16 .align 4, 0xff @@ -202,6 +292,9 @@ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_gdt_end: -- To view, visit https://review.coreboot.org/c/coreboot/+/35681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Gerrit-Change-Number: 35681 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add TODOs for secure SMM when using x86_64
by Patrick Rudolph (Code Review) 08 Jul '20

08 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42982 ) Change subject: Documentation: Add TODOs for secure SMM when using x86_64 ...................................................................... Documentation: Add TODOs for secure SMM when using x86_64 Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42982/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 462e7e6..5e75b5b 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -49,6 +49,15 @@ * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* +## Future work + +1. Fine grained page tables for SMM: + * Must not have execute and write permissions for the same page. + * Must allow only that TSEG pages can be marked executable + * Must reside in SMRAM +2. Support 64bit PCI BARs above 4GiB +3. Place and run code above 4GiB + ## Porting other boards * Fix compilation errors * Test how well CAR works with x86_64 and paging -- To view, visit https://review.coreboot.org/c/coreboot/+/42982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38 Gerrit-Change-Number: 42982 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/acpi: Update to ASL 2.0 syntax
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43152 ) Change subject: nb/intel/haswell/acpi: Update to ASL 2.0 syntax ...................................................................... nb/intel/haswell/acpi: Update to ASL 2.0 syntax Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43152/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 0f2ed16..b8a1af8 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -140,7 +140,7 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Local0 = One /* Start at P1 */ + Local0 = 1 /* Start at P1 */ Local1 = SizeOf (\_SB.CP00._PSS) While (Local0 < Local1) { @@ -252,7 +252,7 @@ Return (0) } - Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit" /* Set _PPC to LFM */ Local0 = PSSS (LFM_) @@ -280,7 +280,7 @@ Return (0) } - Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit" /* Clear PL1 CLAMP bit */ PL1C = 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/43152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd Gerrit-Change-Number: 43152 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/acpi: Fix host bridge registers
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43151 ) Change subject: nb/intel/haswell/acpi: Fix host bridge registers ...................................................................... nb/intel/haswell/acpi: Fix host bridge registers The host bridge register definitions haven't changed from Sandy Bridge to Haswell, according to the datasheets. However, coreboot's ACPI code is not the same. Looks like Haswell values are wrong, so correct them. Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/43151/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index dd4b79a..0f2ed16 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -16,24 +15,24 @@ Offset (0x40), // EPBAR EPEN, 1, // Enable , 11, // - EPBR, 24, // EPBAR + EPBR, 27, // EPBAR Offset (0x48), // MCHBAR MHEN, 1, // Enable - , 13, // - MHBR, 22, // MCHBAR + , 14, // + MHBR, 24, // MCHBAR Offset (0x54), DVEN, 32, Offset (0x60), // PCIe BAR PXEN, 1, // Enable PXSZ, 2, // BAR size , 23, // - PXBR, 10, // PCIe BAR + PXBR, 13, // PCIe BAR Offset (0x68), // DMIBAR DMEN, 1, // Enable , 11, // - DMBR, 24, // DMIBAR + DMBR, 27, // DMIBAR Offset (0x70), // ME Base Address MEBA, 64, -- To view, visit https://review.coreboot.org/c/coreboot/+/43151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib099575b5cc5e7d468db51f382a15b8aac3eedea Gerrit-Change-Number: 43151 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: arm64: silence libpayload main entry
by Michael Walle (Code Review) 08 Jul '20

08 Jul '20

Michael Walle has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43126 ) Change subject: libpayload: arm64: silence libpayload main entry ...................................................................... libpayload: arm64: silence libpayload main entry No other architecture in libpayload outputs anything in the main entry routing. Let alone an exception test which looks like a real exception to the normal user and is most likely really misleading. Silence the startup code. Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866 Signed-off-by: Michael Walle <michael(a)walle.cc> --- M payloads/libpayload/arch/arm64/exception.c M payloads/libpayload/arch/arm64/main.c 2 files changed, 1 insertion(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43126/1 diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c index 94e7990..21ed1c2 100644 --- a/payloads/libpayload/arch/arm64/exception.c +++ b/payloads/libpayload/arch/arm64/exception.c @@ -32,7 +32,6 @@ u64 exception_stack[2*KiB] __attribute__((aligned(16))); u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack); -extern unsigned int test_exc; struct exception_handler_info { @@ -111,13 +110,7 @@ /* Few words below SP in case we need state from a returned function. */ dump_stack(state->sp - 32, 512); - if (test_exc) { - state->elr += 4; - test_exc = 0; - printf("returning back now\n"); - } - else - halt(); + halt(); } void exception_init(void) diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c index 1311a86..374c8b1 100644 --- a/payloads/libpayload/arch/arm64/main.c +++ b/payloads/libpayload/arch/arm64/main.c @@ -35,19 +35,6 @@ /** The argv value to pass to main() */ char *main_argv[MAX_ARGC_COUNT]; -unsigned int test_exc; - -static int test_exception(void) -{ - uint64_t *a = (uint64_t *)0xfffffffff0000000ULL; - - test_exc = 1; - - printf("%llx\n", *a); - - return 0; -} - /* * Func: pre_sysinfo_scan_mmu_setup * Desc: We need to setup and enable MMU before we can go to scan coreboot @@ -126,10 +113,8 @@ console_init(); #endif - printf("ARM64: Libpayload %s\n",__func__); exception_init(); - test_exception(); /* * Any other system init that has to happen before the * user gets control goes here. -- To view, visit https://review.coreboot.org/c/coreboot/+/43126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e49f24ad46ce578a4bb111c2d623ca4470a1866 Gerrit-Change-Number: 43126 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Walle <michael(a)walle.cc> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: arm64: fix OUTPUT_ARCH()
by Michael Walle (Code Review) 08 Jul '20

08 Jul '20

Michael Walle has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43125 ) Change subject: libpayload: arm64: fix OUTPUT_ARCH() ...................................................................... libpayload: arm64: fix OUTPUT_ARCH() There is no bfd "arm64". The correct bfdname is "aarch64". Fix it. With this change libpayload will build with the AArch64 GCC. Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1 Signed-off-by: Michael Walle <michael(a)walle.cc> --- M payloads/libpayload/arch/arm64/libpayload.ldscript 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43125/1 diff --git a/payloads/libpayload/arch/arm64/libpayload.ldscript b/payloads/libpayload/arch/arm64/libpayload.ldscript index 8ebafce..f9fb771 100644 --- a/payloads/libpayload/arch/arm64/libpayload.ldscript +++ b/payloads/libpayload/arch/arm64/libpayload.ldscript @@ -28,7 +28,7 @@ */ OUTPUT_FORMAT("elf64-littleaarch64","elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(arm64) +OUTPUT_ARCH(aarch64) ENTRY(_entry) -- To view, visit https://review.coreboot.org/c/coreboot/+/43125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7a6b14691107c5d4fc67c3cd3990ecc849d4af1 Gerrit-Change-Number: 43125 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Walle <michael(a)walle.cc> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variable...
by Johnny Lin (Code Review) 08 Jul '20

08 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42495 ) Change subject: mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage ...................................................................... mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/romstage.c 3 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42495/1 diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index dd81bfd..23328f8 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -3,9 +3,19 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <drivers/vpd/vpd.h> +#include <string.h> #include "ipmi.h" +/* VPD variable for enabling/disabling FRB2 timer. */ +#define FRB2_TIMER "FRB2_TIMER" +/* VPD variable for setting FRB2 timer countdown value. */ +#define FRB2_COUNTDOWN "FRB2_COUNTDOWN" +#define VPD_LEN 10 +/* Default countdown is 15 minutes. */ +#define DEFAULT_COUNTDOWN 9000 + enum cb_err ipmi_set_ppin(struct ppin_req *req) { int ret; @@ -70,3 +80,33 @@ return CB_SUCCESS; } + +void init_frb2_wdt(void) +{ + + char val[VPD_LEN]; + /* Enable FRB2 timer by default. */ + u8 enable = 1; + uint16_t countdown; + + if (vpd_get_bool(FRB2_TIMER, VPD_RW, &enable)) { + if (!enable) { + printk(BIOS_DEBUG, "Disable FRB2 timer\n"); + ipmi_stop_bmc_wdt(BMC_KCS_BASE); + return; + } + } + if (enable) { + if (vpd_gets(FRB2_COUNTDOWN, val, VPD_LEN, VPD_RW)) { + countdown = (uint16_t)atol(val); + printk(BIOS_DEBUG, "FRB2 timer countdown set to: %d ms\n", + countdown * 100); + } else { + printk(BIOS_DEBUG, "FRB2 timer use default value: %d ms\n", + DEFAULT_COUNTDOWN * 100); + countdown = DEFAULT_COUNTDOWN; + } + ipmi_init_and_start_bmc_wdt(BMC_KCS_BASE, countdown, + TIMEOUT_HARD_RESET); + } +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index b167473..52f5db9 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -26,4 +26,5 @@ enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); enum cb_err ipmi_get_slot_id(uint8_t *slot_id); +void init_frb2_wdt(void); #endif diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 2199494..0f0ee24 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> @@ -104,6 +105,11 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* Since it's the first IPMI command, it's better to run get BMC + selftest result first */ + if (ipmi_kcs_premem_init(BMC_KCS_BASE, 0) == CB_SUCCESS) + init_frb2_wdt(); + mainboard_config_gpios(mupd); mainboard_config_iio(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Gerrit-Change-Number: 42495 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different ...
by Patrick Georgi (Code Review) 08 Jul '20

08 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41527 ) Change subject: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs ...................................................................... mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c 3 files changed, 41 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 45fbcbf..b4e88b5 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -9,6 +9,7 @@ select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select IPMI_KCS + select IPMI_KCS_ROMSTAGE select OCP_DMI select VPD select VPD_SMBIOS_VERSION diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 14162bb..4fb50b2 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -3,6 +3,7 @@ bootblock-y += bootblock.c romstage-y += romstage.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index fb9a549..68ff113 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -1,9 +1,47 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> +#include "ipmi.h" + +/* Update bifurcation settings according to different Configs */ +static void oem_update_iio(FSPM_UPD *mupd) +{ + uint8_t pcie_config = 0; + + /* Default set to PCIE_CONFIG_C first */ + mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_x4x4x4x4; + mupd->FspmConfig.IioConfigIOU1[0] = IIO_BIFURCATE_x4x4x4x4; + mupd->FspmConfig.IioConfigIOU2[0] = IIO_BIFURCATE_xxxxxxxx; + mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxx16; + mupd->FspmConfig.IioConfigIOU4[0] = IIO_BIFURCATE_xxxxxxxx; + /* Update IIO bifurcation according to different Configs */ + if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { + printk(BIOS_DEBUG, "get IPMI PCIe config: %d\n", pcie_config); + switch (pcie_config) { + case PCIE_CONFIG_A: + mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx; + mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxxxx; + break; + case PCIE_CONFIG_B: + mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx; + mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4; + break; + case PCIE_CONFIG_D: + mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4; + break; + case PCIE_CONFIG_C: + default: + break; + } + } else { + printk(BIOS_ERR, "%s failed to get IPMI PCIe config\n", __func__); + } +} + /* * Configure GPIO depend on platform */ @@ -17,6 +55,7 @@ /* Send FSP log message to SOL */ mupd->FspmConfig.SerialIoUartDebugEnable = 1; mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + oem_update_iio(mupd); } void mainboard_memory_init_params(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/41527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Gerrit-Change-Number: 41527 Gerrit-PatchSet: 22 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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