Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC use LPCflash utility to flash FW, it use LPC to send the bridge IC image form host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support.
TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.
[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC
Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3).
iBytesRead (0x00007c00).
Discovering LPC boot loader. Discovered @ 0x3f8.
Configuring LPC boot loader. Configured @ 0x00000600.
Sending header block. Sent.
Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete.
Update done!
Signed-off-by: Bryant Ou Bryant.Ou.Q@gmail.com Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42856/1
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 031d11a..5682ca7 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -37,6 +37,7 @@ register "coherency_support" = "0" register "ats_support" = "0"
+ register "gen1_dec" = "0x00FC0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS
device cpu_cluster 0 on
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
Patch Set 1: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@9 PS1, Line 9: use uses
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@9 PS1, Line 9: it uses
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@10 PS1, Line 10: form from
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@10 PS1, Line 10: bridge IC What's a "bridge IC"? Is it a BMC, or is it another kind of chip?
https://review.coreboot.org/c/coreboot/+/42856/1/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42856/1/src/mainboard/ocp/deltalake... PS1, Line 40: 0x00FC0601 nit: since the value below is in lowercase, make this one lowercase too?
Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Ryback Hung, Philipp Deppenwiese, Angel Pons, Rocky Phagura, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42856
to look at the new patch set (#2).
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support.
TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.
[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC
Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3).
iBytesRead (0x00007c00).
Discovering LPC boot loader. Discovered @ 0x3f8.
Configuring LPC boot loader. Configured @ 0x00000600.
Sending header block. Sent.
Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete.
Update done!
Signed-off-by: Bryant Ou Bryant.Ou.Q@gmail.com Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42856/2
Hello build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Ryback Hung, Philipp Deppenwiese, Angel Pons, Rocky Phagura, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42856
to look at the new patch set (#3).
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support.
TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.
[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC
Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3).
iBytesRead (0x00007c00).
Discovering LPC boot loader. Discovered @ 0x3f8.
Configuring LPC boot loader. Configured @ 0x00000600.
Sending header block. Sent.
Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete.
Update done!
Signed-off-by: Bryant Ou Bryant.Ou.Q@gmail.com Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42856/3
Bryant Ou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@9 PS1, Line 9: it
uses
Done
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@9 PS1, Line 9: use
uses
Done
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@10 PS1, Line 10: bridge IC
What's a "bridge IC"? Is it a BMC, or is it another kind of chip?
Yes, it's another chip.
https://review.coreboot.org/c/coreboot/+/42856/1//COMMIT_MSG@10 PS1, Line 10: form
from
Done
https://review.coreboot.org/c/coreboot/+/42856/1/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42856/1/src/mainboard/ocp/deltalake... PS1, Line 40: 0x00FC0601
nit: since the value below is in lowercase, make this one lowercase too?
Done
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
Patch Set 3: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
Patch Set 3: Code-Review+1
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42856 )
Change subject: mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC ......................................................................
mb/ocp/deltalake: Enable LPC IO 0x600 decode for BIC
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support.
TEST=Use LPCflash utility to flash BIC FW on YV3 successfully.
[root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC
Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3).
iBytesRead (0x00007c00).
Discovering LPC boot loader. Discovered @ 0x3f8.
Configuring LPC boot loader. Configured @ 0x00000600.
Sending header block. Sent.
Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete.
Update done!
Signed-off-by: Bryant Ou Bryant.Ou.Q@gmail.com Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jonathan Zhang jonzhang@fb.com Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve Jonathan Zhang: Looks good to me, but someone else must approve
diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index 2586b73..f1b201d 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -36,6 +36,7 @@ register "coherency_support" = "0" register "ats_support" = "0"
+ register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS
device cpu_cluster 0 on
-
Angel Pons (Code Review) -
Bryant Ou (Code Review)
-
Jonathan Zhang (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)
-
Philipp Deppenwiese (Code Review)