Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43152 )
Change subject: nb/intel/haswell/acpi: Update to ASL 2.0 syntax ......................................................................
nb/intel/haswell/acpi: Update to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43152/1
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 0f2ed16..b8a1af8 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -140,7 +140,7 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Local0 = One /* Start at P1 */ + Local0 = 1 /* Start at P1 */ Local1 = SizeOf (_SB.CP00._PSS)
While (Local0 < Local1) { @@ -252,7 +252,7 @@ Return (0) }
- Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit"
/* Set _PPC to LFM */ Local0 = PSSS (LFM_) @@ -280,7 +280,7 @@ Return (0) }
- Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit"
/* Clear PL1 CLAMP bit */ PL1C = 0
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43152 )
Change subject: nb/intel/haswell/acpi: Update to ASL 2.0 syntax ......................................................................
Patch Set 1: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43152 )
Change subject: nb/intel/haswell/acpi: Update to ASL 2.0 syntax ......................................................................
Patch Set 1: Code-Review+2
hrmm, and here the dead definitions could actually be used but are not. Generally, that would make the code more secure, but if somebody can change PCI 0.0 config space, it's probably too late anyway...
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43152 )
Change subject: nb/intel/haswell/acpi: Update to ASL 2.0 syntax ......................................................................
nb/intel/haswell/acpi: Update to ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ibcc54c2332945fff28d6502edb7eefa06f764bdd Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43152 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 0f2ed16..b8a1af8 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */
- OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -140,7 +140,7 @@ External (_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Local0 = One /* Start at P1 */ + Local0 = 1 /* Start at P1 */ Local1 = SizeOf (_SB.CP00._PSS)
While (Local0 < Local1) { @@ -252,7 +252,7 @@ Return (0) }
- Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit"
/* Set _PPC to LFM */ Local0 = PSSS (LFM_) @@ -280,7 +280,7 @@ Return (0) }
- Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit"
/* Clear PL1 CLAMP bit */ PL1C = 0