Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and ad...
Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc
CPX-SP FSP ww26 release added UPD to allow FSP serial redirection. Also update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf --- M src/mainboard/ocp/deltalake/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 27 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42840/1
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index b6ea3ec..ebe2c80 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -14,6 +14,10 @@
static void mainboard_config_iio(FSPM_UPD *mupd) { + /* Send FSP log message to SOL */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + /* Enable only PCH: PCIE[8:11] */ for (uint8_t i = 0; i < 20; i++) { if (i >= 8 && i <= 11) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index fd84f1a..18f8167 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -594,7 +594,7 @@ **/ UINT8 NtbXlinkCtlOverride;
-/** Offset 0x0100 - PchAdrEn +/** Offset 0x0100 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; @@ -633,7 +633,23 @@ **/ UINT8 PchPciePortLinkSpeed[20];
-/** Offset 0x0140 +/** Offset 0x0140 - SerialIoUartDebugEnable + Enable SerialIo Uart debug library in FSP. + 0:Disable, 1:Enable +**/ + UINT8 SerialIoUartDebugEnable; + +/** Offset 0x0141 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x0142 - ISA Serial Base selection + Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 + 0x3F8, 0x2F8 +**/ + UINT16 SerialIoUartDebugIoBase; + +/** Offset 0x0144 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -654,9 +670,9 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0150 +/** Offset 0x0154 **/ - UINT8 UnusedUpdSpace3[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x0156 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index e9c7dbf..ee86a6d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -85,7 +85,7 @@
/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { - UINT8 reserved1[61]; + UINT8 reserved1[58];
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. @@ -99,11 +99,11 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
- UINT8 reserved3[24417]; + UINT8 reserved3[24514];
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 reserved4[10]; + UINT8 reserved4[2];
} SYSTEM_MEMORY_MAP_HOB;
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... PS2, Line 17: SOL Serial Over LAN?
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... PS2, Line 17: SOL
Serial Over LAN?
Yes, it is Serial Over LAN. From BMC console, I can run "sol-util slotx" command to get to the host console.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... File src/mainboard/ocp/deltalake/romstage.c:
https://review.coreboot.org/c/coreboot/+/42840/2/src/mainboard/ocp/deltalake... PS2, Line 17: SOL
Yes, it is Serial Over LAN. […]
Ah, since SerialIO is something else I was confused
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 2: Code-Review+2
Hello Philipp Deppenwiese, build bot (Jenkins), Christian Walter, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42840
to look at the new patch set (#3).
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf --- M src/mainboard/ocp/deltalake/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 26 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42840/3
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
Patch Set 4: Code-Review+2
Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42840 )
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter christian.walter@9elements.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/deltalake/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 26 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Christian Walter: Looks good to me, approved
diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 35c7e2d..fb9a549 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -14,7 +14,9 @@
static void mainboard_config_iio(FSPM_UPD *mupd) { - /* To be implemented */ + /* Send FSP log message to SOL */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; }
void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index fd84f1a..18f8167 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -594,7 +594,7 @@ **/ UINT8 NtbXlinkCtlOverride;
-/** Offset 0x0100 - PchAdrEn +/** Offset 0x0100 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; @@ -633,7 +633,23 @@ **/ UINT8 PchPciePortLinkSpeed[20];
-/** Offset 0x0140 +/** Offset 0x0140 - SerialIoUartDebugEnable + Enable SerialIo Uart debug library in FSP. + 0:Disable, 1:Enable +**/ + UINT8 SerialIoUartDebugEnable; + +/** Offset 0x0141 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x0142 - ISA Serial Base selection + Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 + 0x3F8, 0x2F8 +**/ + UINT16 SerialIoUartDebugIoBase; + +/** Offset 0x0144 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -654,9 +670,9 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0150 +/** Offset 0x0154 **/ - UINT8 UnusedUpdSpace3[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x0156 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index e9c7dbf..ee86a6d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -85,7 +85,7 @@
/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { - UINT8 reserved1[61]; + UINT8 reserved1[58];
UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. @@ -99,11 +99,11 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES];
- UINT8 reserved3[24417]; + UINT8 reserved3[24514];
UINT32 MmiohBase; // MMIOH base in 64MB granularity
- UINT8 reserved4[10]; + UINT8 reserved4[2];
} SYSTEM_MEMORY_MAP_HOB;
-
Angel Pons (Code Review) -
Christian Walter (Code Review)
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Jonathan Zhang (Code Review)
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Philipp Deppenwiese (Code Review)