coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: Kconfig: hide most options for non-developers
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28636 ) Change subject: Kconfig: hide most options for non-developers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d7a298807185419ecc400a9072269b32c7d71d4 Gerrit-Change-Number: 28636 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/mainboard/*: show blobby boards only if USE_BLOBS is enabled
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28637 ) Change subject: src/mainboard/*: show blobby boards only if USE_BLOBS is enabled ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b6b944ca1ee4281f6e52701f22b65133a43fff Gerrit-Change-Number: 28637 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 07 Jul '20

07 Jul '20

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/29669/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29669/15//COMMIT_MSG@19 PS15, Line 19: Tested on ThinkPad X220. > Also mention W530? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 16 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 07 Jul 2020 11:40:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 07 Jul '20

07 Jul '20

Evgeny Zinoviev has uploaded a new patch set (#16) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Tested on ThinkPad X220 (i5-2520M) and ThinkPad W530 (i7-3940XM). Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.default M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.default M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.default M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.default M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 22 files changed, 84 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 16 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... util/inteltool: Support dumping more BARs on Skylake mobile SoCs Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y. These chipsets are similar to others supported by the tool. Working on SKL-U. Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/memory.c M util/inteltool/pcie.c 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 1bd127b..728d4d6 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -207,10 +207,12 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: - case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index e5828cc..d392c28 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -251,6 +251,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: @@ -380,6 +382,8 @@ dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: @@ -493,6 +497,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: update telemetry settings for dalboz
by chris wang (Code Review) 07 Jul '20

07 Jul '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42999 to review the following change. Change subject: mb/google/zork: update telemetry settings for dalboz ...................................................................... mb/google/zork: update telemetry settings for dalboz update telemetry value for SDLE test result. BUG=b:152922299,b:152369472 BRANCH=trembyle-bringup TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca --- M src/mainboard/google/zork/variants/dalboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42999/1 diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 587d1c5..81fc4fd 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -17,10 +17,10 @@ # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32239" #mA - register "telemetry_vddcr_vdd_offset" = "0-37" - register "telemetry_vddcr_soc_slope" = "22313" #mA - register "telemetry_vddcr_soc_offset" = "0-209" + register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_offset" = "0-1" + register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/42999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca Gerrit-Change-Number: 42999 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 07 Jul '20

07 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 15: Note that puff-cq might fail due to the size increase of depthcharge.elf. This happened to me when I tried to enable this with Groot UI, even with the lowered bmpblk screen resolution (CL:2282241). -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:48:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan stub
by Werner Zeh (Code Review) 07 Jul '20

07 Jul '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42271 ) Change subject: lib: Add ASan stub ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/42271/7/src/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/42271/7/src/Kconfig@261 PS7, Line 261: ~1.5x performance slowdown. > Please mention the needed gcc patch here in this commit or in one of the following ones so that the […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Gerrit-Change-Number: 42271 Gerrit-PatchSet: 7 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 07 Jul '20

07 Jul '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 18: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 07 Jul '20

07 Jul '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41062 to look at the new patch set (#17). Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... soc/intel/jasperlake: Apply FiVR related settings Set optimized values for FiVR to shut the VCCIN_AUX_SHUTDOWN power rails during SOix. TEST=Build and boot dedede and check VCCIN_AUX_SHUTDOWN rails are shut. Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/romstage/fsp_params.c 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41062/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 17 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2020