coreboot-gerrit July 2020

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Change in coreboot[master]: drivers/intel/mipi_camera: Handle acpi_name and common code
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: Handle acpi_name and common code ...................................................................... drivers/intel/mipi_camera: Handle acpi_name and common code This change updates the mipi_camera driver to handle acpi_name based on device_type, if acpi_name is not set in the devicetree and moves some of the common code to separate methods. Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 130 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 61f72ab..4356b0a 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -7,12 +7,27 @@ #include <device/i2c_simple.h> #include <device/device.h> #include <device/path.h> +#include <device/pci_def.h> #include "chip.h" -static void camera_fill_ssdt(const struct device *dev) +static void write_pci_camera_device(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); + + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); + return; + } + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_ADR_pci_device(dev); + acpigen_write_name_string("_DDN", config->device_type == INTEL_ACPI_CAMERA_CIO2 ? + "Camera and Imaging Subsystem" : "Imaging Unit"); +} + +static void write_i2c_camera_device(const struct device *dev, const char *scope) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, @@ -20,13 +35,23 @@ .resource = scope, }; - if (!dev->enabled || !scope) + if (dev->path.type != DEVICE_PATH_I2C) { + printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); return; + } - /* Device */ - acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_string("_HID", config->acpi_hid); + + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) + acpigen_write_name_integer("_ADR", 0); + + if (config->acpi_hid) + acpigen_write_name_string("_HID", config->acpi_hid); + else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); + else if (config->device_type == INTEL_ACPI_CAMERA_NVM) + acpigen_write_name_string("_HID", "INT3499"); + acpigen_write_name_integer("_UID", config->acpi_uid); acpigen_write_name_string("_DDN", config->chip_name); acpigen_write_STA(acpi_device_status(dev)); @@ -35,35 +60,111 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); - acpigen_write_resourcetemplate_footer(); - /* Mark it as Camera related device */ - acpigen_write_name_integer("CAMD", config->device_type); - - /* Create Device specific data */ - if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) { - acpigen_write_method_serialized("SSDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, - sizeof(config->ssdb)); - acpigen_pop_len(); /* Method */ + /* + * The optional vcm/nvram devices are presumed to be on the same I2C bus as the camera + * sensor. + */ + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.vcm_type && config->vcm_address) { + struct acpi_i2c i2c_vcm = i2c; + i2c_vcm.address = config->vcm_address; + acpi_device_write_i2c(&i2c_vcm); } - /* Fill Power Sequencing Data */ - acpigen_write_method_serialized("PWDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, - (sizeof(struct intel_pwdb) * config->num_pwdb_entries)); - acpigen_pop_len(); /* Method */ + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.rom_type && config->rom_address) { + struct acpi_i2c i2c_rom = i2c; + i2c_rom.address = config->rom_address; + acpi_device_write_i2c(&i2c_rom); + } + + acpigen_write_resourcetemplate_footer(); +} + +static void write_camera_device_common(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + + /* Mark it as Camera related device */ + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU || + config->device_type == INTEL_ACPI_CAMERA_SENSOR || + config->device_type == INTEL_ACPI_CAMERA_VCM) { + acpigen_write_name_integer("CAMD", config->device_type); + } +} + +static void camera_fill_ssdt(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU) + write_pci_camera_device(dev); + else + write_i2c_camera_device(dev, scope); + + write_camera_device_common(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev), - dev->chip_ops->name, dev->path.i2c.device); + + if (dev->path.type == DEVICE_PATH_PCI) { + printk(BIOS_INFO, "%s: %s PCI address 0%x\n", acpi_device_path(dev), + dev->chip_ops->name, dev->path.pci.devfn); + } else { + printk(BIOS_INFO, "%s: %s I2C address 0%xh\n", acpi_device_path(dev), + dev->chip_ops->name, dev->path.i2c.device); + } } static const char *camera_acpi_name(const struct device *dev) { + const char *prefix = NULL; + static char name[5]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; - return config->acpi_name; + + if (config->acpi_name) + return config->acpi_name; + + switch (config->device_type) { + case INTEL_ACPI_CAMERA_CIO2: + return "CIO2"; + case INTEL_ACPI_CAMERA_IMGU: + return "IMGU"; + case INTEL_ACPI_CAMERA_PMIC: + return "PMIC"; + case INTEL_ACPI_CAMERA_SENSOR: + prefix = "CAM"; + break; + case INTEL_ACPI_CAMERA_VCM: + prefix = "VCM"; + break; + case INTEL_ACPI_CAMERA_NVM: + prefix = "NVM"; + break; + default: + printk(BIOS_ERR, "Invalid device type: %x\n", config->device_type); + return NULL; + } + + /* + * The camera # knows which link # they use, so that's used as the basis for the + * instance #. The VCM and NVM don't have this information, so the best we can go on is + * the _UID. + */ + snprintf(name, sizeof(name), "%s%1u", prefix, + config->device_type == INTEL_ACPI_CAMERA_SENSOR ? + config->ssdb.link_used : config->acpi_uid); + return name; } static struct device_operations camera_ops = { diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 7b6c5d5..c029570 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -12,6 +12,7 @@ INTEL_ACPI_CAMERA_IMGU, INTEL_ACPI_CAMERA_SENSOR, INTEL_ACPI_CAMERA_VCM, + INTEL_ACPI_CAMERA_NVM, INTEL_ACPI_CAMERA_PMIC = 100, }; @@ -90,6 +91,10 @@ const char *acpi_name; const char *chip_name; unsigned int acpi_uid; + const char *remote_name; /* default "\_SB.PCI0.CIO2" */ + const char *vcm_name; /* defaults to |vcm_address| device */ + uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ + uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */ }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 33 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Kconfig: hide most options for non-developers
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28636 ) Change subject: Kconfig: hide most options for non-developers ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d7a298807185419ecc400a9072269b32c7d71d4 Gerrit-Change-Number: 28636 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/mainboard/*: show blobby boards only if USE_BLOBS is enabled
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/28637 ) Change subject: src/mainboard/*: show blobby boards only if USE_BLOBS is enabled ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/28637 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10b6b944ca1ee4281f6e52701f22b65133a43fff Gerrit-Change-Number: 28637 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 07 Jul '20

07 Jul '20

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/29669/15//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29669/15//COMMIT_MSG@19 PS15, Line 19: Tested on ThinkPad X220. > Also mention W530? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 16 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 07 Jul 2020 11:40:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 07 Jul '20

07 Jul '20

Evgeny Zinoviev has uploaded a new patch set (#16) to the change originally created by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... cpu/intel/sandybridge: Add `hyper_threading` option More and more people request an option to disable HT. To implement that we have to toggle a bit in a `soft reset` register in the PCH that can override certain default settings of the CPU when it comes out of reset. The `soft reset` register is already used for other settings. So we have to take care that all settings are gathered before we issue the reset. Note, the current code using `soft reset` for flex ratio selection seems incomplete. Tested on ThinkPad X220 (i5-2520M) and ThinkPad W530 (i7-3940XM). Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M src/cpu/intel/model_206ax/bootblock.c M src/mainboard/lenovo/l520/cmos.default M src/mainboard/lenovo/l520/cmos.layout M src/mainboard/lenovo/t420/cmos.default M src/mainboard/lenovo/t420/cmos.layout M src/mainboard/lenovo/t420s/cmos.default M src/mainboard/lenovo/t420s/cmos.layout M src/mainboard/lenovo/t430/cmos.default M src/mainboard/lenovo/t430/cmos.layout M src/mainboard/lenovo/t430s/cmos.default M src/mainboard/lenovo/t430s/cmos.layout M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t520/cmos.layout M src/mainboard/lenovo/t530/cmos.default M src/mainboard/lenovo/t530/cmos.layout M src/mainboard/lenovo/x1_carbon_gen1/cmos.default M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout M src/mainboard/lenovo/x220/cmos.default M src/mainboard/lenovo/x220/cmos.layout M src/mainboard/lenovo/x230/cmos.default M src/mainboard/lenovo/x230/cmos.layout M src/southbridge/intel/bd82x6x/pch.h 22 files changed, 84 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29669/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 16 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Patrick Georgi (Code Review) 07 Jul '20

07 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... util/inteltool: Support dumping more BARs on Skylake mobile SoCs Support dumping MCHBAR, EPBAR, DMIBAR and PCIEXBAR on SKL-U/Y. These chipsets are similar to others supported by the tool. Working on SKL-U. Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/inteltool/memory.c M util/inteltool/pcie.c 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 1bd127b..728d4d6 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -207,10 +207,12 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: - case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index e5828cc..d392c28 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -251,6 +251,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: @@ -380,6 +382,8 @@ dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ break; case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: @@ -493,6 +497,8 @@ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: update telemetry settings for dalboz
by chris wang (Code Review) 07 Jul '20

07 Jul '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42999 to review the following change. Change subject: mb/google/zork: update telemetry settings for dalboz ...................................................................... mb/google/zork: update telemetry settings for dalboz update telemetry value for SDLE test result. BUG=b:152922299,b:152369472 BRANCH=trembyle-bringup TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca --- M src/mainboard/google/zork/variants/dalboz/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42999/1 diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 587d1c5..81fc4fd 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -17,10 +17,10 @@ # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32239" #mA - register "telemetry_vddcr_vdd_offset" = "0-37" - register "telemetry_vddcr_soc_slope" = "22313" #mA - register "telemetry_vddcr_soc_offset" = "0-209" + register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_offset" = "0-1" + register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/42999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca Gerrit-Change-Number: 42999 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 07 Jul '20

07 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 15: Note that puff-cq might fail due to the size increase of depthcharge.elf. This happened to me when I tried to enable this with Groot UI, even with the lowered bmpblk screen resolution (CL:2282241). -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:48:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan stub
by Werner Zeh (Code Review) 07 Jul '20

07 Jul '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42271 ) Change subject: lib: Add ASan stub ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/42271/7/src/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/42271/7/src/Kconfig@261 PS7, Line 261: ~1.5x performance slowdown. > Please mention the needed gcc patch here in this commit or in one of the following ones so that the […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/42271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Gerrit-Change-Number: 42271 Gerrit-PatchSet: 7 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:10:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 07 Jul '20

07 Jul '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 18: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 08:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2020