coreboot-gerrit July 2020

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Change in coreboot[master]: Documentation/security/vboot: Add device list
by Marcello Sylvester Bauer (Code Review) 07 Jul '20

07 Jul '20

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39200 ) Change subject: Documentation/security/vboot: Add device list ...................................................................... Documentation/security/vboot: Add device list Add a list of VBOOT enabled devices to the documetation. Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Signed-off-by: Marcello Sylvester Bauer <sylv(a)sylv.io> --- M Documentation/security/vboot/index.md 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/39200/1 diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md index 400c2b5..75f34cc 100644 --- a/Documentation/security/vboot/index.md +++ b/Documentation/security/vboot/index.md @@ -342,3 +342,99 @@ any firmware may be placed on the device. However, accessing this screw requires opening the case and voids the system warranty! + +## VBOOT enabled devices + +### AAEON +- UP Square + +### emulation +- qemu-i440fx +- qemu-q35 + +### facebook +- monolith + +### Google +- auron +- beltino +- butterfly +- cheza +- cyan +- daisy +- dragonegg +- drallion +- eve +- fizz +- foster +- gale +- glados +- gru +- hatch +- jecht +- kahlee +- kukui +- link +- mistral +- nyan_big +- nyan_blaze +- nyan +- oak +- parrot +- peach_pit +- poppy +- rambi +- reef +- sarien +- slippy +- smaug +- storm +- stout +- trogdor +- veyron +- veyron_mickey +- veyron_rialto + +### HP +- z220_sff_workstation + +### Intel +- baskingridge +- cannonlake_rvp +- coffeelake_rvp +- emeraldlake2 +- galileo +- glkrvp +- icelake_rvp +- jasperlake_rvp +- kblrvp +- kunimitsu +- strago +- tglrvp +- wtm2 + +### Lenovo +- t400 +- t410 +- t420 +- t420s +- t520 +- x200 +- x201 +- x220 + +### OpenCellular +- elgon + +### Samsung +- lumpy +- stumpy + +### Siemens +- mc_apl2 +- mc_apl4 +- mc_apl5 +- mc_apl6 + +### Supermicro +- x11-lga1151 -- To view, visit https://review.coreboot.org/c/coreboot/+/39200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93 Gerrit-Change-Number: 39200 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylv(a)sylv.io> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: src/**/acpi/smbus.asl: Drop dead code
by Angel Pons (Code Review) 07 Jul '20

07 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43024 ) Change subject: src/**/acpi/smbus.asl: Drop dead code ...................................................................... src/**/acpi/smbus.asl: Drop dead code The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code isn't even being tested. So, throw it into the bitbucket before it rots any further. If anyone needs that code ever again, it's in git history. Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi/smbus.asl M src/soc/intel/denverton_ns/acpi/smbus.asl M src/soc/intel/skylake/acpi/smbus.asl M src/southbridge/intel/common/acpi/smbus.asl 4 files changed, 0 insertions(+), 856 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/43024/1 diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/acpi/smbus.asl index 83c8991..32b0b9c 100644 --- a/src/soc/intel/broadwell/acpi/smbus.asl +++ b/src/soc/intel/broadwell/acpi/smbus.asl @@ -5,218 +5,4 @@ Device (SBUS) { Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif } diff --git a/src/soc/intel/denverton_ns/acpi/smbus.asl b/src/soc/intel/denverton_ns/acpi/smbus.asl index 6397622..7860f60 100644 --- a/src/soc/intel/denverton_ns/acpi/smbus.asl +++ b/src/soc/intel/denverton_ns/acpi/smbus.asl @@ -5,218 +5,4 @@ Device (SBUS) { Name (_ADR, 0x001f0004) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif } diff --git a/src/soc/intel/skylake/acpi/smbus.asl b/src/soc/intel/skylake/acpi/smbus.asl index 6397622..7860f60 100644 --- a/src/soc/intel/skylake/acpi/smbus.asl +++ b/src/soc/intel/skylake/acpi/smbus.asl @@ -5,218 +5,4 @@ Device (SBUS) { Name (_ADR, 0x001f0004) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - Or (HCNT, 0x02, HCNT) // Send Kill - Or (HSTS, 0xff, HSTS) // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Store (4000, Local0) // Timeout 200ms in 50us steps - While (Local0) { - If (And(HSTS, 0x02)) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Decrement (Local0) - If (LEqual(Local0, 0)) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Store (200, Local0) // Timeout 200ms - While (Local0) { - If (And(HSTS, 0x40)) { // IN_USE? - Sleep(1) // Wait 1ms - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - Return (1) - } - } Else { - Store (0, Local0) // We're ready - } - } - - Store (4000, Local0) // Timeout 200ms (50us * 4000) - While (Local0) { - If (And (HSTS, 0x01)) { // Host Busy? - Stall(50) // Wait 50us - Decrement(Local0) // timeout-- - If (LEqual(Local0, 0)) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Data - - Store (0x48, HCNT) // Start + Byte Data Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - - Store (0x44, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Arg0, TXSA) // Write Address - Store (Arg1, HCMD) // Write Command - Store (Arg2, DAT0) // Write Data - - Store (0x48, HCNT) // Start + Byte Protocol - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - Store (0, I2CE) // SMBus Enable - Store (0xbf, HSTS) - Store (Or (Arg0, 1), TXSA) // Write Address - Store (Arg1, HCMD) // Command - - Store (0x48, HCNT) // Start - - If (CMPL()) { - Or (HSTS, 0xff, HSTS) // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif } diff --git a/src/southbridge/intel/common/acpi/smbus.asl b/src/southbridge/intel/common/acpi/smbus.asl index cc9c4e2..32b0b9c 100644 --- a/src/southbridge/intel/common/acpi/smbus.asl +++ b/src/southbridge/intel/common/acpi/smbus.asl @@ -5,218 +5,4 @@ Device (SBUS) { Name (_ADR, 0x001f0003) - -#ifdef ENABLE_SMBUS_METHODS - OperationRegion (SMBP, PCI_Config, 0x00, 0x100) - Field(SMBP, DWordAcc, NoLock, Preserve) - { - Offset(0x40), - , 2, - I2CE, 1 - } - - OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20) - Field (SMBI, ByteAcc, NoLock, Preserve) - { - HSTS, 8, // Host Status - , 8, - HCNT, 8, // Host Control - HCMD, 8, // Host Command - TXSA, 8, // Transmit Slave Address - DAT0, 8, // Host Data 0 - DAT1, 8, // Host Data 1 - HBDB, 8, // Host Block Data Byte - PECK, 8, // Packet Error Check - RXSA, 8, // Receive Slave Address - RXDA, 16, // Receive Slave Data - AUXS, 8, // Auxiliary Status - AUXC, 8, // Auxiliary Control - SLPC, 8, // SMLink Pin Control - SBPC, 8, // SMBus Pin Control - SSTS, 8, // Slave Status - SCMD, 8, // Slave Command - NADR, 8, // Notify Device Address - NDLB, 8, // Notify Data Low Byte - NDLH, 8, // Notify Data High Byte - } - - // Kill all SMBus communication - Method (KILL, 0, Serialized) - { - HCNT |= 0x02 // Send Kill - HSTS |= 0xff // Clean Status - } - - // Check if last operation completed - // return Failure = 0, Success = 1 - Method (CMPL, 0, Serialized) - { - Local0 = 4000 // Timeout 200ms in 50us steps - While (Local0) { - If (HSTS & 0x02) { // Completion Status? - Return (1) // Operation Completed - } Else { - Stall (50) - Local0-- - If (Local0 == 0) { - KILL() - } - } - } - - Return (0) // Failure - } - - - // Wait for SMBus to become ready - Method (SRDY, 0, Serialized) - { - Local0 = 200 // Timeout 200ms - While (Local0) { - If (HSTS & 0x40) { // IN_USE? - Sleep(1) // Wait 1ms - Local0-- // timeout-- - If (Local0 == 0) { - Return (1) - } - } Else { - Local0 = 0 // We're ready - } - } - - Local0 = 4000 // Timeout 200ms (50us * 4000) - While (Local0) { - If (HSTS & 0x01) { // Host Busy? - Stall(50) // Wait 50us - Local0-- // timeout-- - If (Local0 == 0) { - KILL() - } - } Else { - Return (0) // Success - } - } - - Return (1) // Failure - } - - // SMBus Send Byte - // Arg0: Address - // Arg1: Data - // Return: 1 = Success, 0=Failure - - Method (SSXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - I2CE = 0 // SMBus Enable - HSTS = 0xbf - TXSA = Arg0 // Write Address - HCMD = Arg1 // Write Data - - HCNT = 0x48 // Start + Byte Data Protocol - - If (CMPL()) { - HSTS |= 0xff // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Receive Byte - // Arg0: Address - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRXB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - I2CE = 0 // SMBus Enable - HSTS = 0xbf - TXSA = Arg0 | 1 // Write Address - - HCNT = 0x44 // Start - - If (CMPL()) { - HSTS |= 0xff // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } - - - // SMBus Write Byte - // Arg0: Address - // Arg1: Command - // Arg2: Data - // Return: 1 = Success, 0=Failure - - Method (SWRB, 3, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0) - } - - // Send Byte - I2CE = 0 // SMBus Enable - HSTS = 0xbf - TXSA = Arg0 // Write Address - HCMD = Arg1 // Write Command - DAT0 = Arg2 // Write Data - - HCNT = 0x48 // Start + Byte Protocol - - If (CMPL()) { - HSTS |= 0xff // Clean up - Return (1) // Success - } - - Return (0) - } - - - // SMBus Read Byte - // Arg0: Address - // Arg1: Command - // Return: 0xffff = Failure, Data (8bit) = Success - - Method (SRDB, 2, Serialized) - { - - // Is the SMBus Controller Ready? - If (SRDY()) { - Return (0xffff) - } - - // Receive Byte - I2CE = 0 // SMBus Enable - HSTS = 0xbf - TXSA = Arg0 | 1 // Write Address - HCMD = Arg1 // Command - - HCNT = 0x48 // Start - - If (CMPL()) { - HSTS |= 0xff // Clean up - Return (DAT0) // Success - } - - Return (0xffff) - } -#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/43024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01 Gerrit-Change-Number: 43024 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_*
by Angel Pons (Code Review) 07 Jul '20

07 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42144 ) Change subject: mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_* ...................................................................... mb/google/poppy: Drop VARIANT_SPECIFIC_OPTIONS_* Putting variant-specific options in Kconfig.name seems to be what is popular now, so we might as well do the same for Poppy. Change-Id: I8ce3237ac620c26856b6cf3d08293729641dd0b0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/Kconfig.name 2 files changed, 49 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42144/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 8553821..4298950 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -134,76 +134,6 @@ bool default n -config VARIANT_SPECIFIC_OPTIONS_ATLAS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - -config VARIANT_SPECIFIC_OPTIONS_POPPY - def_bool n - select DRIVERS_I2C_MAX98927 - select NO_FADT_8042 - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NAMI - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NAUTILUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_NOCTURNE - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_SX9310 if CHROMEOS_WIFI_SAR - select DRIVERS_I2C_MAX98373 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select EXCLUDE_NATIVE_SD_INTERFACE - select MAINBOARD_HAS_SPI_TPM_CR50 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR - -config VARIANT_SPECIFIC_OPTIONS_RAMMUS - def_bool n - select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_MAX98927 - select DRIVERS_I2C_DA7219 - select DRIVERS_SPI_ACPI - select DRIVERS_USB_ACPI - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_SPI_TPM_CR50 - -config VARIANT_SPECIFIC_OPTIONS_SORAKA - def_bool n - select DRIVERS_I2C_MAX98927 - select NO_FADT_8042 - select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI - select MAINBOARD_HAS_I2C_TPM_CR50 - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/poppy/Kconfig.name b/src/mainboard/google/poppy/Kconfig.name index 9ecdb44..cf8d2c1 100644 --- a/src/mainboard/google/poppy/Kconfig.name +++ b/src/mainboard/google/poppy/Kconfig.name @@ -3,34 +3,76 @@ config BOARD_GOOGLE_ATLAS bool "-> Atlas (Google Pixelbook Go)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_ATLAS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 + select VARIANT_HAS_CAMERA_ACPI + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_POPPY bool "-> Poppy" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_POPPY + select DRIVERS_I2C_MAX98927 + select NO_FADT_8042 + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 config BOARD_GOOGLE_NAMI bool "-> Nami" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAMI + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_SPI_TPM_CR50 config BOARD_GOOGLE_NAUTILUS bool "-> Nautilus (Samsung Chromebook Plus (V2 / LTE))" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NAUTILUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 config BOARD_GOOGLE_NOCTURNE bool "-> Nocturne (Google Pixel Slate)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_NOCTURNE + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_SX9310 if CHROMEOS_WIFI_SAR + select DRIVERS_I2C_MAX98373 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EXCLUDE_NATIVE_SD_INTERFACE + select MAINBOARD_HAS_SPI_TPM_CR50 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI + select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR config BOARD_GOOGLE_RAMMUS bool "-> Rammus (Asus Chromebook C425, Flip C433, Flip C434)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_RAMMUS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_MAX98927 + select DRIVERS_I2C_DA7219 + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_SPI_TPM_CR50 config BOARD_GOOGLE_SORAKA bool "-> Soraka (HP Chromebook x2)" select BOARD_GOOGLE_BASEBOARD_POPPY - select VARIANT_SPECIFIC_OPTIONS_SORAKA + select DRIVERS_I2C_MAX98927 + select NO_FADT_8042 + select SYSTEM_TYPE_DETACHABLE + select VARIANT_HAS_CAMERA_ACPI + select MAINBOARD_HAS_I2C_TPM_CR50 -- To view, visit https://review.coreboot.org/c/coreboot/+/42144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ce3237ac620c26856b6cf3d08293729641dd0b0 Gerrit-Change-Number: 42144 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: volteer: enable VBOOT_EC_EFS
by Nick Vaccaro (Code Review) 07 Jul '20

07 Jul '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43044 ) Change subject: volteer: enable VBOOT_EC_EFS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71bb169242b2511b4a4102d46a6981d72d07806 Gerrit-Change-Number: 43044 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 22:42:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by build bot (Jenkins) (Code Review) 07 Jul '20

07 Jul '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/42792/15/payloads/libpayload/drive… File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/42792/15/payloads/libpayload/drive… PS15, Line 751: if (equals++ >= (SSZ * SSZ)) Too many leading tabs - consider code refactoring -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 22:34:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Julius Werner (Code Review) 07 Jul '20

07 Jul '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 15: (4 comments) https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 473: > Align with previous line? Done https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 517: from -2 to 4 > Where are the numbers -2 and 4 from? Do you mean […] Yes. I'm trying to only talk about the 6x6 case in all the basic explanations how stuff works to avoid making it too confusing. I'll add a "(for 6x6)" to clarify. https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 628: weigths > weights Done https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 651: dim->height < sy - S0 > Should it be […] Woah... yeah, this should have been dim_org all along. Good find, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 22:16:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Julius Werner (Code Review) 07 Jul '20

07 Jul '20

Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42792 to look at the new patch set (#15). Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... libpayload: cbgfx: Replace bilinear resampling with Lanczos This patch improves the image resampling (scaling) code in CBGFX to use the Lanczos algorithm that is widely considered the "best" resampling algorithm (e.g. also the first choice in Python's PIL library). It is of course much more elaborate and therefore slower than bilinear resampling, but a lot of the difference can be made up with optimizations, and the resulting code was found to still produce acceptable speeds for existing Chrome OS UI use cases. Nevertheless, if this should be too slow for anyone there's also an option to tune it down a little (but still much better than bilinear). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/video/graphics.c 2 files changed, 303 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/42792/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Evgeny Zinoviev (Code Review) 06 Jul '20

06 Jul '20

Evgeny Zinoviev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 15: I've been using this on ThinkPad W530 (i7-3940XM) for more than 2 weeks with different tasks (browsing, videos, virtualization, coding, etc.) and hadn't had a single issue. Please consider reviewing this. -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 15 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Mon, 06 Jul 2020 21:54:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t60: Switch to override tree
by Peter Lemenkov (Code Review) 06 Jul '20

06 Jul '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34779 ) Change subject: mb/lenovo/t60: Switch to override tree ...................................................................... mb/lenovo/t60: Switch to override tree Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/Kconfig R src/mainboard/lenovo/t60/devicetree.cb A src/mainboard/lenovo/t60/variants/t60/overridetree.cb D src/mainboard/lenovo/t60/variants/z61t/devicetree.cb A src/mainboard/lenovo/t60/variants/z61t/overridetree.cb 5 files changed, 135 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/34779/1 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 725528d..ad74f63 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,9 +33,9 @@ default "t60" if BOARD_LENOVO_T60 default "z61t" if BOARD_LENOVO_Z61T -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb similarity index 93% rename from src/mainboard/lenovo/t60/variants/t60/devicetree.cb rename to src/mainboard/lenovo/t60/devicetree.cb index 9279dcb..70900ea 100644 --- a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -116,7 +116,6 @@ end register "scr" = "0x0844d070" register "mrr" = "0x01d01002" - end end device pci 1e.2 off end # AC'97 Audio @@ -159,10 +158,6 @@ register "eventb_enable" = "0xff" register "eventc_enable" = "0x3c" register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR @@ -209,21 +204,12 @@ end end end - device pci 1f.1 on # IDE - subsystemid 0x17aa 0x200c - end device pci 1f.2 on # SATA subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff }" - register "regs" = "{ 0x2e, 0xf7, 0x3c, - 0x20, 0x01, 0x00, 0x1b, 0x01, - 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end # eeprom, 8 virtual devices, same chip diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb new file mode 100644 index 0000000..eee3a4d --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 4 + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb deleted file mode 100644 index d35c62b..0000000 --- a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2017 - end - - device pci 01.0 on # PEG - device pci 00.0 on end # VGA - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # PCI Express Port 1 - subsystemid 0x17aa 0x2011 - end - device pci 1c.1 on # PCI Express Port 2 - subsystemid 0x17aa 0x2011 - end - device pci 1c.2 on # PCI Express Port 3 - subsystemid 0x17aa 0x2011 - end - device pci 1c.3 on # PCI Express Port 4 - subsystemid 0x17aa 0x2011 - end - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2013 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff }" - # vendor clockgen setup - register "regs" = "{ 0x6d, 0xff, 0xff, - 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb new file mode 100644 index 0000000..d29df3b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2017 + end + device pci 01.0 on # PEG + device pci 00.0 on end # VGA + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # PCI Express Port 1 + subsystemid 0x17aa 0x2011 + end + device pci 1c.1 on # PCI Express Port 2 + subsystemid 0x17aa 0x2011 + end + device pci 1c.2 on # PCI Express Port 3 + subsystemid 0x17aa 0x2011 + end + device pci 1c.3 on # PCI Express Port 4 + subsystemid 0x17aa 0x2011 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2013 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 3 + end + end + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + # vendor clockgen setup + register "regs" = "{ 0x6d, 0xff, 0xff, + 0x20, 0x41, 0x7f, 0x18, 0x00 }" + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/34779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Gerrit-Change-Number: 34779 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: volteer: enable VBOOT_EC_EFS
by Tim Wawrzynczak (Code Review) 06 Jul '20

06 Jul '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43044 ) Change subject: volteer: enable VBOOT_EC_EFS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/43044/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43044/1//COMMIT_MSG@12 PS1, Line 12: TEST=used "V=1 emerge-${BOARD} coreboot" to verify "-DEC_EFS=1" is : used when compiling 2ec_sync.c > LoL, ya 😊 […] Haha, that was my implicit question I guess, did it just dump you straight into recovery or not, because exactly that, this is the Kconfig option for EFS1, which I don't remember how it works. -- To view, visit https://review.coreboot.org/c/coreboot/+/43044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71bb169242b2511b4a4102d46a6981d72d07806 Gerrit-Change-Number: 43044 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 21:33:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2020