coreboot-gerrit July 2020

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 06 Jul '20

06 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 15 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 Jul 2020 04:54:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb
by David Wu (Code Review) 06 Jul '20

06 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42302 ) Change subject: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb ...................................................................... mb/google/volteer/var/terrador: update gpio setting and overridetree.cb Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador. BUG=b:b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 227 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/1 diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index a54aeca..198d7e1 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -1,15 +1,156 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> +#include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> /* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> ESPI_RST_L */ + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A23 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_A23, NONE), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B5 : ISH_I2C0_CVF_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D17 : ISH_GP4 ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E8 : SPI1_CS1# ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E17, NONE, DEEP, EDGE_SINGLE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F8 : I2S_MCLK2_INOUT ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + /* R6 : I2S1_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), }; -const struct pad_config *variant_base_gpio_table(size_t *num) +const struct pad_config *variant_override_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -17,7 +158,38 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) @@ -25,12 +197,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h index 0075826..fe512d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h @@ -5,6 +5,8 @@ #include <baseboard/gpio.h> -/* Copied from baseboard and may need to change for the new variant. */ +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 #endif diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 75422d8..24842a1 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -1,4 +1,54 @@ chip soc/intel/tigerlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end # I2C #0 0xA0E8 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HD audio 0xA0C8-A0CF end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Gerrit-Change-Number: 42302 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different ...
by Johnny Lin (Code Review) 06 Jul '20

06 Jul '20

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Andrey Petrov, Patrick Georgi, Martin Roth, Jonathan Zhang, Paul Menzel, David Hendricks, Jingle Hsu, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41527 to look at the new patch set (#21). Change subject: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs ...................................................................... mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc M src/mainboard/ocp/deltalake/romstage.c 3 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41527/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/41527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Gerrit-Change-Number: 41527 Gerrit-PatchSet: 21 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/variants/terrador: Add two SPD files
by David Wu (Code Review) 06 Jul '20

06 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41995 ) Change subject: mb/google/volteer/variants/terrador: Add two SPD files ...................................................................... mb/google/volteer/variants/terrador: Add two SPD files Adds SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex, which will be used initially for the "MT53E512M64D4NW-046 WT:E" Micron part as DRAM ID #7. Adds SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex, which will be used initially for the "MT53E1G64D8NW-046 WT:E" Micron part as DRAM ID #8. BUG=b:152936481 b:151978872 TEST=build. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c --- M src/mainboard/google/volteer/variants/terrador/Makefile.inc A src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex A src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex 3 files changed, 67 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/41995/1 diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc index c9a128d..da23cf7 100644 --- a/src/mainboard/google/volteer/variants/terrador/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_432b_1R_32Gb_QDP_4267 # b0111 # MT53E512M64D4NW-046 WT:E +SPD_SOURCES += SPD_LPDDR4X_432b_2R_64Gb_ODP_4267 # b0100 # MT53E1G64D8NW-046 WT:E bootblock-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex new file mode 100644 index 0000000..ef177a3 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B9 08 00 40 00 00 02 01 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex new file mode 100644 index 0000000..2f32372 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 F9 08 00 40 00 00 0A 01 00 00 +49 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/41995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c Gerrit-Change-Number: 41995 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: lp4x: Add new memory parts and generate SPDs
by David Wu (Code Review) 06 Jul '20

06 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43060 ) Change subject: lp4x: Add new memory parts and generate SPDs ...................................................................... lp4x: Add new memory parts and generate SPDs This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST=build. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 --- M src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt M util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43060/1 diff --git a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt index 49fe445..f57b372 100644 --- a/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x/spd_manifest.generated.txt @@ -11,3 +11,5 @@ MT53E512M32D2NP-046 WT:E,spd-1.hex H9HCNNNCPMMLXR-NEE,spd-3.hex K4UBE3D4AA-MGCR,spd-3.hex +MT53E512M64D4NW-046 WT:E,spd-1.hex +MT53E1G64D8NW-046 WT:E,spd-3.hex diff --git a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt index b9dd4b3..109fadb 100644 --- a/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/intel/lp4x/global_lp4x_mem_parts.json.txt @@ -157,6 +157,30 @@ "ranksPerChannel": 2, "speedMbps": 4267 } + }, + { + "name": "MT53E512M64D4NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } + }, + { + "name": "MT53E1G64D8NW-046 WT:E", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 4, + "bitWidthPerChannel": 16, + "ranksPerChannel": 2, + "speedMbps": 4267 + } } ] } -- To view, visit https://review.coreboot.org/c/coreboot/+/43060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Gerrit-Change-Number: 43060 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: cpu/intel/sandybridge: Add `hyper_threading` option
by Angel Pons (Code Review) 06 Jul '20

06 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 ) Change subject: cpu/intel/sandybridge: Add `hyper_threading` option ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b73e32ff5af8ea64a47e8aa706e27648aaf0993 Gerrit-Change-Number: 29669 Gerrit-PatchSet: 15 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 07 Jul 2020 00:09:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: trogdor: Add board variant checks in Kconfig
by Ravi kumar (Code Review) 06 Jul '20

06 Jul '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42730 ) Change subject: trogdor: Add board variant checks in Kconfig ...................................................................... trogdor: Add board variant checks in Kconfig Diffentiate Lazor and trogdor build configuration Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc --- M src/mainboard/google/trogdor/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42730/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index dfd98f0..9f0e037 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -5,7 +5,8 @@ if BOARD_GOOGLE_TROGDOR_COMMON config TROGDOR_REV0 - def_bool y + def_bool y if BOARD_GOOGLE_TROGDOR + def_bool n if BOARD_GOOGLE_LAZOR config BOARD_SPECIFIC_OPTIONS def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/42730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc Gerrit-Change-Number: 42730 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: tests: Add lib/b64_decode-test test case
by Anna Karas (Code Review) 06 Jul '20

06 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42313 ) Change subject: tests: Add lib/b64_decode-test test case ...................................................................... tests: Add lib/b64_decode-test test case Implement unit tests for lib/b64_decode module. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: Id5fe9272e30eaff3d086a95241b3819101089c2b --- M tests/lib/Makefile.inc A tests/lib/b64_decode-test.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42313/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 61f99bf..abb279c 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,10 @@ # two examples - first should be simply string.c, second should use -wrap tests-y += string-test +tests-y += b64_decode-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c + +b64_decode-test-srcs += tests/lib/b64_decode-test.c +b64_decode-test-srcs += src/lib/b64_decode.c diff --git a/tests/lib/b64_decode-test.c b/tests/lib/b64_decode-test.c new file mode 100644 index 0000000..9426236 --- /dev/null +++ b/tests/lib/b64_decode-test.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <b64_decode.h> +#include <tests/test.h> + +struct messages_t { + const char *enc; + const char *dec; +} messages[] = { + {"QQ==", "A"}, + {"QUI=", "AB"}, + {"QUJD", "ABC"}, + {"QUJDRA==", "ABCD"}, + {"SGVsbG8=", "Hello"}, + {"SGVsbG8h", "Hello!"} +}; + +const char *invalid[] = { + "QQ=-=", + "SGVsbG-8=" +}; + +/* Provide necessary definition in order to satisfy dependencies. */ +int do_printk(int msg_level, const char *fmt, ...) { + return 0; +} + +static void test_b64_decode(void **state) +{ + uint8_t *decoded; + size_t res; + + for (int i = 0; i < ARRAY_SIZE(messages); i++) { + decoded = malloc(strlen(messages[i].enc) * sizeof(char)); + + res = b64_decode((uint8_t *)messages[i].enc, strlen(messages[i].enc), decoded); + + assert_int_equal(res, (strlen(messages[i].dec))); + assert_string_equal(decoded, messages[i].dec); + + free(decoded); + } + + for (int i = 0; i < ARRAY_SIZE(invalid); i++) { + decoded = malloc(strlen(invalid[i]) * sizeof(char)); + + res = b64_decode((uint8_t *)invalid[i], strlen(invalid[i]), decoded); + + assert_int_equal(res, 0); + + free(decoded); + } +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_b64_decode), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5fe9272e30eaff3d086a95241b3819101089c2b Gerrit-Change-Number: 42313 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 13

Change in coreboot[master]: tests: Complete lib/string-test test case
by Anna Karas (Code Review) 06 Jul '20

06 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42311 ) Change subject: tests: Complete lib/string-test test case ...................................................................... tests: Complete lib/string-test test case Implement unit tests for remaining string library functions. Fix memory leak in test_strdup(). Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862 --- M tests/lib/string-test.c 1 file changed, 212 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/42311/1 diff --git a/tests/lib/string-test.c b/tests/lib/string-test.c index 08f4177..39e9be9 100644 --- a/tests/lib/string-test.c +++ b/tests/lib/string-test.c @@ -1,50 +1,243 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <string.h> +#include <stdlib.h> +#include <stdint.h> #include <tests/test.h> +#define DST_SIZE 20 + /* * Important note: In every particular test, don't use any string-related * functions other than function under test. We are linking against * src/lib/string.c not the standard library. This is important for proper test - * isolation. One can use __builtin_xxx for many of the most simple str*() - * functions, when non-coreboot one is required. + * isolation. */ -struct strings_t { - char *str; - size_t size; -} strings[] = { - {"coreboot", 8}, - {"is\0very", 2}, /* strlen should be 2 because of the embedded \0 */ - {"nice\n", 5} +struct string_pairs_t { + char *dst; + char *src; +} string_pairs[] = { + {"Hello ", "world!"}, + {"He\0llo ", "world"}, + {"", "world!"}, + {"", ""}, }; -static void test_strlen_strings(void **state) -{ - int i; +const char *strings[] = { + "coreboot", + "is\0very", + "nice\n" +}; - for (i = 0; i < ARRAY_SIZE(strings); i++) - assert_int_equal(strings[i].size, strlen(strings[i].str)); -} +struct str_with_l_val_t { + char *str; + long value; +} str_with_l_val[] = { + {"42", 42}, + {"four42", 0}, + {"42five5", 42}, + {"4\02", 4}, + {"+42", 42}, + {"-42", -42}, + {"\t\n\r\f\v-42", -42}, +}; + +struct str_with_u_val_t { + char *str; + uint32_t value; +} str_with_u_val[] = { + {"42aa", 42}, + {"a", 0}, + {"0", 0}, + {"4a2", 4}, +}; static void test_strdup(void **state) { char str[] = "Hello coreboot\n"; - char *duplicate; - - duplicate = strdup(str); + char *duplicate = strdup(str); /* There is a more suitable Cmocka's function 'assert_string_equal()', but it is using strcmp() internally. */ assert_int_equal(0, memcmp(str, duplicate, __builtin_strlen(str))); + + free(duplicate); +} + +static void test_strconcat(void **state) +{ + int i; + size_t str_len, str2_len, res_len; + char *result; + + for (i = 0; i < ARRAY_SIZE(string_pairs); i++) { + str_len = __builtin_strlen(string_pairs[i].dst); + str2_len = __builtin_strlen(string_pairs[i].src); + + result = strconcat(string_pairs[i].dst, string_pairs[i].src); + res_len = __builtin_strlen(result); + + assert_int_equal(res_len, str_len + str2_len); + assert_int_equal(0, memcmp(string_pairs[i].dst, result, str_len)); + assert_int_equal(0, memcmp(string_pairs[i].src, result + str_len, str2_len)); + + free(result); + } +} + +static void test_strnlen(void **state) +{ + int i, n = 5; + size_t str_len, limited_len; + + for (i = 0; i < ARRAY_SIZE(strings); i++) { + str_len = __builtin_strlen(strings[i]); + limited_len = str_len > n ? n : str_len; + assert_int_equal(limited_len, strnlen(strings[i], n)); + } +} + +static void test_strlen(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(strings); i++) + assert_int_equal(__builtin_strlen(strings[i]), strlen(strings[i])); +} + +static void test_strchr(void **state) +{ + char str[] = "Abracadabra!\n"; + + assert_ptr_equal(str, strchr(str, 'A')); + assert_ptr_equal(str + 3, strchr(str, 'a')); + assert_ptr_not_equal(str + 10, strchr(str, 'a')); + + assert_null(strchr(str, 'z')); +} + + +static void test_strrchr(void **state) +{ + char str[] = "Abracadabra!\n"; + + assert_ptr_equal(str + 9, strrchr(str, 'r')); + assert_ptr_not_equal(str + 2, strrchr(str, 'r')); + + assert_null(strrchr(str, 'z')); +} + + +static void test_strncpy(void **state) +{ + int i, n = 7; + char dst[DST_SIZE]; + char src[] = "Hello coreboot\n"; + size_t src_len = __builtin_strlen(src); + + strncpy(dst, src, n); + + assert_int_equal(0, memcmp(dst, src, n)); + + for (i = src_len; i < n; i++) + assert_true(dst[i] == '\0'); +} + +static void test_strcpy(void **state) +{ + char dst[DST_SIZE]; + char src[] = "Hello coreboot\n"; + + /* Make sure that strcpy() sets '\0' by initializing a whole + dst array to fixed, non-'\0' value */ + memset(dst, 'x', DST_SIZE); + + strcpy(dst, src); + + assert_int_equal(0, memcmp(dst, src, __builtin_strlen(src))); + assert_true(dst[__builtin_strlen(dst)] == '\0'); +} + +static void test_strcmp(void **state) +{ + char str[] = "Banana"; + char str2[] = "Bananas"; + + assert_true(strcmp(str, str2) < 0); + assert_int_equal(0, strcmp(str, str)); + assert_true(strcmp(str2, str) > 0); +} + +static void test_strncmp(void **state) +{ + char str[] = "Banana"; + char str2[] = "Bananas"; + + size_t str2_len = __builtin_strlen(str2); + + assert_true(strncmp(str, str2, str2_len) < 0); + assert_int_equal(0, strncmp(str, str2, str2_len - 1)); +} + +static void test_skip_atoi(void **state) +{ + int i; + char *ptr; + + for (i = 0; i < ARRAY_SIZE(str_with_u_val); i++) { + ptr = str_with_u_val[i].str; + assert_int_equal(str_with_u_val[i].value, skip_atoi(&ptr)); + } +} + +static void test_strspn(void **state) +{ + char str[] = "123404567"; + char str2[] = "01234"; + char str3[] = "1234"; + + assert_int_equal(4, strspn(str, str3)); + assert_int_equal(0, strspn(str2, str3)); +} + +static void test_strcspn(void **state) +{ + char str[] = "12340000"; + char str2[] = "00001234"; + char str3[] = "1234"; + + assert_int_equal(0, strcspn(str, str3)); + assert_int_equal(4, strcspn(str2, str3)); +} + +/* Please bear in mind that `atol()` uses `strspn()` internally, so the result + of `test_atol` is dependent on the result of `test_strspn`. */ +static void test_atol(void **state) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(str_with_l_val); i++) + assert_int_equal(str_with_l_val[i].value, atol(str_with_l_val[i].str)); } int main(void) { const struct CMUnitTest tests[] = { - cmocka_unit_test(test_strlen_strings), cmocka_unit_test(test_strdup), + cmocka_unit_test(test_strconcat), + cmocka_unit_test(test_strnlen), + cmocka_unit_test(test_strlen), + cmocka_unit_test(test_strchr), + cmocka_unit_test(test_strrchr), + cmocka_unit_test(test_strncpy), + cmocka_unit_test(test_strcpy), + cmocka_unit_test(test_strcmp), + cmocka_unit_test(test_strncmp), + cmocka_unit_test(test_skip_atoi), + cmocka_unit_test(test_strspn), + cmocka_unit_test(test_strcspn), + cmocka_unit_test(test_atol), }; return cmocka_run_group_tests(tests, NULL, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/42311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ac6a6b2413d9077dc9ea81f638a2b0acd5c8862 Gerrit-Change-Number: 42311 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/sata.c: Handle ABAR as a resource
by Angel Pons (Code Review) 06 Jul '20

06 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42643 ) Change subject: sb/intel/i82801jx/sata.c: Handle ABAR as a resource ...................................................................... sb/intel/i82801jx/sata.c: Handle ABAR as a resource Instead of directly reading ABAR without any checking, do like i82801ix and treat it as a resource. This prevents problems if ABAR is not set. Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/sata.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/42643/1 diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 73a7d82..947842a 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -20,9 +20,14 @@ { int i; u32 reg32; + struct resource *res; /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (!res) + return; + + u8 *abar = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Set AHCI access mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/42643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f888b748204860b0a7e1bf5611f5f3e487e8081 Gerrit-Change-Number: 42643 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020