coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3167 discussions

Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Arthur Heymans (Code Review) 06 Jul '20

06 Jul '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 27 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 19:46:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Drop unused `#include <reg_script.h>`
by Angel Pons (Code Review) 06 Jul '20

06 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43138 ) Change subject: soc/intel: Drop unused `#include <reg_script.h>` ...................................................................... soc/intel: Drop unused `#include <reg_script.h>` In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig. Change-Id: I617f332b80c534997e06a91247d1be90a85573be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/sd.c M src/soc/intel/braswell/sd.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/finalize.c 13 files changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/43138/1 diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 6e4179c..57cd8f4 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h> #include <soc/iosf.h> #include <soc/nvs.h> diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index edb5e77..34dd835 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h> #include <soc/iosf.h> #include <soc/nvs.h> diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 8128458..cb1d3e5 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -7,7 +7,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <reg_script.h> #include <string.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 49e9d7f..315c67a 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 47a7b71..50af9ee 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> -#include <reg_script.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 9764a3e..b1eda9b 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -12,7 +12,6 @@ #include <device/device.h> #include <device/pci.h> #include <intelblocks/cpulib.h> -#include <reg_script.h> #include <soc/msr.h> #include <soc/cpu.h> diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 2b98d9e..1497c8d 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> -#include <reg_script.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index fdeaaad..53e3cba 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index a1954fd..bf82067 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -10,7 +10,6 @@ #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> -#include <reg_script.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index d16080f..08a6bab 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -11,7 +11,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index dbb451c..98f12a5 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -15,7 +15,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/me.h> #include <soc/p2sb.h> diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 8cc8303..513da5a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -16,7 +16,6 @@ #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> -#include <reg_script.h> #include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index d0dc30e..534abd9 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -17,7 +17,6 @@ #include <intelblocks/pcr.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> -#include <reg_script.h> #include <spi-generic.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I617f332b80c534997e06a91247d1be90a85573be Gerrit-Change-Number: 43138 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/intel/mipi_camera: Add guard variables to protect shared reso...
by Sugnan Prabhu S (Code Review) 06 Jul '20

06 Jul '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43003 ) Change subject: drivers/intel/mipi_camera: Add guard variables to protect shared resource ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/43003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c Gerrit-Change-Number: 43003 Gerrit-PatchSet: 5 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 06 Jul 2020 17:30:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: pgtblgen: Update comment to match what the code does
by Patrick Rudolph (Code Review) 06 Jul '20

06 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42981 ) Change subject: pgtblgen: Update comment to match what the code does ...................................................................... pgtblgen: Update comment to match what the code does Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M util/pgtblgen/pgtblgen.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/42981/1 diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 27114ed..640d0ba 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -23,7 +23,7 @@ * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2", * Document 24593-Rev. 3.31-July 2019 Chapter 5.3.4 * - * Page table attributes: WB, User+Supervisor, Present, Writeable + * Page table attributes: WB, User+Supervisor, Present, Writeable, Accessed, Dirty */ #define _PRES (1ULL << 0) #define _RW (1ULL << 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/42981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib87c804b139a96a4173a6f392f0f99a77d32fc01 Gerrit-Change-Number: 42981 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [TESTONLY] devicetree: Remove weak declarations for ops
by Kyösti Mälkki (Code Review) 06 Jul '20

06 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35086 ) Change subject: [TESTONLY] devicetree: Remove weak declarations for ops ...................................................................... [TESTONLY] devicetree: Remove weak declarations for ops Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/sconfig/main.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35086/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5e3a1d4..586de06 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -936,9 +936,14 @@ chip = tmp; while (chip) { - fprintf(fil, - "__attribute__((weak)) struct chip_operations %s_ops = {};\n", - chip->name_underscore); + if (strstr(chip->name_underscore, "cpu_") == chip->name_underscore) { + fprintf(fil, + "__attribute__((weak)) struct chip_operations %s_ops = {};\n", + chip->name_underscore); + } else { + fprintf(fil, "extern struct chip_operations %s_ops;\n", + chip->name_underscore); + } chip = chip->next; } fprintf(fil, "#endif\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Gerrit-Change-Number: 35086 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

9 25

Change in coreboot[master]: drivers/intel/mipi_camera: Handle acpi_name and common code
by Balaji Manigandan (Code Review) 06 Jul '20

06 Jul '20

Balaji Manigandan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41607 ) Change subject: drivers/intel/mipi_camera: Handle acpi_name and common code ...................................................................... Patch Set 32: @Tim, the +2 is lost due to rebase, could you please revisit this patch, this will allow the other dependent patches to be merged -- To view, visit https://review.coreboot.org/c/coreboot/+/41607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15979f345fb823df2560db269e902a1ea650b69e Gerrit-Change-Number: 41607 Gerrit-PatchSet: 32 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Daniel Kang <daniel.h.kang(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Kiran2 Kumar <kiran2.kumar(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Mon, 06 Jul 2020 15:59:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/amd/mandolin: Drop SPD eeproms in devicetree
by Kyösti Mälkki (Code Review) 06 Jul '20

06 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43046 ) Change subject: mb/amd/mandolin: Drop SPD eeproms in devicetree ...................................................................... mb/amd/mandolin: Drop SPD eeproms in devicetree Even with previous platforms, these entries were not utilised for raminit. Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/43046/1 diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 495961f..97022c5 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -62,12 +62,7 @@ device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 50 on end - device i2c 51 on end - end - end # SM + device pci 14.0 on end # SM device pci 14.3 on # - D14F3 bridge chip superio/smsc/sio1036 # optional debug card end -- To view, visit https://review.coreboot.org/c/coreboot/+/43046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f Gerrit-Change-Number: 43046 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: security/intel/txt: Add Intel TXT support
by Arthur Heymans (Code Review) 06 Jul '20

06 Jul '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37016 ) Change subject: security/intel/txt: Add Intel TXT support ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/37016/6/src/security/intel/txt/com… File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/37016/6/src/security/intel/txt/com… PS6, Line 31: int boot_cpu(void); this is defined in <smp/node.h> https://review.coreboot.org/c/coreboot/+/37016/6/src/security/intel/txt/com… PS6, Line 450: msr = rdmsr(LAPIC_BASE_MSR); unused -- To view, visit https://review.coreboot.org/c/coreboot/+/37016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284 Gerrit-Change-Number: 37016 Gerrit-PatchSet: 6 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 15:22:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/intel/txt: Add Intel TXT support
by Philipp Deppenwiese (Code Review) 06 Jul '20

06 Jul '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37016 ) Change subject: security/intel/txt: Add Intel TXT support ...................................................................... Patch Set 5: (9 comments) https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/com… File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/com… PS1, Line 41: if (acm_error & ACMERROR_TXT_VALID) { : const uint8_t type = (acm_error & ACMERROR_TXT_TYPE_CODE) : >> ACMERROR_TXT_TYPE_SHIFT; : : switch (type) { : case ACMERROR_TXT_AC_MODULE_TYPE_BIOS: : printk(BIOS_ERR, "BIOSACM"); : break; : case ACMERROR_TXT_AC_MODULE_TYPE_SINIT: : printk(BIOS_ERR, "SINIT"); : break; : default: : printk(BIOS_ERR, "ACM"); : break; : } : printk(BIOS_ERR, ": Error code valid\n"); : : if (acm_error & ACMERROR_TXT_EXTERNAL) : printk(BIOS_ERR, " Caused by: External\n"); : else : printk(BIOS_ERR, " Caused by: Processor\n"); : : const uint32_t class = (acm_error & ACMERROR_TXT_CLASS_CODE) : >> ACMERROR_TXT_CLASS_SHIFT; : const uint32_t major = (acm_error & ACMERROR_TXT_MAJOR_CODE) : >> ACMERROR_TXT_MAJOR_SHIFT; : const uint32_t minor = (acm_error & ACMERROR_TXT_MINOR_CODE) : >> ACMERROR_TXT_MINOR_SHIFT; : const uint32_t progress = (acm_error & ACMERROR_TXT_PROGRESS_CODE) : >> ACMERROR_TXT_PROGRESS_SHIFT; : : if (!minor) { : if (class == 0 && major == 0 && progress > 0) { : printk(BIOS_ERR, " Execution successful\n"); : printk(BIOS_ERR, " Progress code 0x%x\n", : progress); : } else { : printk(BIOS_ERR, " Error Class: %x\n", class); : printk(BIOS_ERR, " Error: %x.%x\n", major, progress); : } : } else { : printk(BIOS_ERR, " ACM didn't start\n"); : printk(BIOS_ERR, " Error Type: 0x%x\n", acm_error & 0xffffff); : return -1; : } : : return (acm_error & ACMERROR_TXT_EXTERNAL) && : class == 0 && : major == 0 && : progress > 0; : } : : return -1; > reduce indentation level by reversing the if condition and returning -1 Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/com… PS1, Line 241: ((uintptr_t)acm_data) % 4096 != 0 > use the IS_ALIGNED macro. Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/com… PS1, Line 456: !(msr.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) > !boot_cpu() Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/com… PS1, Line 502: PARALLEL_MP_AP_WORK > This depends on PARALLEL_MP? Ack https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… File src/security/intel/txt/getsec_enteraccs.S: https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… PS1, Line 21: CONFIG_CPU_ADDR_BITS > You can get this at runtime via cpuid 0x80000008. Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… PS1, Line 45: (MTRR_CAP_MSR) > parentheses not required? Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… PS1, Line 61: (0x200 + 2 * (\x) + 1) > MTRR_PHYS_MASK(0) + 2 * (\x). Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… PS1, Line 62: (0x200 + 2 * (\x)) > MTRR_PHYS_BASE(0) + 2 * (\x). Done https://review.coreboot.org/c/coreboot/+/37016/1/src/security/intel/txt/get… PS1, Line 319: %ebp,%esp > space after ',' Done -- To view, visit https://review.coreboot.org/c/coreboot/+/37016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284 Gerrit-Change-Number: 37016 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 06 Jul 2020 15:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/intel/txt: Add Intel TXT support
by Philipp Deppenwiese (Code Review) 06 Jul '20

06 Jul '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37016 to look at the new patch set (#5). Change subject: security/intel/txt: Add Intel TXT support ...................................................................... security/intel/txt: Add Intel TXT support * Add TXT ramstage driver ** Show startup errors ** Check for TXT reset ** Check for Secrets-in-memory ** Add assembly for GETSEC instruction ** Check platform state if GETSEC instruction is supported ** Configure TXT memory regions ** Lock TXT ** Protect TSEG using DMA protected regions ** Place SINIT ACM ** Print information about ACMs * Extend security_clear_dram_request() ** To clear all DRAM if secrets are in memory Tested on OCP Wedge100s and Facebook Watson * Able to enter a Measure Launch Environment using SINIT ACM and TBOOT * Secrets in Memory bit is set on ungraceful shutdown * Memory is cleared after ungraceful shutdown Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/intel/txt/Kconfig M src/security/intel/txt/Makefile.inc A src/security/intel/txt/common.c A src/security/intel/txt/getsec.c A src/security/intel/txt/getsec_enteraccs.S A src/security/intel/txt/logging.c A src/security/intel/txt/ramstage.c A src/security/intel/txt/txt.h A src/security/intel/txt/txt_getsec.h A src/security/intel/txt/txt_register.h M src/security/memory/memory.c 11 files changed, 1,967 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37016/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/37016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf4be7f016cc12d3971e1e1fe171e6665e44c284 Gerrit-Change-Number: 37016 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020