coreboot-gerrit July 2020

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Change in coreboot[master]: mb/google/volteer: Rename remaining pmc_mux/con to conn
by Patrick Georgi (Code Review) 06 Jul '20

06 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43141 ) Change subject: mb/google/volteer: Rename remaining pmc_mux/con to conn ...................................................................... mb/google/volteer: Rename remaining pmc_mux/con to conn CB:43090 renamed con to conn to avoid issues when building on Windows. CB:42905 introduced more uses of the old name. Adapt the latter to comply with the former. Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43141/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 577f7c8..404b257 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -163,7 +163,7 @@ probe DB_USB USB3_NO_A end end - chip drivers/intel/pmc_mux/con + chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU & HSL follow CC diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 9ee7e6a..2219de0 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -111,14 +111,14 @@ # PMC.MUX device in the ACPI hierarchy. chip drivers/intel/pmc_mux device generic 0 on - chip drivers/intel/pmc_mux/con + chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 0 on end end - chip drivers/intel/pmc_mux/con + chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC -- To view, visit https://review.coreboot.org/c/coreboot/+/43141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Gerrit-Change-Number: 43141 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: prog_loaders: Fix ramstage loading on x86
by Nico Huber (Code Review) 06 Jul '20

06 Jul '20

Hello Kyösti Mälkki, Werner Zeh, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43142 to review the following change. Change subject: prog_loaders: Fix ramstage loading on x86 ...................................................................... prog_loaders: Fix ramstage loading on x86 A regression sneaked in with 18a8ba41cc (arch/x86: Remove RELOCATABLE_ RAMSTAGE). We want to call load_relocatable_ramstage() on x86, and cbfs_prog_stage_load() on other architectures. But with the current code the latter is also called on x86 if the former succeeded. Fix that and also balance the if structure to make it more obvious. Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/lib/prog_loaders.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43142/1 diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 419f4cd..93efc0a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -129,10 +129,13 @@ timestamp_add_now(TS_START_COPYRAM); - if (ENV_X86 && load_relocatable_ramstage(&ramstage)) - goto fail; - else if (cbfs_prog_stage_load(&ramstage)) - goto fail; + if (ENV_X86) { + if (load_relocatable_ramstage(&ramstage)) + goto fail; + } else { + if (cbfs_prog_stage_load(&ramstage)) + goto fail; + } stage_cache_add(STAGE_RAMSTAGE, &ramstage); -- To view, visit https://review.coreboot.org/c/coreboot/+/43142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b1db5aac772b9b3a388a1a8ae490fa627334320 Gerrit-Change-Number: 43142 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: post_code: add defines for missing postcode values
by Christian Walter (Code Review) 06 Jul '20

06 Jul '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42278 ) Change subject: post_code: add defines for missing postcode values ...................................................................... Patch Set 10: You need to cherry-pick CB:43141 in order to make this work - Or wait until CB:43141 has been merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/42278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc Gerrit-Change-Number: 42278 Gerrit-PatchSet: 10 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 09:30:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 06 Jul '20

06 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 473: Align with previous line? -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 14 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 09:19:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: cbgfx: Replace bilinear resampling with Lanczos
by Yu-Ping Wu (Code Review) 06 Jul '20

06 Jul '20

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42792 ) Change subject: libpayload: cbgfx: Replace bilinear resampling with Lanczos ...................................................................... Patch Set 14: (3 comments) https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… File payloads/libpayload/drivers/video/graphics.c: https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 517: from -2 to 4 Where are the numbers -2 and 4 from? Do you mean from -LNCZ_A+1 to LNCZ_A https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 628: weigths weights https://review.coreboot.org/c/coreboot/+/42792/14/payloads/libpayload/drive… PS14, Line 651: dim->height < sy - S0 Should it be dim_org->height <= sy - S0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a Gerrit-Change-Number: 42792 Gerrit-PatchSet: 14 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 06 Jul 2020 09:18:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate
by Keith Hui (Code Review) 05 Jul '20

05 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41225 ) Change subject: mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate ...................................................................... mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicate PS/2 keyboard and mouse devices are declared twice in the DSDT, once in mainboard and once in southbridge. It would appear in Windows Device Manager as two PS/2 keyboards and two PS/2 mouses, all with resource conflicts. This change drops the declaration from mainboard. The issue was discovered when this setup was copied for p8z77-m and then boot tested there. Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8z77-m_pro/dsdt.asl 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41225/1 diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl index 21b3954..e5446a9 100644 --- a/src/mainboard/asus/p8z77-m_pro/dsdt.asl +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -12,7 +12,6 @@ ) { #include "acpi/platform.asl" - #include "acpi/superio.asl" #include <cpu/intel/common/acpi/cpu.asl> #include <southbridge/intel/common/acpi/platform.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Gerrit-Change-Number: 41225 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO
by Paul Menzel (Code Review) 05 Jul '20

05 Jul '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41998 ) Change subject: drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO ...................................................................... drivers/ipmi: Increase BMC waiting message level from DEBUG to INFO As the booting the system can be delayed for a noticeable amount of time, often 60 seconds is the default, this is not a debug message. Chose log level BIOS_INFO. Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/41998/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index a5a963e..edc8c18 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -88,7 +88,7 @@ if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); - printk(BIOS_DEBUG, "IPMI: Waiting for BMC...\n"); + printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); while (!stopwatch_expired(&sw)) { if (inb(dev->path.pnp.port) != 0xff) -- To view, visit https://review.coreboot.org/c/coreboot/+/41998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f Gerrit-Change-Number: 41998 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: Add PMCR register to ACPI code
by Keith Hui (Code Review) 05 Jul '20

05 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41092 ) Change subject: nb/intel/i440bx: Add PMCR register to ACPI code ...................................................................... nb/intel/i440bx: Add PMCR register to ACPI code p3b-f suspend code is going to use it. Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41092/1 diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index fa5948f..476be30 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -10,6 +10,8 @@ { Offset (0x67), // DRB7 DRB7, 8, + Offset (0x7A), // PMCR + PMCR, 8 } Method(TOM1, 0) { /* Multiply by 8MB to get TOM */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc17257e9f690115ec35d94c7c36df39341f0df Gerrit-Change-Number: 41092 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/i440bx: DSDT upgrade
by Keith Hui (Code Review) 05 Jul '20

05 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41049 ) Change subject: nb/intel/i440bx: DSDT upgrade ...................................................................... nb/intel/i440bx: DSDT upgrade - Separate northbridge DSDT memory device into its own ACPI device, in its own file, to be placed in the \_SB scope. The existing file goes to \_SB.PCI0. - Add PMCR register. It'll come in handy for S3 support. - Add a memory device in ACPI to match ASUS P3B-F vendor DSDT. Memory ranges between TOM and 4GB was declared available for MMIO, now it is between TOM and (4GB - CONFIG_ROM_SIZE). Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/northbridge/intel/i440bx/acpi/i440bx.asl M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl 2 files changed, 66 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/41049/1 diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl new file mode 100644 index 0000000..ae82625 --- /dev/null +++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* i440bx Northbridge resources that sits on \_SB */ + +Device (MEM1) +{ + Name (_HID, EisaId ("PNP0C01") /* System Board */) // _HID: Hardware ID + Method (_CRS, 0) // _CRS: Current Resource Settings + { + Name (BUF1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x000A0000, // Address Length + ) + Memory32Fixed (ReadOnly, + 0x000F0000, // Address Base + 0x00010000, // Address Length + ) + /* + * Main memory. Length of this block will be adjusted to TOM1, + * TOM1-4GB is declared in sb_pci0_crs.asl for MMIO. + */ + Memory32Fixed (ReadWrite, + 0x00100000, // Address Base + 0x00000000, // Address Length + _Y00) + /* Reserved for firmware flash */ + Memory32Fixed (ReadOnly, + 0xFFFC0000, // Address Base + CONFIG_ROM_SIZE, // Address Length + _Y01) + }) + CreateDWordField (BUF1, _Y00._LEN, EMLN) // _LEN: Length + CreateDWordField (BUF1, _Y01._BAS, FLSB) // _BAS: Base + + /* + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + + /* Top of 4GB */ + ShiftLeft(0x10000000, 4, Local0) + FLSB = Local0 - CONFIG_ROM_SIZE; + EMLN = \_SB.PCI0.NB.TOM1 - 0x100000; + Return (BUF1) /* \_SB_.MEM1._CRS.BUF1 */ + } +} diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl index 856b3e8..476be30 100644 --- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl +++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl @@ -1,22 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ -/* i440bx Northbridge */ +/* i440bx Northbridge resources that sits on \_SB.PCI0 */ Device (NB) { Name(_ADR, 0x00000000) OperationRegion(PCIC, PCI_Config, 0x00, 0x100) -} - -Field (NB.PCIC, AnyAcc, NoLock, Preserve) -{ - Offset (0x67), // DRB7 - DRB7, 8, -} - -Method(TOM1, 0) { - /* Multiply by 8MB to get TOM */ - Return(ShiftLeft(DRB7, 23)) + Field (PCIC, ByteAcc, NoLock, Preserve) + { + Offset (0x67), // DRB7 + DRB7, 8, + Offset (0x7A), // PMCR + PMCR, 8 + } + Method(TOM1, 0) { + /* Multiply by 8MB to get TOM */ + Return(ShiftLeft(DRB7, 23)) + } } Method(_CRS, 0) { @@ -61,10 +61,10 @@ * 32bit (0x00000000 - TOM1) will wrap and give the same * result as 64bit (0x100000000 - TOM1). */ - Store(TOM1, MM1B) + MM1B = \_SB.PCI0.NB.TOM1 ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + Local0 -= CONFIG_ROM_SIZE + MM1L = Local0 - MM1B Return(TMP) } -- To view, visit https://review.coreboot.org/c/coreboot/+/41049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c74ef30a9bb48e02154f963b1ca3a4f5f3004df Gerrit-Change-Number: 41049 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS
by Keith Hui (Code Review) 05 Jul '20

05 Jul '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41457 ) Change subject: sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS ...................................................................... sb/intel/i82371eb: Don't fill \_SB.PCI0.MBRS Only two mainboard groups use this southbridge: emulation/qemu-i440fx: Nothing creates or consumes this ACPI path. asus/p2b: It only fills the (mostly static) PIIX4E PM/SMBus I/O resources, which are being declared in DSDT. It is not doing anything useful and causes ACPI errors in Linux kernel[1][2], so it has to stop. [1] https://review.coreboot.org/c/coreboot/+/38601 [2] https://review.coreboot.org/c/coreboot/+/38304 Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/isa.c 1 file changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/41457/1 diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index efbfb22..83e2789 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -104,21 +104,13 @@ #endif } -#if CONFIG(HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(const struct device *device) -{ - acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); - generate_cpu_entries(device); -} -#endif - static const struct device_operations isa_ops = { .read_resources = sb_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, - .acpi_fill_ssdt = southbridge_acpi_fill_ssdt_generator, + .acpi_fill_ssdt = generate_cpu_entries, #endif .init = isa_init, .scan_bus = scan_static_bus, -- To view, visit https://review.coreboot.org/c/coreboot/+/41457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I770047610e02c08191613b57c989b3bc1d464684 Gerrit-Change-Number: 41457 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020