coreboot-gerrit July 2020

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Change in coreboot[master]: mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_init
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43118 ) Change subject: mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_init ...................................................................... mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_init This change drops the check for ENV_RAMSTAGE in mainboard_ec_init() since it is included only in ramstage. Also, the content of ramstage_ec_init() is moved into mainboard_ec_init(). Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/ec.c 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/43118/1 diff --git a/src/mainboard/google/zork/ec.c b/src/mainboard/google/zork/ec.c index 4c4329d..d770d27 100644 --- a/src/mainboard/google/zork/ec.c +++ b/src/mainboard/google/zork/ec.c @@ -3,10 +3,9 @@ #include <acpi/acpi.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <soc/southbridge.h> #include <variant/ec.h> -static void ramstage_ec_init(void) +void mainboard_ec_init(void) { const struct google_chromeec_event_info info = { .log_events = MAINBOARD_EC_LOG_EVENTS, @@ -19,9 +18,3 @@ google_chromeec_events_init(&info, acpi_is_wakeup_s3()); } - -void mainboard_ec_init(void) -{ - if (ENV_RAMSTAGE) - ramstage_ec_init(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Gerrit-Change-Number: 43118 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Drop mainboard_ec_init() from romstage
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43117 ) Change subject: mb/google/zork: Drop mainboard_ec_init() from romstage ...................................................................... mb/google/zork: Drop mainboard_ec_init() from romstage mainboard_ec_init() does nothing in any stage other than ramstage. So, this change drops the call to mainboard_ec_init() from romstage.c. Additionally, it also drops ec.c from romstage and verstage. Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/Makefile.inc M src/mainboard/google/zork/romstage.c 2 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43117/1 diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index ac828e2..88aef86 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -3,7 +3,6 @@ bootblock-y += bootblock.c romstage-y += chromeos.c -romstage-y += ec.c romstage-y += sku_id.c ramstage-y += chromeos.c @@ -14,7 +13,6 @@ verstage-y += verstage.c else verstage-y += chromeos.c -verstage-y += ec.c endif smm-y += smihandler.c diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c index 3da8a53..bd4c96e 100644 --- a/src/mainboard/google/zork/romstage.c +++ b/src/mainboard/google/zork/romstage.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <ec/ec.h> -#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <soc/romstage.h> -#include <variant/ec.h> #include <console/console.h> void mainboard_romstage_entry_s3(int s3_resume) @@ -16,6 +13,4 @@ gpios = variant_romstage_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); variant_pcie_power_reset_configure(); - - mainboard_ec_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Gerrit-Change-Number: 43117 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Drop unused function variant_romstage_entry()
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43116 ) Change subject: mb/google/zork: Drop unused function variant_romstage_entry() ...................................................................... mb/google/zork: Drop unused function variant_romstage_entry() This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/romstage.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43116/1 diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c index 9d7b850..3da8a53 100644 --- a/src/mainboard/google/zork/romstage.c +++ b/src/mainboard/google/zork/romstage.c @@ -8,11 +8,6 @@ #include <variant/ec.h> #include <console/console.h> -void __weak variant_romstage_entry(void) -{ - /* By default, don't do anything */ -} - void mainboard_romstage_entry_s3(int s3_resume) { size_t num_gpios; @@ -23,6 +18,4 @@ variant_pcie_power_reset_configure(); mainboard_ec_init(); - - variant_romstage_entry(); } diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index c3986bc..ac29b92 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -32,7 +32,6 @@ */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); -void variant_romstage_entry(void); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); /* Update audio configuration in devicetree during ramstage. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Gerrit-Change-Number: 43116 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Drop codec.asl
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43043 ) Change subject: ec/google/chromeec: Drop codec.asl ...................................................................... ec/google/chromeec: Drop codec.asl This change drops codec.asl file from Chrome EC since it is now unused. Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/ec/google/chromeec/acpi/codec.asl 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/43043/1 diff --git a/src/ec/google/chromeec/acpi/codec.asl b/src/ec/google/chromeec/acpi/codec.asl deleted file mode 100644 index 14d8d0c..0000000 --- a/src/ec/google/chromeec/acpi/codec.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (ECOD) -{ - Name (_HID, "GOOG0013") - Name (_UID, 1) - Name (_DDN, "CROS EC CODEC") -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c2f3e53b14aaf76b9c6d038a732e79a4d7bb2f1 Gerrit-Change-Number: 43043 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Use SSDT generator for Chrome EC audio codec device
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43042 ) Change subject: mb/google/zork: Use SSDT generator for Chrome EC audio codec device ...................................................................... mb/google/zork: Use SSDT generator for Chrome EC audio codec device This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/dsdt.asl M src/mainboard/google/zork/variants/baseboard/devicetree.cb D src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl D src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl 10 files changed, 5 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43042/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 3e7756b..e24f78a 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -19,6 +19,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_AUDIO_CODEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index f561de3..8b42102 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -60,8 +60,6 @@ #include <ec/google/chromeec/acpi/superio.asl> /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> - /* ACPI code for EC I2C Audio Tunnel */ - #include <variant/acpi/audio.asl> } } /* End of ASL file */ diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 9324749..79a4c89 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -171,6 +171,10 @@ register "remote_bus" = "9" device generic 1.0 on end end + chip ec/google/chromeec/audio_codec + register "uid" = "1" + device generic 0 on end + end end end end diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl deleted file mode 100644 index b892570..0000000 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -Scope (EC0.CREC) { - #include <ec/google/chromeec/acpi/codec.asl> -} diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/43042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Gerrit-Change-Number: 43042 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Add driver for audio codec device
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43041 ) Change subject: ec/google/chromeec: Add driver for audio codec device ...................................................................... ec/google/chromeec: Add driver for audio codec device This change adds driver for audio codec device (HID `GOOG0013`) living behind Chrome EC. This driver generates the required ACPI node for the codec device. In a later change, GOOG0013 device will be dropped the .asl file. Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/audio_codec/Kconfig A src/ec/google/chromeec/audio_codec/Makefile.inc A src/ec/google/chromeec/audio_codec/audio_codec.c A src/ec/google/chromeec/audio_codec/chip.h 5 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43041/1 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index b11f5c8..1f7e03d 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) +subdirs-y += audio_codec subdirs-y += i2c_tunnel bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/audio_codec/Kconfig b/src/ec/google/chromeec/audio_codec/Kconfig new file mode 100644 index 0000000..148a7a8 --- /dev/null +++ b/src/ec/google/chromeec/audio_codec/Kconfig @@ -0,0 +1,10 @@ +if EC_GOOGLE_CHROMEEC + +config EC_GOOGLE_CHROMEEC_AUDIO_CODEC + bool + depends on HAVE_ACPI_TABLES + help + This enables the Cros EC audio codec driver that is required to fill the + SSDT nodes for the codec device used by the mainboard. + +endif diff --git a/src/ec/google/chromeec/audio_codec/Makefile.inc b/src/ec/google/chromeec/audio_codec/Makefile.inc new file mode 100644 index 0000000..8726b92 --- /dev/null +++ b/src/ec/google/chromeec/audio_codec/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_AUDIO_CODEC) += audio_codec.c diff --git a/src/ec/google/chromeec/audio_codec/audio_codec.c b/src/ec/google/chromeec/audio_codec/audio_codec.c new file mode 100644 index 0000000..612b1f6 --- /dev/null +++ b/src/ec/google/chromeec/audio_codec/audio_codec.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include "chip.h" + +#define CROS_EC_AUDIO_CODEC_HID "GOOG0013" +#define CROS_EC_AUDIO_CODEC_DDN "Cros EC audio codec" + +static void crosec_audio_codec_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info; + + if (!dev->enabled || !scope || !cfg) + return; + + acpigen_write_scope(scope); + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CROS_EC_AUDIO_CODEC_HID); + acpigen_write_name_integer("_UID", cfg->uid); + acpigen_write_name_string("_DDN", CROS_EC_AUDIO_CODEC_DDN); + acpigen_write_STA(acpi_device_status(dev)); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), CROS_EC_AUDIO_CODEC_DDN, + dev_path(dev)); +} + +static const char *crosec_audio_codec_acpi_name(const struct device *dev) +{ + struct ec_google_chromeec_audio_codec_config *cfg = dev->chip_info; + static char name[5]; + + if (cfg->name) + return cfg->name; + + snprintf(name, sizeof(name), "ECA%X", dev->path.generic.id); + return name; +} + +static struct device_operations crosec_audio_codec_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = crosec_audio_codec_acpi_name, + .acpi_fill_ssdt = crosec_audio_codec_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void crosec_audio_codec_enable(struct device *dev) +{ + dev->ops = &crosec_audio_codec_ops; +} + +struct chip_operations ec_google_chromeec_audio_codec_ops = { + CHIP_NAME("CrosEC Audio Codec Device") + .enable_dev = crosec_audio_codec_enable +}; diff --git a/src/ec/google/chromeec/audio_codec/chip.h b/src/ec/google/chromeec/audio_codec/chip.h new file mode 100644 index 0000000..30a83ef --- /dev/null +++ b/src/ec/google/chromeec/audio_codec/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __EC_GOOGLE_CHROMEEC_AUDIO_CODEC__ +#define __EC_GOOGLE_CHROMEEC_AUDIO_CODEC__ + +struct ec_google_chromeec_audio_codec_config { + /* ACPI device name */ + const char *name; + /* ACPI _UID */ + unsigned int uid; +}; + +#endif /* __EC_GOOGLE_CHROMEEC_AUDIO_CODEC__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2759eac60265ef81df70af1d4f1f72bd9d987e8 Gerrit-Change-Number: 43041 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/Kconfig
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43040 ) Change subject: ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/Kconfig ...................................................................... ec/google/chromeec: Move if EC_GOOGLE_CHROMEEC to i2c_tunnel/Kconfig This change moves `if EC_GOOGLE_CHROMEEC` from chromeec/Kconfig to chromeec/i2c_tunnel/Kconfig. This is done to make it clear that the Kconfig file in i2c_tunnel is sourced unconditionally, but the configs in i2c_tunnel/Kconfig are conditionally defined based on the evaluation of if condition. This change addressed the feedback received on https://review.coreboot.org/c/coreboot/+/40515/11/src/ec/google/chromeec/Kc…. Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/i2c_tunnel/Kconfig 2 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/43040/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 4615878..638c011 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -197,8 +197,4 @@ Enable support for Chrome OS mode switches provided by the Chrome OS EC. -if EC_GOOGLE_CHROMEEC - source "src/ec/google/chromeec/*/Kconfig" - -endif diff --git a/src/ec/google/chromeec/i2c_tunnel/Kconfig b/src/ec/google/chromeec/i2c_tunnel/Kconfig index 20169fd..e517a17 100644 --- a/src/ec/google/chromeec/i2c_tunnel/Kconfig +++ b/src/ec/google/chromeec/i2c_tunnel/Kconfig @@ -1,6 +1,11 @@ +if EC_GOOGLE_CHROMEEC + config EC_GOOGLE_CHROMEEC_I2C_TUNNEL bool depends on HAVE_ACPI_TABLES help This enables the Cros EC I2C tunnel driver that is required to fill the SSDT nodes for the I2C tunnel used by the mainboard. + +endif + -- To view, visit https://review.coreboot.org/c/coreboot/+/43040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66cd91d6b1813ff6d0fb7be719e2da65ac6ac23b Gerrit-Change-Number: 43040 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee: Drop macro H1_PCH_INT
by Furquan Shaikh (Code Review) 05 Jul '20

05 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43015 ) Change subject: mb/google/kahlee: Drop macro H1_PCH_INT ...................................................................... mb/google/kahlee: Drop macro H1_PCH_INT This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43015/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h index 6c1c941..8851072 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h @@ -11,9 +11,6 @@ # define MEM_CONFIG2 GPIO_131 # define MEM_CONFIG3 GPIO_132 -/* CR50 interrupt pin */ -#define H1_PCH_INT GPIO_9 - /* SPI Write protect */ #define CROS_WP_GPIO GPIO_122 #define GPIO_EC_IN_RW GPIO_15 diff --git a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c index 63625c4..1c87952 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/kahlee/variants/baseboard/tpm_tis.c @@ -6,5 +6,5 @@ int tis_plat_irq_status(void) { - return gpio_interrupt_status(H1_PCH_INT); + return gpio_interrupt_status(GPIO_9); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Gerrit-Change-Number: 43015 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 05 Jul '20

05 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 60: (2 comments) https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl: https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… PS60, Line 18: Scope (\_SB) { : Device (PCI0) { > You are always complaining about this - but this throws an error when comping the asl code ;) Uh, weird. It works for me on other platforms https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… PS60, Line 27: .rcomp_resistor = {121, 81, 100}, > These values often go through me and come from Intel doc #573387. […] I usually dig the resistor values from schematics for ULT and Halo, and then ask Nico if they are correct. They usually are the same for SKL and CFL parts with the same topology (CFL is just SKL refresh refresh). On socketed platforms, however, the resistors are under the CPU [1]. One day on IRC, Nico and I were curious about the value of those resistors, so I took a dead i5-6400 and desoldered the resistors to measure the values. And the resistor values matched those for Halo: 121, 75, 100. [1]: https://i.imgur.com/YMdxMWf.jpg (The three light blue components on the top left corner of the center are those RCOMP resistors) -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 60 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Jul 2020 17:33:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Nico Huber (Code Review) 05 Jul '20

05 Jul '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 60: (2 comments) https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/memory.c: https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… PS60, Line 27: .rcomp_resistor = {121, 81, 100}, > Where do you got those values from? - Also why CFL-U? These values often go through me and come from Intel doc #573387. The Rcomp values are all specific to the chip generation, class (Y/U/H/S), and DRAM topology (e.g. DIMM/SO-DIMM/soldered down this/that way). For the socketed -S CPUs, it's not board specific at all, as the resistors are on the bottom of the CPU package. IIRC, we confirmed the 121, 75, 100 by measuring once (and it's what the document says for CFL-S). https://review.coreboot.org/c/coreboot/+/37441/60/src/mainboard/supermicro/… PS60, Line 30: .rcomp_targets = {100, 40, 20, 20, 26}, > Same question? Origin? Same document, and I can confirm Angel's values. -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 60 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 05 Jul 2020 16:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2020