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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42277 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC ...................................................................... mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/ramstage.c 3 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42277/1 diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index fe620fa..dd81bfd 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -45,3 +45,28 @@ return CB_SUCCESS; } + +enum cb_err ipmi_get_slot_id(uint8_t *slot_id) +{ + int ret; + struct ipmi_config_rsp { + struct ipmi_rsp resp; + uint8_t board_sku_id; + uint8_t board_rev_id; + uint8_t slot_id; + uint8_t slot_config_id; + } __packed; + struct ipmi_config_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, + NULL, 0, (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + *slot_id = rsp.slot_id; + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index 310ff27..b167473 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -8,6 +8,7 @@ #define IPMI_NETFN_OEM 0x30 #define IPMI_OEM_SET_PPIN 0x77 #define IPMI_OEM_GET_PCIE_CONFIG 0xf4 +#define IPMI_OEM_GET_BOARD_ID 0x37 #define PCIE_CONFIG_UNKNOWN 0x0 #define PCIE_CONFIG_A 0x1 @@ -24,4 +25,5 @@ enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); +enum cb_err ipmi_get_slot_id(uint8_t *slot_id); #endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index ae11296..f08eb9b 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -4,10 +4,31 @@ #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> +#include <stdio.h> #include "ipmi.h" +#define SLOT_ID_LEN 2 + extern struct fru_info_str fru_strings; +static char slot_id_str[SLOT_ID_LEN]; + +/* Override SMBIOS 2 Location In Chassis from BMC */ +const char *smbios_mainboard_location_in_chassis(void) +{ + uint8_t slot_id = 0; + + if (ipmi_get_slot_id(&slot_id) != CB_SUCCESS) + return ""; + + /* Sanity check, slot_id can only be 1~4 since there are 4 slots in YV3 */ + if (!slot_id || slot_id > 4) { + printk(BIOS_ERR, "slot_id %d is not between 1~4\n", slot_id); + return ""; + } + snprintf(slot_id_str, SLOT_ID_LEN, "%d", slot_id); + return slot_id_str; +} static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Gerrit-Change-Number: 42277 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: arch/x86/smbios: Add SMBIOS type8 data
by Bryant Ou (Code Review) 04 Jul '20

04 Jul '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40545 ) Change subject: arch/x86/smbios: Add SMBIOS type8 data ...................................................................... arch/x86/smbios: Add SMBIOS type8 data Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/40545/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c047d75..eb383b2 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -890,6 +890,41 @@ return len; } + +const struct port_information *__weak smbios_get_port_info(size_t *num_port) +{ + *num_port = 0; + return NULL; +} + +static int smbios_write_type8(unsigned long *current, int *handle) +{ + int len = sizeof(struct smbios_type8); + int totallen = 0, i; + const struct port_information *port; + size_t num_port; + + port = smbios_get_port_info(&num_port); + for (i = 0; i < num_port; i++, port++) { + struct smbios_type8 *t = (struct smbios_type8 *)*current; + memset(t, 0, sizeof(struct smbios_type8)); + t->type = SMBIOS_PORT_CONNECTOR_INFORMATION; + t->handle = *handle; + t->length = len - 2; + t->internal_reference_designator = + smbios_add_string(t->eos, port->internal_reference_designator); + t->internal_connector_type = port->internal_connector_type; + t->external_reference_designator = + smbios_add_string(t->eos, port->external_reference_designator); + t->external_connector_type = port->external_connector_type; + t->port_type = port->port_type; + *handle += 1; + *current += t->length + smbios_string_table_len(t->eos); + totallen += t->length + smbios_string_table_len(t->eos); + } + return totallen; +} + int smbios_write_type9(unsigned long *current, int *handle, const char *name, const enum misc_slot_type type, const enum slot_data_bus_bandwidth bandwidth, @@ -1187,6 +1222,8 @@ handle++)); len += smbios_write_type7_cache_parameters(&current, &handle, &max_struct_size, type4); + update_max(len, max_struct_size, smbios_write_type8(&current, + &handle)); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) diff --git a/src/include/smbios.h b/src/include/smbios.h index 184b2c8..60d9364 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,8 @@ u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); +const struct port_information *smbios_get_port_info(size_t *num_port); + #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) #define BIOS_CHARACTERISTICS_PNP (1 << 9) @@ -209,6 +211,7 @@ SMBIOS_SYSTEM_ENCLOSURE = 3, SMBIOS_PROCESSOR_INFORMATION = 4, SMBIOS_CACHE_INFORMATION = 7, + SMBIOS_PORT_CONNECTOR_INFORMATION = 8, SMBIOS_SYSTEM_SLOTS = 9, SMBIOS_OEM_STRINGS = 11, SMBIOS_EVENT_LOG = 15, @@ -483,6 +486,115 @@ u8 eos[2]; } __packed; +/* enum for connector types */ +enum type8_connector_types { + CONN_NONE = 0x00, + CONN_CENTRONICS = 0x01, + CONN_MINI_CENTRONICS = 0x02, + CONN_PROPRIETARY = 0x03, + CONN_DB_25_PIN_MALE = 0x04, + CONN_DB_25_PIN_FEMALE = 0x05, + CONN_DB_15_PIN_MALE = 0x06, + CONN_DB_15_PIN_FEMALE = 0x07, + CONN_DB_9_PIN_MALE = 0x08, + CONN_DB_9_PIN_FEMALE = 0x09, + CONN_RJ_11 = 0x0A, + CONN_RJ_45 = 0x0B, + CONN_50_PIN_MINI_SCSI = 0x0C, + CONN_MINI_DIN = 0x0D, + CONN_MICRO_DIN = 0x0E, + CONN_PS_2 = 0x0F, + CONN_INFRARED = 0x10, + CONN_HP_HIL = 0x11, + CONN_ACCESS_BUS_USB = 0x12, + CONN_SSA_SCSI = 0x13, + CONN_CIRCULAR_DIN_8_MALE = 0x14, + CONN_CIRCULAR_DIN_8_FEMALE = 0x15, + CONN_ON_BOARD_IDE = 0x16, + CONN_ON_BOARD_FLOPPY = 0x17, + CONN_9_PIN_DUAL_INLINE = 0x18, + CONN_25_PIN_DUAL_INLINE = 0x19, + CONN_50_PIN_DUAL_INLINE = 0x1A, + CONN_68_PIN_DUAL_INLINE = 0x1B, + CONN_ON_BOARD_SOUND_INPUT_FROM_CD_ROM = 0x1C, + CONN_MINI_CENTRONICS_TYPE14 = 0x1D, + CONN_MINI_CENTRONICS_TYPE26 = 0x1E, + CONN_MINI_JACK_HEADPHONES = 0x1F, + CONN_BNC = 0x20, + CONN_1394 = 0x21, + CONN_SAS_SATA = 0x22, + CONN_USB_TYPE_C = 0x23, + CONN_PC_98 = 0xA0, + CONN_PC_98_HIRESO = 0xA1, + CONN_PC_H98 = 0xA2, + CONN_PC98_NOTE = 0xA3, + CONN_PC_98_FULL = 0xA4, + CONN_OTHER = 0xFF, +}; + +/* enum for port types */ +enum type8_port_types { + TYPE_NONE = 0x00, + TYPE_PARALLEL_PORT_XT_AT_COMPATIBLE = 0x01, + TYPE_PARALLEL_PORT_PS_2 = 0x02, + TYPE_PARALLEL_PORT_ECP = 0x03, + TYPE_PARALLEL_PORT_EPP = 0x04, + TYPE_PARALLEL_PORT_ECP_EPP = 0x05, + TYPE_SERIAL_PORT_XT_AT_COMPATIBLE = 0x06, + TYPE_SERIAL_PORT_16450_COMPATIBLE = 0x07, + TYPE_SERIAL_PORT_16550_COMPATIBLE = 0x08, + TYPE_SERIAL_PORT_16550A_COMPATIBLE = 0x09, + TYPE_SCSI_PORT = 0x0A, + TYPE_MIDI_PORT = 0x0B, + TYPE_JOY_STICK_PORT = 0x0C, + TYPE_KEYBOARD_PORT = 0x0D, + TYPE_MOUSE_PORT = 0x0E, + TYPE_SSA_SCSI = 0x0F, + TYPE_USB = 0x10, + TYPE_FIREWIRE_IEEE_P1394 = 0x11, + TYPE_PCMCIA_TYPE_I = 0x12, + TYPE_PCMCIA_TYPE_II = 0x13, + TYPE_PCMCIA_TYPE_III = 0x14, + TYPE_CARDBUS = 0x15, + TYPE_ACCESS_BUS_PORT = 0x16, + TYPE_SCSI_II = 0x17, + TYPE_SCSI_WIDE = 0x18, + TYPE_PC_98 = 0x19, + TYPE_PC_98_HIRESO = 0x1A, + TYPE_PC_H98 = 0x1B, + TYPE_VIDEO_PORT = 0x1C, + TYPE_AUDIO_PORT = 0x1D, + TYPE_MODEM_PORT = 0x1E, + TYPE_NETWORK_PORT = 0x1F, + TYPE_SATA = 0x20, + TYPE_SAS = 0x21, + TYPE_MFDP = 0x22, + TYPE_THUNDERBOLT = 0x23, + TYPE_8251_COMPATIBLE = 0xA0, + TYPE_8251_FIFO_COMPATIBLE = 0xA1, + TYPE_OTHER = 0xFF, +}; + +struct port_information { + const char *internal_reference_designator; + uint8_t internal_connector_type; + const char *external_reference_designator; + uint8_t external_connector_type; + uint8_t port_type; +}; + +struct smbios_type8 { + uint8_t type; + uint8_t length; + uint16_t handle; + uint8_t internal_reference_designator; + uint8_t internal_connector_type; + uint8_t external_reference_designator; + uint8_t external_connector_type; + uint8_t port_type; + uint8_t eos[2]; +} __packed; + /* System Slots - Slot Type */ enum misc_slot_type { SlotTypeOther = 0x01, -- To view, visit https://review.coreboot.org/c/coreboot/+/40545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Gerrit-Change-Number: 40545 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[4.11_branch]: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a ...
by Philipp Deppenwiese (Code Review) 04 Jul '20

04 Jul '20

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42747 ) Change subject: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD variable ...................................................................... smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD variable If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can override SMBIOS type 0 version. One special scenario of using this feature is to assign a BIOS version to a coreboot image without the need to rebuild from source. VPD_SMBIOS_VERSION default is n. Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated from VPD. Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: insomniac <insomniac(a)slackware.it> Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit c746a748c4c5ec6421d7f9f5760717348231d091) Reviewed-on: https://review.coreboot.org/c/coreboot/+/42747 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/Kconfig M src/arch/x86/smbios.c 2 files changed, 71 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved insomniac: Looks good to me, but someone else must approve diff --git a/src/Kconfig b/src/Kconfig index ba9ae86..c031523 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -730,6 +730,16 @@ convertible, or tablet enclosure will be used if the appropriate system type is selected. +config VPD_SMBIOS_VERSION + bool "Populates SMBIOS type 0 version from the VPD_RO variable 'firmware_version'" + default n + depends on VPD && GENERATE_SMBIOS_TABLES + help + Selecting this option will read firmware_version from + VPD_RO and override SMBIOS type 0 version. One special + scenario of using this feature is to assign a BIOS version + to a coreboot image without the need to rebuild from source. + endmenu source "payloads/Kconfig" diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7deac63..f23e1dc 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -32,6 +32,8 @@ #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif +#include <drivers/vpd/vpd.h> +#include <stdlib.h> #define update_max(len, max_len, stmt) \ do { \ @@ -381,12 +383,64 @@ return t->length + smbios_string_table_len(t->eos); } +#define VERSION_VPD "firmware_version" +static const char *vpd_get_bios_version(void) +{ + int size; + const char *s; + char *version; + + s = vpd_find(VERSION_VPD, &size, VPD_RO); + if (!s) { + printk(BIOS_ERR, "Find version from VPD %s failed\n", VERSION_VPD); + return NULL; + } + + version = malloc(size + 1); + if (!version) { + printk(BIOS_ERR, "Failed to malloc %d bytes for VPD version\n", size + 1); + return NULL; + } + memcpy(version, s, size); + version[size] = '\0'; + printk(BIOS_DEBUG, "Firmware version %s from VPD %s\n", version, VERSION_VPD); + return version; +} + +static const char *get_bios_version(void) +{ + const char *s; + +#define SPACES \ + " " + + if (CONFIG(CHROMEOS)) + return SPACES; + + if (CONFIG(VPD_SMBIOS_VERSION)) { + s = vpd_get_bios_version(); + if (s != NULL) + return s; + } + + s = smbios_mainboard_bios_version(); + if (s != NULL) + return s; + + if (strlen(CONFIG_LOCALVERSION) != 0) { + printk(BIOS_DEBUG, "BIOS version set to CONFIG_LOCALVERSION: '%s'\n", + CONFIG_LOCALVERSION); + return CONFIG_LOCALVERSION; + } + + printk(BIOS_DEBUG, "SMBIOS firmware version is set to coreboot_version: '%s'\n", + coreboot_version); + return coreboot_version; +} + const char *__weak smbios_mainboard_bios_version(void) { - if (strlen(CONFIG_LOCALVERSION)) - return CONFIG_LOCALVERSION; - else - return coreboot_version; + return NULL; } static int smbios_write_type0(unsigned long *current, int handle) @@ -400,27 +454,14 @@ t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); -#if !CONFIG(CHROMEOS) t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); - t->bios_version = smbios_add_string(t->eos, - smbios_mainboard_bios_version()); -#else -#define SPACES \ - " " - t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); -#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES) u32 version_offset = (u32)smbios_string_table_len(t->eos); -#endif - t->bios_version = smbios_add_string(t->eos, SPACES); - -#if CONFIG(HAVE_ACPI_TABLES) /* SMBIOS offsets start at 1 rather than 0 */ - chromeos_get_chromeos_acpi()->vbt10 = - (u32)t->eos + (version_offset - 1); + chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1); #endif -#endif /* CONFIG_CHROMEOS */ - + t->bios_version = smbios_add_string(t->eos, get_bios_version()); uint32_t rom_size = CONFIG_ROM_SIZE; rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB); t->bios_rom_size = (rom_size / 65535) - 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/42747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Gerrit-Change-Number: 42747 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: lib/coreboot_table: Add Intel FSP version for cbmem to display
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41809 ) Change subject: lib/coreboot_table: Add Intel FSP version for cbmem to display ...................................................................... lib/coreboot_table: Add Intel FSP version for cbmem to display Add Intel FSP version to coreboot table LB_TAG_EXTRA_VERSION when FSP_ADD_VERSION_TO_CBMEM is selected. Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/lib/coreboot_table.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41809/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 075bd04..51c1cc3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -31,6 +31,9 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) +#include <fsp/util.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -408,6 +411,23 @@ } +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) +/* Add FSP version to coreboot table LB_TAG_EXTRA_VERSION */ +static void lb_strings_fsp_version(struct lb_header *header) +{ + struct lb_string *rec; + size_t len; + char fsp_version[FSP_VER_LEN] = {0}; + + fsp_get_version(fsp_version); + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_EXTRA_VERSION; + len = strlen(fsp_version); + rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); + memcpy(rec->string, fsp_version, len+1); +} +#endif + static void lb_record_version_timestamp(struct lb_header *header) { struct lb_timestamp *rec; @@ -516,6 +536,9 @@ /* Record our various random string information */ lb_strings(head); +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) + lb_strings_fsp_version(head); +#endif lb_record_version_timestamp(head); /* Record our framebuffer */ lb_framebuffer(head); -- To view, visit https://review.coreboot.org/c/coreboot/+/41809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Gerrit-Change-Number: 41809 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

8 28

Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Philipp Deppenwiese (Code Review) 04 Jul '20

04 Jul '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 52: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 52 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 04 Jul 2020 11:19:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different ...
by Philipp Deppenwiese (Code Review) 04 Jul '20

04 Jul '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41527 ) Change subject: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/41527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Gerrit-Change-Number: 41527 Gerrit-PatchSet: 20 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Sat, 04 Jul 2020 11:18:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/pc80/tpm: Remove LPC_TPM
by Kyösti Mälkki (Code Review) 04 Jul '20

04 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41872 ) Change subject: drivers/pc80/tpm: Remove LPC_TPM ...................................................................... drivers/pc80/tpm: Remove LPC_TPM Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm is present in devicetree.cb it is necessary to always include the driver in the build. Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M configs/builder/config.lenovo_t420 M configs/builder/config.lenovo_t420s M configs/builder/config.lenovo_t430s M configs/builder/config.lenovo_t520 M configs/builder/config.lenovo_t530 M configs/builder/config.lenovo_x220 M configs/builder/config.lenovo_x220i M configs/builder/config.lenovo_x230 M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc M src/security/tpm/Kconfig 11 files changed, 10 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/41872/1 diff --git a/configs/builder/config.lenovo_t420 b/configs/builder/config.lenovo_t420 index e4e4b9b..5ac036d 100644 --- a/configs/builder/config.lenovo_t420 +++ b/configs/builder/config.lenovo_t420 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t420s b/configs/builder/config.lenovo_t420s index 7593b7a..f0b312b 100644 --- a/configs/builder/config.lenovo_t420s +++ b/configs/builder/config.lenovo_t420s @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t430s b/configs/builder/config.lenovo_t430s index b21dbba..682b17e 100644 --- a/configs/builder/config.lenovo_t430s +++ b/configs/builder/config.lenovo_t430s @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t520 b/configs/builder/config.lenovo_t520 index 1d7816e..4bbbb25 100644 --- a/configs/builder/config.lenovo_t520 +++ b/configs/builder/config.lenovo_t520 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t530 b/configs/builder/config.lenovo_t530 index 0106bbc..635e355 100644 --- a/configs/builder/config.lenovo_t530 +++ b/configs/builder/config.lenovo_t530 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220 b/configs/builder/config.lenovo_x220 index da5a474..29d9639 100644 --- a/configs/builder/config.lenovo_x220 +++ b/configs/builder/config.lenovo_x220 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220i b/configs/builder/config.lenovo_x220i index 5612f5b..24e381d 100644 --- a/configs/builder/config.lenovo_x220i +++ b/configs/builder/config.lenovo_x220i @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x230 b/configs/builder/config.lenovo_x230 index d897f44..5040145 100644 --- a/configs/builder/config.lenovo_x230 +++ b/configs/builder/config.lenovo_x230 @@ -12,7 +12,6 @@ CONFIG_GBE_BIN_PATH="site-local/gbe.bin" CONFIG_PCIEXP_CLK_PM=y CONFIG_PCIEXP_L1_SUB_STATE=y -CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 853801b..4a40b29 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -1,13 +1,14 @@ -config LPC_TPM +config MAINBOARD_HAS_LPC_TPM bool default n help - LPC TPM driver is enabled! + Board has LPC TPM support + +if MAINBOARD_HAS_LPC_TPM config TPM_TIS_BASE_ADDRESS hex default 0xfed40000 - depends on LPC_TPM help This can be used to adjust the TPM memory base address. The default is specified by the TCG PC Client Specific TPM @@ -17,14 +18,8 @@ config TPM_PIRQ hex default 0x0 - depends on LPC_TPM help This can be used to specify a PIRQ to use instead of SERIRQ, which is needed for SPI TPM interrupt support on x86. -config MAINBOARD_HAS_LPC_TPM - bool - default n - select LPC_TPM - help - Board has LPC TPM support +endif diff --git a/src/drivers/pc80/tpm/Makefile.inc b/src/drivers/pc80/tpm/Makefile.inc index 0de1b76..a16f6af 100644 --- a/src/drivers/pc80/tpm/Makefile.inc +++ b/src/drivers/pc80/tpm/Makefile.inc @@ -1,4 +1,4 @@ -verstage-$(CONFIG_LPC_TPM) += tis.c -romstage-$(CONFIG_LPC_TPM) += tis.c -ramstage-$(CONFIG_LPC_TPM) += tis.c -postcar-$(CONFIG_LPC_TPM) += tis.c +verstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +romstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +ramstage-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c +postcar-$(CONFIG_MAINBOARD_HAS_LPC_TPM) += tis.c diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index b6a7781..e1255d1 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -82,7 +82,7 @@ config TPM_RDRESP_NEED_DELAY bool "Enable Delay Workaround for TPM" default n - depends on LPC_TPM + depends on MAINBOARD_HAS_LPC_TPM help Certain TPMs seem to need some delay when reading response to work around a race-condition-related issue, possibly -- To view, visit https://review.coreboot.org/c/coreboot/+/41872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce Gerrit-Change-Number: 41872 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: doc/mb/ocp: Add documentation for Delta Lake
by Jonathan Zhang (Code Review) 04 Jul '20

04 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42947 ) Change subject: doc/mb/ocp: Add documentation for Delta Lake ...................................................................... doc/mb/ocp: Add documentation for Delta Lake Add OCP platform Delta Lake documentation. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e --- A Documentation/mainboard/ocp/deltalake.md 1 file changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/42947/1 diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md new file mode 100644 index 0000000..3af893a --- /dev/null +++ b/Documentation/mainboard/ocp/deltalake.md @@ -0,0 +1,98 @@ +# OCP Delta Lake + +This page describes coreboot support status for the [OCP] (Open Compute Project) +Delta Lake server platform. + +## Introduction + +OCP Delta Lake server platform is a component of multi-host server system +Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020]. + +Delta Lake server is a one socket CooperLake Sacalable Processor server. + +Yosemite-V3 has multiple configurations. Depending on configurations, it may +host up to 4 Delta Lake servers in one sled. + +Yosemite-V3 and Delta Lake are currently in DVT phase. Facebook, Intel and partners +jointly develop FSP/coreboot/Linuxboot solution on Delta Lake as a hack project. + +## Required blobs + +This board currently requires: +- FSP blob: The blob (Intel CooperLake Scalable Processor Firmware Support Package) + is not yet available to the public. It will be made public some time after the MP + of CooperLake Scalable Processor when the FSP is mature. +- Microcode: Not yet available to the public. +- ME binary: Not yet available to the public. + +## Payload +- Linuxboot: This is necessary only if you use Linuxboot as coreboot payload. + U-root as initramfs, is used in the joint development. It can be built + following [All about u-root]. + +## Flashing coreboot + +To do in-band FW image update, use [flashrom]: + flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \ + -i bios --noverify-all -w <path to coreboot image> + +From OpenBMC, to update FW image: + fw-util slotx --update bios <path to coreboot image> + +To power off/on the host: + power-util slotx off + power-util slotx on + +To connect to console through SOL (Serial Over Lan): + sol-util slotx + +## Working features +The solution is developed using Linuxboot payload. The Linuxboot +kernel versions tried is 5.2.9. The initramfs image is u-root. +- Most SMBIOS types +- BMC integration: + - BMC readiness check + - IPMI commands + - watchdog timer + - POST complete pin acknowledgement +- SEL record generation +- Early serial output +- port 80h direct to GPIO +- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- Skipping memory training upon subsequent reboots +- BMC crash dump +- Error injection through ITP + +## Firmware configurations +[ChromeOS VPD] is used to store most of firmware configurations. RO_VPD +holds default values, while RW_VPD holds customized values. + +VPD variables supported are: +- firmware_version: This variable holds overall firmware version. coreboot + uses its value to populate smbios type 1 version field. + +## Known issues / feature gaps +- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not + support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. +- VT-d is not supported. An IPS ticket is filed with Intel. +- PCIe bifuration is not supported. An IPS ticket is filed with Intel. +- SMBIOS type 7 and type 17 are not populated. +- ME based power capping. + +## Technology + +```eval_rst ++------------------------+---------------------------------------------+ +| Processor (1 socket) | Intel CooperLake Scalable Processor | ++------------------------+---------------------------------------------+ +| BMC | Aspeed AST 2500 | ++------------------------+---------------------------------------------+ +| PCH | Intel Lewisburg C621 | ++------------------------+---------------------------------------------+ +``` + +[OCP]: https://www.opencompute.org +[OCP virtual summit 2020]: https://www.opencompute.org/summit/virtual-summit/schedule +[flashrom]: https://flashrom.org/Flashrom +[All about u-root]: https://github.com/linuxboot/book/tree/master/u-root +[ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md -- To view, visit https://review.coreboot.org/c/coreboot/+/42947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e Gerrit-Change-Number: 42947 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard
by Christian Walter (Code Review) 04 Jul '20

04 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42479 ) Change subject: MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard ...................................................................... MAINTAINERS: Add Maintainers for Prodrive Hermes Mainboard Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42479/1 diff --git a/MAINTAINERS b/MAINTAINERS index e15e31c..a8c8365 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -367,6 +367,12 @@ S: Maintained F: src/mainboard/protectli/ +PRODRIVE HERMES MAINBOARD +M: Christian Walter <christian.walter(a)9elements.com> +M: Patrick Rudolph <patrick.rudolph(a)9elements.com> +S: Maintained +F: src/mainboard/prodrive/hermes + SIEMENS MC_xxxx MAINBOARDS M: Werner Zeh <werner.zeh(a)siemens.com> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/42479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaed81016be9cd2845b3a2c55ee1a5ac4d317081 Gerrit-Change-Number: 42479 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41279 ) Change subject: mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC ...................................................................... mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMC 1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/Makefile.inc A src/mainboard/ocp/deltalake/ipmi.c A src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/ramstage.c 5 files changed, 143 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/41279/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index d61a3a6..698c57b 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -9,6 +9,7 @@ select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select IPMI_KCS + select OCP_DMI config IPMI_KCS_REGISTER_SPACING int diff --git a/src/mainboard/ocp/deltalake/Makefile.inc b/src/mainboard/ocp/deltalake/Makefile.inc index 0cc98d4..90a3c10 100644 --- a/src/mainboard/ocp/deltalake/Makefile.inc +++ b/src/mainboard/ocp/deltalake/Makefile.inc @@ -19,7 +19,7 @@ romstage-y += romstage.c -ramstage-y += ramstage.c +ramstage-y += ramstage.c ipmi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c new file mode 100644 index 0000000..daf2d7b --- /dev/null +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/ocp/dmi/ocp_dmi.h> + +#include "ipmi.h" + +enum cb_err ipmi_set_ppin(struct ppin_req *req) +{ + int ret; + struct ipmi_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_SET_PPIN, + (const unsigned char *) req, sizeof(*req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err ipmi_get_pcie_config(uint8_t *pcie_config) +{ + int ret; + struct ipmi_config_rsp { + struct ipmi_rsp resp; + uint8_t config; + } __packed; + struct ipmi_config_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_PCIE_CONFIG, + NULL, 0, (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + *pcie_config = rsp.config; + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h new file mode 100644 index 0000000..6134d21 --- /dev/null +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#ifndef DELTALAKE_IPMI_H +#define DELTALAKE_IPMI_H +#include <types.h> + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_PPIN 0x77 +#define IPMI_OEM_GET_PCIE_CONFIG 0xf4 + +#define PCIE_CONFIG_UNKNOWN 0x0 +#define PCIE_CONFIG_A 0x1 +#define PCIE_CONFIG_B 0x2 +#define PCIE_CONFIG_C 0x3 +#define PCIE_CONFIG_D 0x4 + +struct ppin_req { + uint32_t cpu0_lo; + uint32_t cpu0_hi; + uint32_t cpu1_lo; + uint32_t cpu1_hi; +} __packed; + +enum cb_err ipmi_set_ppin(struct ppin_req *req); +enum cb_err ipmi_get_pcie_config(uint8_t *config); +#endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index c9e3fbb..44699a3 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -1,8 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */ +#include <console/console.h> +#include <drivers/ipmi/ipmi_ops.h> +#include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> +#include <stdio.h> + +#include "ipmi.h" + +extern struct fru_info_str fru_strings; + +static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + uint8_t pcie_config = 0; + + /* OEM string 1 to 6 */ + ocp_oem_smbios_strings(dev, t); + + /* TODO: Add real OEM string 7, add TBF for now */ + t->count = smbios_add_oem_string(t->eos, TBF); + + /* Add OEM string 8 */ + if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) { + switch (pcie_config) { + case PCIE_CONFIG_UNKNOWN: + t->count = smbios_add_oem_string(t->eos, "0x0: Unknown"); + break; + case PCIE_CONFIG_A: + t->count = smbios_add_oem_string(t->eos, "0x1: YV3 Config-A"); + break; + case PCIE_CONFIG_B: + t->count = smbios_add_oem_string(t->eos, "0x2: YV3 Config-B"); + break; + case PCIE_CONFIG_C: + t->count = smbios_add_oem_string(t->eos, "0x3: YV3 Config-C"); + break; + case PCIE_CONFIG_D: + t->count = smbios_add_oem_string(t->eos, "0x4: YV3 Config-D"); + break; + default: + t->count = smbios_add_oem_string(t->eos, "Check BMC return data"); + } + } else { + printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); + } +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_strings = dl_oem_smbios_strings, + read_fru_areas(BMC_KCS_BASE, FRU_DEVICE_ID, 0, &fru_strings); +} void mainboard_silicon_init_params(FSPS_UPD *params) { } + +static void mainboard_final(void *chip_info) +{ + struct ppin_req req = {0}; + + req.cpu0_lo = xeon_sp_ppin[0].lo; + req.cpu0_hi = xeon_sp_ppin[0].hi; + /* Set PPIN to BMC */ + if (ipmi_set_ppin(&req) != CB_SUCCESS) + printk(BIOS_ERR, "ipmi_set_ppin failed\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Gerrit-Change-Number: 41279 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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