coreboot-gerrit July 2020

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Change in coreboot[master]: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM
by Nico Huber (Code Review) 03 Jul '20

03 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35489 ) Change subject: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM ...................................................................... sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM Instead of using fragile dev_find_slot_on_smbus(), link the devices in the devicetree directly. msi/ms9652 referenced a non-existing device (commented), so remove the reference entirely. Change-Id: I050e681142c5b19f97fec865e887eda157ee830b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/msi/ms9652_fam10/devicetree.cb M src/mainboard/supermicro/h8dmr_fam10/devicetree.cb M src/mainboard/supermicro/h8qme_fam10/devicetree.cb M src/mainboard/tyan/s2912_fam10/devicetree.cb M src/southbridge/nvidia/ck804/chip.h M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/mcp55/chip.h M src/southbridge/nvidia/mcp55/nic.c 8 files changed, 56 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35489/1 diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index c6dae6d..1815870 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -149,9 +149,6 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end device pci 18.0 on end # HT 1.0 diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index ee88c31..89c579e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -103,7 +103,7 @@ # device i2c 55 on end # end chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -133,9 +133,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 317d643..de78ce2 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -56,11 +56,8 @@ end device pci 1.1 on end device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -84,9 +81,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index e49e16b..4a4118e 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -103,7 +103,7 @@ # device i2c 55 on end # end chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -127,9 +127,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h index b1676ce..16fdbde 100644 --- a/src/southbridge/nvidia/ck804/chip.h +++ b/src/southbridge/nvidia/ck804/chip.h @@ -17,14 +17,15 @@ #ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H #define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_ck804_config { unsigned int usb1_hc_reset : 1; unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; + DEVTREE_CONST struct device *mac_eeprom; }; extern struct pci_operations ck804_pci_ops; diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index 5dbb6b4..188dc23 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -47,37 +47,31 @@ conf = dev->chip_info; - if (conf->mac_eeprom_smbus != 0) { + if (conf->mac_eeprom) { /* Read MAC address from EEPROM at first. */ - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); - - if (dev_eeprom) { - /* If that is valid we will use that. */ - unsigned char dat[6]; - int i, status; - for (i = 0; i < 6; i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) - break; - dat[i] = status & 0xff; + /* If that is valid we will use that. */ + unsigned char dat[6]; + int i, status; + for (i = 0; i < 6; i++) { + status = smbus_read_byte(conf->mac_eeprom, i); + if (status < 0) + break; + dat[i] = status & 0xff; + } + if (status >= 0) { + mac_l = 0; + for (i = 3; i >= 0; i--) { + mac_l <<= 8; + mac_l += dat[i]; } - if (status >= 0) { - mac_l = 0; - for (i = 3; i >= 0; i--) { - mac_l <<= 8; - mac_l += dat[i]; + if (mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for (i = 5; i >= 4; i--) { + mac_h <<= 8; + mac_h += dat[i]; } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i = 5; i >= 4; i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } + eeprom_valid = 1; } } } diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h index 4bc8428..36eea22 100644 --- a/src/southbridge/nvidia/mcp55/chip.h +++ b/src/southbridge/nvidia/mcp55/chip.h @@ -18,14 +18,15 @@ #ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H #define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; + DEVTREE_CONST struct device *mac_eeprom; }; #endif diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index af4df44..b562503 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -124,36 +124,31 @@ conf = dev->chip_info; - if (conf->mac_eeprom_smbus != 0) { + if (conf->mac_eeprom) { // read MAC address from EEPROM at first - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); - - if (dev_eeprom) { - // if that is valid we will use that - unsigned char dat[6]; - int status; - int i; - for (i=0;i<6;i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) break; - dat[i] = status & 0xff; + // if that is valid we will use that + unsigned char dat[6]; + int status; + int i; + for (i=0;i<6;i++) { + status = smbus_read_byte(conf->mac_eeprom, i); + if (status < 0) break; + dat[i] = status & 0xff; + } + if (status >= 0) { + mac_l = 0; + for (i=3;i>=0;i--) { + mac_l <<= 8; + mac_l += dat[i]; } - if (status >= 0) { - mac_l = 0; - for (i=3;i>=0;i--) { - mac_l <<= 8; - mac_l += dat[i]; + if (mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for (i=5;i>=4;i--) { + mac_h <<= 8; + mac_h += dat[i]; } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i=5;i>=4;i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } + eeprom_valid = 1; } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I050e681142c5b19f97fec865e887eda157ee830b Gerrit-Change-Number: 35489 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Paul Menzel (Code Review) 03 Jul '20

03 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... Patch Set 2: a -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Jul 2020 06:54:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: chromeec: fix error path return value
by Paul Menzel (Code Review) 03 Jul '20

03 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43045 ) Change subject: chromeec: fix error path return value ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bf8d74229f4ac2bf87f9ee83e0c88c3c94de765 Gerrit-Change-Number: 43045 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Jul 2020 06:39:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: volteer: enable VBOOT_EC_EFS
by Paul Menzel (Code Review) 03 Jul '20

03 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43044 ) Change subject: volteer: enable VBOOT_EC_EFS ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/43044/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43044/1//COMMIT_MSG@9 PS1, Line 9: EFS Please mention what EFS is. -- To view, visit https://review.coreboot.org/c/coreboot/+/43044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71bb169242b2511b4a4102d46a6981d72d07806 Gerrit-Change-Number: 43044 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Jul 2020 06:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 k...
by Johnny Li (Code Review) 03 Jul '20

03 Jul '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43058 ) Change subject: mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 kHz for touch ...................................................................... mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 kHz for touch The current I2C1 bus frequency is 351 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C1 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C1 frequency is 390kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: I593c3cfdb50e94e222e5c07176ee3c6fdd29e835 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/43058/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 2f853e1..aee6954 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -190,7 +190,7 @@ .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 163, + .scl_lcnt = 162, .scl_hcnt = 75, .sda_hold = 36, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/43058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I593c3cfdb50e94e222e5c07176ee3c6fdd29e835 Gerrit-Change-Number: 43058 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 k...
by Johnny Li (Code Review) 03 Jul '20

03 Jul '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43057 ) Change subject: mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 kHz for Touch ...................................................................... mb/google/volteer/variant/volteer: Turn I2C1 bus freq closer to 400 kHz for Touch The current I2C2 bus frequency is 356 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C1 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C1 frequency is 390kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: I76953a9a62041779e6d8c6418073f01ec08a5d67 --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43057/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 6549932..2f853e1 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -188,9 +188,6 @@ }, .i2c[1] = { .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, .scl_lcnt = 163, @@ -198,6 +195,9 @@ .sda_hold = 36, }, }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, .i2c[3] = { .speed = I2C_SPEED_FAST, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/43057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76953a9a62041779e6d8c6418073f01ec08a5d67 Gerrit-Change-Number: 43057 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variant/volteer: Turn I2C2 bus freq closer to 400 k...
by Johnny Li (Code Review) 03 Jul '20

03 Jul '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43053 ) Change subject: mb/google/volteer/variant/volteer: Turn I2C2 bus freq closer to 400 kHz for WLAN ...................................................................... mb/google/volteer/variant/volteer: Turn I2C2 bus freq closer to 400 kHz for WLAN The current I2C2 bus frequency is 344 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C2 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C2 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: I5c4ec105f12ac3938124547340c9177290b7b2bc --- M src/mainboard/google/volteer/variants/volteer/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43053/1 diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index 3effc6d..6549932 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -191,16 +191,16 @@ }, .i2c[2] = { .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { + .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 153, + .scl_lcnt = 163, .scl_hcnt = 75, .sda_hold = 36, }, }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, .i2c[5] = { .speed = I2C_SPEED_FAST, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/43053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c4ec105f12ac3938124547340c9177290b7b2bc Gerrit-Change-Number: 43053 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/tianocore: Don't recurse submodules
by Benjamin Doron (Code Review) 03 Jul '20

03 Jul '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43063 ) Change subject: payloads/tianocore: Don't recurse submodules ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/43063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c5d6dd6e5070720870fc22b2476c6fe8dc7fd40 Gerrit-Change-Number: 43063 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Jul 2020 04:44:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different ...
by Johnny Lin (Code Review) 03 Jul '20

03 Jul '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41527 ) Change subject: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/41527/20/src/mainboard/ocp/deltala… File src/mainboard/ocp/deltalake/romstage.c: https://review.coreboot.org/c/coreboot/+/41527/20/src/mainboard/ocp/deltala… PS20, Line 18: mupd->FspmConfig.IioConfigIOU2[0] = IIO_BIFURCATE_xxxxxxxx; : mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxx16; : mupd->FspmConfig.IioConfigIOU4[0] = IIO_BIFURCATE_xxxxxxxx; > This changed? The bifurcation for CONFIG C is IOU0 and IOU1: x4x4x4x4, IOU2: CPX doesn't have it. IOU3: x16 for NIC. FspmUpd->FspmConfig.IioConfigIOU0[0] => Maps to physical PCI express lanes Port 1A~1D. FspmUpd->FspmConfig.IioConfigIOU1[0] => Maps to physical PCI express lanes Port 2A~2D. FspmUpd->FspmConfig.IioConfigIOU2[0] => CPX doesn’t have this port. FspmUpd->FspmConfig.IioConfigIOU3[0] => Maps to physical PCI express lanes Port 3A~3D. FspmUpd->FspmConfig.IioConfigIOU4[0] ==> is not used by YV3 so I set it to IIO_BIFURCATE_xxxxxxxx. We have an excel table for the IIO bifurcation for each config if you need more detail. -- To view, visit https://review.coreboot.org/c/coreboot/+/41527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Gerrit-Change-Number: 41527 Gerrit-PatchSet: 20 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Jul 2020 03:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable HECI interface
by Jamie Ryu (Code Review) 03 Jul '20

03 Jul '20

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42307 ) Change subject: mb/intel/tglrvp: Enable HECI interface ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23117fa96503942e6a72765dd3fd1cc762e3f705 Gerrit-Change-Number: 42307 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Jul 2020 03:02:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2020