coreboot-gerrit July 2020

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Change in gerrit-avatars[master]: Add Christian Walter Avatar
by Christian Walter (Code Review) 03 Jul '20

03 Jul '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/43016 ) Change subject: Add Christian Walter Avatar ...................................................................... Add Christian Walter Avatar Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Change-Id: If4ab7192e49e2507763c3d8fc73375cac7b0f215 --- A 1002388.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/16/43016/1 diff --git a/1002388.jpg b/1002388.jpg new file mode 100644 index 0000000..b988ede --- /dev/null +++ b/1002388.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/43016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: If4ab7192e49e2507763c3d8fc73375cac7b0f215 Gerrit-Change-Number: 43016 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Add RTC failure checking
by Jonathan Zhang (Code Review) 03 Jul '20

03 Jul '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43004 ) Change subject: soc/intel/xeon_sp: Add RTC failure checking ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/c/coreboot/+/43004/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43004/2//COMMIT_MSG@8 PS2, Line 8: Please add some explanation of the flow. Here we are checking these error conditions: RTC battery is removed; RTC battery is dead. https://review.coreboot.org/c/coreboot/+/43004/2/src/soc/intel/xeon_sp/pmut… File src/soc/intel/xeon_sp/pmutil.c: https://review.coreboot.org/c/coreboot/+/43004/2/src/soc/intel/xeon_sp/pmut… PS2, Line 16: return !!(gen_pmcon_b & RTC_BATTERY_DEAD); If RTC battery is dead, let's print an error message. https://review.coreboot.org/c/coreboot/+/43004/2/src/soc/intel/xeon_sp/pmut… PS2, Line 24: __func__, (pmcon_b&0x04)?"removed":"inserted", pmcon_b); If RTC battery is removed, let's print an error message. Otherwise, a SPEW message. https://review.coreboot.org/c/coreboot/+/43004/2/src/soc/intel/xeon_sp/roms… File src/soc/intel/xeon_sp/romstage.c: https://review.coreboot.org/c/coreboot/+/43004/2/src/soc/intel/xeon_sp/roms… PS2, Line 21: if (soc_get_rtc_failed()) If RTC failed, let's print an error message. -- To view, visit https://review.coreboot.org/c/coreboot/+/43004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Gerrit-Change-Number: 43004 Gerrit-PatchSet: 2 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Comment-Date: Fri, 03 Jul 2020 16:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failu...
by Jonathan Zhang (Code Review) 03 Jul '20

03 Jul '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43005 ) Change subject: mb/ocp/deltalake: Send OEM IPMI command for CMOS clear when RTC failure is detected ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/43005/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43005/6//COMMIT_MSG@11 PS6, Line 11: This is to let the payload (LinuxBoot) do some handling. What kind of handling? https://review.coreboot.org/c/coreboot/+/43005/6//COMMIT_MSG@13 PS6, Line 13: Tested on OCP Delta Lake How is this tested? How do you simulate RTC failure? https://review.coreboot.org/c/coreboot/+/43005/6/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ipmi.h: https://review.coreboot.org/c/coreboot/+/43005/6/src/mainboard/ocp/deltalak… PS6, Line 42: uint8_t boot_dev4; Regarding boot order, how does the difference between systemboot and UEFI BDS affect it? What is boot_mode? How does user know which boot_dev (a uinit8_t) is for which boot device (a string)? -- To view, visit https://review.coreboot.org/c/coreboot/+/43005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f Gerrit-Change-Number: 43005 Gerrit-PatchSet: 6 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Comment-Date: Fri, 03 Jul 2020 16:21:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: adjust eSPI virtual irq settings
by Aaron Durbin (Code Review) 03 Jul '20

03 Jul '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43011 ) Change subject: mb/google/zork: adjust eSPI virtual irq settings ...................................................................... mb/google/zork: adjust eSPI virtual irq settings The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 --- M src/mainboard/google/zork/variants/baseboard/devicetree.cb M src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h 2 files changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43011/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 3cc311b..beb2c71 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -93,19 +93,11 @@ .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), }" register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" - register "irq_override" = "{ - /* PS/2 keyboard IRQ1 override */ - {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, - - /* PS/2 mouse IRQ12 override */ - {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index 8ef0645..ff42989 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -59,8 +59,6 @@ #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -#define SIO_EC_PS2K_IRQ IRQ (Level, ActiveHigh, Exclusive) {1} -#define SIO_EC_PS2M_IRQ IRQ (Level, ActiveHigh, Exclusive) {12} /* * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in -- To view, visit https://review.coreboot.org/c/coreboot/+/43011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Gerrit-Change-Number: 43011 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: fix eSPI virtual wire polarity encoding
by Aaron Durbin (Code Review) 03 Jul '20

03 Jul '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43010 ) Change subject: soc/amd/common: fix eSPI virtual wire polarity encoding ...................................................................... soc/amd/common: fix eSPI virtual wire polarity encoding eSPI interrupts are active level high. The eSPI polarity register in the chipset inverts incoming signals if the corresonding bit is 0 in the register. Therefore, all active high (edge or level) virtual wire interrupts need to ensure they are not inverted. And really the sender of the interrupts should be conforming to the the eSPI spec. As such inverting any signals should not be necessary, but this register in the chipset allows for fixing up those misbehaviors. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48 --- M src/soc/amd/common/block/include/amdblocks/espi.h 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43010/1 diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h index e882af0..2bfef89 100644 --- a/src/soc/amd/common/block/include/amdblocks/espi.h +++ b/src/soc/amd/common/block/include/amdblocks/espi.h @@ -43,14 +43,11 @@ #define ESPI_OOB_CH_EN (1 << 1) #define ESPI_FLASH_CH_EN (1 << 0) -/* - * Virtual wire interrupt polarity. If the interrupt is active level high or active falling - * edge, then controller expects its bit to be cleared in ESPI_RXVW_POLARITY whereas if the - * interrupt is active level low or active rising edge, then its bit needs to be set in - * ESPI_RXVW_POLARITY. - */ -#define ESPI_VW_IRQ_LEVEL_HIGH(x) (0 << (x)) -#define ESPI_VW_IRQ_LEVEL_LOW(x) (1 << (x)) +/* Virtual wire interrupt polarity. eSPI interrupts are active level high signals. The + polarity register inverts the incoming signal if the associated bit with the irq is + 0. */ +#define ESPI_VW_IRQ_LEVEL_HIGH(x) (1 << (x)) +#define ESPI_VW_IRQ_LEVEL_LOW(x) (0 << (x)) #define ESPI_VW_IRQ_EDGE_HIGH(x) (1 << (x)) #define ESPI_VW_IRQ_EDGE_LOW(x) (0 << (x)) -- To view, visit https://review.coreboot.org/c/coreboot/+/43010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7346bb0484506d96d7ab2e6d046ffa0571683a48 Gerrit-Change-Number: 43010 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/pmx_mux: Remove redundant declaration
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41871 ) Change subject: drivers/intel/pmx_mux: Remove redundant declaration ...................................................................... drivers/intel/pmx_mux: Remove redundant declaration Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/pmc_mux/chip.h M src/soc/intel/tigerlake/pmc.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/41871/1 diff --git a/src/drivers/intel/pmc_mux/chip.h b/src/drivers/intel/pmc_mux/chip.h index f73a070..dcca2a3 100644 --- a/src/drivers/intel/pmc_mux/chip.h +++ b/src/drivers/intel/pmc_mux/chip.h @@ -3,8 +3,6 @@ #ifndef __DRIVERS_INTEL_PMC_MUX_H__ #define __DRIVERS_INTEL_PMC_MUX_H__ -extern struct chip_operations drivers_intel_pmc_mux_ops; - struct drivers_intel_pmc_mux_config { }; diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 84a18e3..8afa412 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -124,6 +124,9 @@ dev_path(dev)); } +/* FIXME: Rewrite loop below without this. */ +extern struct chip_operations drivers_intel_pmc_mux_ops; + /* By default, TGL uses the PMC MUX for all ports, so port_number is unused */ const struct device *soc_get_pmc_mux_device(int port_number) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie64b267ac01afa9774105e1ab8a7c18021726ff3 Gerrit-Change-Number: 41871 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi/acpi.h: Add processor x2APIC and GICC affinity struct
by HAOUAS Elyes (Code Review) 03 Jul '20

03 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43013 ) Change subject: acpi/acpi.h: Add processor x2APIC and GICC affinity struct ...................................................................... acpi/acpi.h: Add processor x2APIC and GICC affinity struct Change-Id: I0ba611b77cd24eca73b499e8173890283d54002a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/acpi/acpi.h 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/43013/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 9b6cf4c..464f018 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -235,6 +235,33 @@ u32 resv2[2]; } __packed acpi_srat_mem_t; +/* TODO: add SRAT Processor x2APIC and GICC Affinity Structure */ +/* SRAT: Processor Local x2APIC Affinity Structure */ +typedef struct acpi_srat_x2apic_cpu { + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (24) */ + u16 resv; /* Reserved, must be zero */ + u32 proximity_domain; + u32 x2apic_id; + u32 flags; /* bit 0: if clear, the OSPM ignores the contents of acpi_srat_x2apic_cpu + * bit[31:1] must be 0 + */ + u32 clock_domain; + u32 resv1; +} __packed acpi_srat_x2apic_cpu_t; + +/* SRAT: GICC Affinity Structure */ +typedef struct acpi_srat_gicc { + u8 type; /* Type (3) */ + u8 length; /* Length in bytes (18) */ + u32 proximity_domain; + u32 processor_uid + u32 flags; /* bit 0: if clear, the OSPM ignores the contents of acpi_srat_gicc. + * bit[31:1] must be 0 + */ + u32 clock_domain; +} __packed acpi_srat_gicc; + /* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { acpi_header_t header; -- To view, visit https://review.coreboot.org/c/coreboot/+/43013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba611b77cd24eca73b499e8173890283d54002a Gerrit-Change-Number: 43013 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41706 ) Change subject: [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers ...................................................................... [WIP] mb/intel/cannonlake_rvp: Unconditionally select audio drivers Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/41706/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index e4885a8..b34079b 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -10,6 +10,9 @@ select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_GENERIC_MAX98357A select SOC_INTEL_CANNONLAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE @@ -42,8 +45,6 @@ config INCLUDE_SND_MAX98357_DA7219_NHLT bool "Include blobs for audio with MAX98357_DA7219" - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_DA7219 @@ -51,7 +52,6 @@ config INCLUDE_SND_MAX98373_NHLT bool "Include blobs for audio with MAX98373" - select DRIVERS_I2C_MAX98373 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_MAX98373 -- To view, visit https://review.coreboot.org/c/coreboot/+/41706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Gerrit-Change-Number: 41706 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/intel/coffeelake_rvp: Unconditionally select audio drivers
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41705 ) Change subject: [WIP] mb/intel/coffeelake_rvp: Unconditionally select audio drivers ...................................................................... [WIP] mb/intel/coffeelake_rvp: Unconditionally select audio drivers Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/coffeelake_rvp/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/41705/1 diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 1b1a85c..fe6f2f3 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -11,6 +11,9 @@ select MAINBOARD_HAS_CHROMEOS select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_MAX98373 + select DRIVERS_GENERIC_MAX98357A select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU @@ -74,8 +77,6 @@ config INCLUDE_SND_MAX98357_DA7219_NHLT bool "Include blobs for audio with MAX98357_DA7219" - select DRIVERS_GENERIC_MAX98357A - select DRIVERS_I2C_DA7219 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_DA7219 @@ -83,7 +84,6 @@ config INCLUDE_SND_MAX98373_NHLT bool "Include blobs for audio with MAX98373" - select DRIVERS_I2C_MAX98373 select NHLT_DMIC_4CH_16B select NHLT_DMIC_2CH_16B select NHLT_MAX98373 -- To view, visit https://review.coreboot.org/c/coreboot/+/41705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2 Gerrit-Change-Number: 41705 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPI
by Kyösti Mälkki (Code Review) 03 Jul '20

03 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41703 ) Change subject: [WIP] mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPI ...................................................................... [WIP] mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPI Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/icelake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41703/1 diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index 8331f1b..834ccc8 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -11,6 +11,7 @@ select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_ICELAKE diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index a1283bd..af08c23 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -7,6 +7,7 @@ select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 + select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI select GENERIC_SPD_BIN -- To view, visit https://review.coreboot.org/c/coreboot/+/41703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Gerrit-Change-Number: 41703 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020