coreboot-gerrit July 2020

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Change in coreboot[master]: ec/google/chromeec: Add i2c_tunnel device under Chrome EC
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40515 ) Change subject: ec/google/chromeec: Add i2c_tunnel device under Chrome EC ...................................................................... ec/google/chromeec: Add i2c_tunnel device under Chrome EC This change enables support for generating ACPI nodes for I2C tunnel for any device that is sitting behind the Chrome EC. It accepts a config "remote_bus" which allows mainboard to configure the id of the remote bus that is being tunneled. BUG=b:154290952 BRANCH=None TEST=Verified that SSDT node for I2C tunnel behind Chrome EC is generated correctly. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/i2c_tunnel/Kconfig A src/ec/google/chromeec/i2c_tunnel/Makefile.inc A src/ec/google/chromeec/i2c_tunnel/chip.h A src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c 6 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/40515/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 554677c..1b269ec 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -1,3 +1,6 @@ + +source "src/ec/google/chromeec/*/Kconfig" + config EC_GOOGLE_CHROMEEC bool select EC_SUPPORTS_DPTF_TEVT diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 590b131..b11f5c8 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,7 @@ ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y) +subdirs-y += i2c_tunnel + bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/i2c_tunnel/Kconfig b/src/ec/google/chromeec/i2c_tunnel/Kconfig new file mode 100644 index 0000000..c90f0d1 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Kconfig @@ -0,0 +1,6 @@ +config EC_GOOGLE_CHROMEEC_I2C_TUNNEL + bool + depends on EC_GOOGLE_CHROMEEC && HAVE_ACPI_TABLES + help + This enables the crosec i2c tunnel driver that is required to fill the + SSDT nodes for i2c tunnel used by the mainboard. diff --git a/src/ec/google/chromeec/i2c_tunnel/Makefile.inc b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc new file mode 100644 index 0000000..85e0fba --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C_TUNNEL) += i2c_tunnel.c diff --git a/src/ec/google/chromeec/i2c_tunnel/chip.h b/src/ec/google/chromeec/i2c_tunnel/chip.h new file mode 100644 index 0000000..070a59a --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ +#define __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ + +#include <arch/acpi_device.h> + +struct ec_google_chromeec_i2c_tunnel_config { + /* ACPI device name */ + const char *name; + /* ACPI _UID */ + int uid; + /* EC bus number we tunnel to on the other side. */ + int remote_bus; +}; + +#endif /* __EC_GOOGLE_CHROMEEC_I2C_TUNNEL__ */ diff --git a/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c new file mode 100644 index 0000000..764f589 --- /dev/null +++ b/src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <string.h> +#include "chip.h" + +#define CROS_EC_I2C_TUNNEL_HID "GOOG0012" +#define CROS_EC_I2C_TUNNEL_DDN "Cros EC I2C Tunnel" + +static void crosec_i2c_tunnel_fill_ssdt(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + struct acpi_dp *dsd; + + if (!dev->enabled || !scope || !cfg) + return; + + acpigen_write_scope(scope); + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", CROS_EC_I2C_TUNNEL_HID); + acpigen_write_name_integer("_UID", cfg->uid); + acpigen_write_name_string("_DDN", CROS_EC_I2C_TUNNEL_DDN); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dsd, "google,remote-bus", cfg->remote_bus); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), CROS_EC_I2C_TUNNEL_DDN, + dev_path(dev)); +} + +static const char *crosec_i2c_tunnel_acpi_name(const struct device *dev) +{ + struct ec_google_chromeec_i2c_tunnel_config *cfg = dev->chip_info; + static char name[5]; + + if (cfg->name) + return cfg->name; + + snprintf(name, sizeof(name), "IT%02.2X", dev->path.generic.id); + name[4] = '\0'; + return name; +} + +static struct device_operations crosec_i2c_tunnel_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = crosec_i2c_tunnel_acpi_name, + .acpi_fill_ssdt_generator = crosec_i2c_tunnel_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void crosec_i2c_tunnel_enable(struct device *dev) +{ + dev->ops = &crosec_i2c_tunnel_ops; +} + +struct chip_operations ec_google_chromeec_i2c_tunnel_ops = { + CHIP_NAME("CrosEC I2C Tunnel Device") + .enable_dev = crosec_i2c_tunnel_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/40515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc0ec3725d7f1d20bcb5cb43a0a23aac72bf4eb Gerrit-Change-Number: 40515 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm: Enable SMM support for Xeon-SP
by Jonathan Zhang (Code Review) 02 Jul '20

02 Jul '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41829 ) Change subject: cpu/x86/smm: Enable SMM support for Xeon-SP ...................................................................... Patch Set 7: (7 comments) https://review.coreboot.org/c/coreboot/+/41829/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/41829/7//COMMIT_MSG@9 PS7, Line 9: Xeon-SP a skylake based system has 36 CPU threads (18 cores). Current coreboot Skylake Scalable Process can have 36 cpu threads (18 cores). https://review.coreboot.org/c/coreboot/+/41829/7/src/cpu/x86/mp_init.c File src/cpu/x86/mp_init.c: https://review.coreboot.org/c/coreboot/+/41829/7/src/cpu/x86/mp_init.c@541 PS7, Line 541: mdelay(1); This will add to boot time. Let's find out which MP record needs such added delay, when SMM is enabled. https://review.coreboot.org/c/coreboot/+/41829/7/src/cpu/x86/smm/smm_module… File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/41829/7/src/cpu/x86/smm/smm_module… PS7, Line 354: printk(BIOS_INFO, "%s : not enough stacks\n", __func__); The error conditions should be printk'ed as BIOS_ERR https://review.coreboot.org/c/coreboot/+/41829/7/src/cpu/x86/smm/smm_module… PS7, Line 612: "%s : increase SMM_CODE_SEGMENT_SIZE\n", __func__); print out handler_size will help to know to increase SMM_CODE_SEGMENT_SIZE https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/Make… File src/soc/intel/xeon_sp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/Make… PS7, Line 11: ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c The xeon_sp related changes should be made into a separate patch. https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/smmr… File src/soc/intel/xeon_sp/smmrelocate.c: https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/smmr… PS7, Line 106: * BSP to do * the final move. For APs, a relocation handler always There is an extra '*' https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/unco… File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/41829/7/src/soc/intel/xeon_sp/unco… PS7, Line 290: void smm_region(uintptr_t *start, size_t *size) Add an empty line above. -- To view, visit https://review.coreboot.org/c/coreboot/+/41829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78bd74c11ca42fb430f63711b5ec87d4bfe6ca2a Gerrit-Change-Number: 41829 Gerrit-PatchSet: 7 Gerrit-Owner: Rocky Phagura Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Eugene Myers <cedarhouse(a)comcast.net> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 Jul 2020 22:48:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42874 ) Change subject: mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL ...................................................................... mb/google/kahlee: Do not enable SCI for H1_PCH_INT_ODL H1 is not a wake source and hence there is no need to configure SCI GEVENT for it. This change drops PAD_SCI() configuration for GPIO_9 i.e. H1_PCH_INT_ODL. BUG=b:159944426 Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42874/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index abdcb0d..6d8dd52 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -20,7 +20,6 @@ /* GPIO_9 - H1_PCH_INT_ODL, SCI */ PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), - PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), /* GPIO_15 - EC_IN_RW_OD */ PAD_GPI(GPIO_15, PULL_UP), -- To view, visit https://review.coreboot.org/c/coreboot/+/42874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec2285b76f9c5fa1b4b1be15128fea316fa04555 Gerrit-Change-Number: 42874 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different ...
by Christian Walter (Code Review) 02 Jul '20

02 Jul '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41527 ) Change subject: mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configs ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/41527/20/src/mainboard/ocp/deltala… File src/mainboard/ocp/deltalake/romstage.c: https://review.coreboot.org/c/coreboot/+/41527/20/src/mainboard/ocp/deltala… PS20, Line 18: mupd->FspmConfig.IioConfigIOU2[0] = IIO_BIFURCATE_xxxxxxxx; : mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxx16; : mupd->FspmConfig.IioConfigIOU4[0] = IIO_BIFURCATE_xxxxxxxx; This changed? -- To view, visit https://review.coreboot.org/c/coreboot/+/41527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Gerrit-Change-Number: 41527 Gerrit-PatchSet: 20 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 02 Jul 2020 20:37:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp: remove sonorapass
by Jonathan Zhang (Code Review) 02 Jul '20

02 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42948 ) Change subject: mb/ocp: remove sonorapass ...................................................................... mb/ocp: remove sonorapass Sonora Pass server program was terminated. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 --- D src/mainboard/ocp/sonorapass/Kconfig D src/mainboard/ocp/sonorapass/Kconfig.name D src/mainboard/ocp/sonorapass/Makefile.inc D src/mainboard/ocp/sonorapass/acpi/platform.asl D src/mainboard/ocp/sonorapass/board.fmd D src/mainboard/ocp/sonorapass/board_info.txt D src/mainboard/ocp/sonorapass/bootblock.c D src/mainboard/ocp/sonorapass/devicetree.cb D src/mainboard/ocp/sonorapass/dsdt.asl D src/mainboard/ocp/sonorapass/romstage.c 10 files changed, 0 insertions(+), 283 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42948/1 diff --git a/src/mainboard/ocp/sonorapass/Kconfig b/src/mainboard/ocp/sonorapass/Kconfig deleted file mode 100644 index 55c144b..0000000 --- a/src/mainboard/ocp/sonorapass/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_OCP_SONORAPASS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_65536 - select MAINBOARD_USES_FSP2_0 - select IPMI_KCS - select SOC_INTEL_COOPERLAKE_SP - select SUPERIO_ASPEED_AST2400 - select HAVE_ACPI_TABLES - -config MAINBOARD_DIR - string - default "ocp/sonorapass" - -config MAINBOARD_PART_NUMBER - string - default "SonoraPass" - -config MAINBOARD_FAMILY - string - default "SonoraPass" - -config FMDFILE - string - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" - -endif diff --git a/src/mainboard/ocp/sonorapass/Kconfig.name b/src/mainboard/ocp/sonorapass/Kconfig.name deleted file mode 100644 index 90e7f3d..0000000 --- a/src/mainboard/ocp/sonorapass/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_OCP_SONORAPASS - bool "SonoraPass" diff --git a/src/mainboard/ocp/sonorapass/Makefile.inc b/src/mainboard/ocp/sonorapass/Makefile.inc deleted file mode 100644 index 9bd0173..0000000 --- a/src/mainboard/ocp/sonorapass/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -bootblock-y += bootblock.c -romstage-y += romstage.c diff --git a/src/mainboard/ocp/sonorapass/acpi/platform.asl b/src/mainboard/ocp/sonorapass/acpi/platform.asl deleted file mode 100644 index 9649592..0000000 --- a/src/mainboard/ocp/sonorapass/acpi/platform.asl +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -Name(\APC1, Zero) // IIO IOAPIC - -Name(\PICM, Zero) // IOAPIC/8259 - -Method(_PIC, 1) -{ - Store(Arg0, PICM) -} - -/* - * The _PTS method (Prepare To Sleep) is called before the OS is - * entering a sleep state. The sleep state number is passed in Arg0 - */ - -Method(_PTS,1) -{ -} - -/* The _WAK method is called on system wakeup */ - -Method(_WAK,1) -{ - Return(Package(){0,0}) -} diff --git a/src/mainboard/ocp/sonorapass/board.fmd b/src/mainboard/ocp/sonorapass/board.fmd deleted file mode 100644 index e28bcf0..0000000 --- a/src/mainboard/ocp/sonorapass/board.fmd +++ /dev/null @@ -1,10 +0,0 @@ -FLASH@0xfc000000 64M { - SI_ALL@0x0 0x2fd8000 { - SI_DESC@0x0 0x1000 - SI_GBE@0x1000 0x2000 - SI_ME@0x3000 0x2fc5000 - } - FMAP@0x03000000 0x800 - RW_MRC_CACHE@0x3000800 0x10000 - COREBOOT(CBFS)@0x3010800 -} diff --git a/src/mainboard/ocp/sonorapass/board_info.txt b/src/mainboard/ocp/sonorapass/board_info.txt deleted file mode 100644 index bbf3ee9..0000000 --- a/src/mainboard/ocp/sonorapass/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Board name: SonoraPass -Category: server -ROM protocol: SPI -ROM socketed: y -Flashrom support: y diff --git a/src/mainboard/ocp/sonorapass/bootblock.c b/src/mainboard/ocp/sonorapass/bootblock.c deleted file mode 100644 index e51073e..0000000 --- a/src/mainboard/ocp/sonorapass/bootblock.c +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <device/pnp_ops.h> -#include <intelblocks/lpc_lib.h> -#include <intelblocks/pcr.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> -#include <superio/aspeed/ast2400/ast2400.h> -#include <superio/aspeed/common/aspeed.h> - -#define ASPEED_CONFIG_INDEX 0x2E -#define ASPEED_CONFIG_DATA 0x2F - -static void enable_espi_lpc_io_windows(void) -{ - /* - * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, - * one is connected to debug header (SUART1) and another is used as SOL (SUART2). - * For that end it is wired into BMC virtual port. - */ - - /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); - /* LPC I/O enable: com1 and com2 */ - pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); - - /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ - pci_mmio_write_config32(PCH_DEV_LPC, 0x80, - (1 << 28) | (1 << 16) | (1 << 17) | (0 << 0) | (1 << 4)); -} - -static uint8_t com_to_ast_sio(uint8_t com) -{ - switch (com) { - case 0: - return AST2400_SUART1; - case 1: - return AST2400_SUART2; - case 2: - return AST2400_SUART3; - case 4: - return AST2400_SUART4; - default: - return AST2400_SUART1; - } -} - -void bootblock_mainboard_early_init(void) -{ - /* Open IO windows */ - enable_espi_lpc_io_windows(); - - /* Configure appropriate physical port of SuperIO chip off BMC */ - const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_CONFIG_INDEX, - com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); - aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); - - /* Port 80h direct to GPIO for LED display */ - const pnp_devfn_t gpio_dev = PNP_DEV(ASPEED_CONFIG_INDEX, AST2400_GPIO); - aspeed_enable_port80_direct_gpio(gpio_dev, GPIOH); - - /* Enable UART function pin*/ - aspeed_enable_uart_pin(serial_dev); -} diff --git a/src/mainboard/ocp/sonorapass/devicetree.cb b/src/mainboard/ocp/sonorapass/devicetree.cb deleted file mode 100644 index 05dac45..0000000 --- a/src/mainboard/ocp/sonorapass/devicetree.cb +++ /dev/null @@ -1,39 +0,0 @@ -chip soc/intel/xeon_sp/cpx - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host bridge - device pci 04.0 on end - device pci 04.1 on end - device pci 04.2 on end - device pci 04.3 on end - device pci 04.4 on end - device pci 04.5 on end - device pci 04.6 on end - device pci 04.7 on end - device pci 05.0 on end - device pci 05.2 on end - device pci 05.4 on end - device pci 08.0 on end - device pci 08.1 on end - device pci 08.2 on end - device pci 11.0 on end - device pci 11.1 on end - device pci 11.5 on end - device pci 14.0 on end - device pci 16.0 on end - device pci 16.1 on end - device pci 16.4 on end - device pci 17.0 on end - device pci 1c.0 on end - device pci 1c.4 on end - device pci 1f.2 on end - device pci 1f.4 on end - device pci 1f.5 on end - - device pci 1f.0 on # LPC/eSPI Interface - end - - end -end diff --git a/src/mainboard/ocp/sonorapass/dsdt.asl b/src/mainboard/ocp/sonorapass/dsdt.asl deleted file mode 100644 index 6f408b3..0000000 --- a/src/mainboard/ocp/sonorapass/dsdt.asl +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <soc/iomap.h> - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - #include "acpi/platform.asl" - - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) - Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) - - Scope (\_SB) - { - Device (PCI0) - { - #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> - #include <soc/intel/common/block/acpi/acpi/lpc.asl> - - } - - - Device (UNC0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x3F) - Method (_BBN, 0, NotSerialized) - { - Return (0xff) - } - - Method (_STA, 0, NotSerialized) - { - Return (0xf) - } - - Name (_CRS, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x00FF, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0001, // Length - ,, ) - }) - - } - } - -} diff --git a/src/mainboard/ocp/sonorapass/romstage.c b/src/mainboard/ocp/sonorapass/romstage.c deleted file mode 100644 index 4ea00b6..0000000 --- a/src/mainboard/ocp/sonorapass/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/romstage.h> - -void mainboard_memory_init_params(FSPM_UPD *mupd) -{ - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - void *start = (void *) m_cfg; - - // BoardId - *((uint8_t *) (start + 140)) = 0x1d; - // BoardTypeBitmask - *((uint32_t *) (start + 104)) = 0x11111111; - // DebugPrintLevel - *((uint8_t *) (start + 45)) = 8; - // KtiLinkSpeedMode - *((uint8_t *) (start + 64)) = 0; - // mmiolSize - *((uint32_t *) (start + 88)) = 0; - // mmiohBase - *((uint32_t *) (start + 92)) = 0x2000; - // KtiPrefetchEn - *((uint8_t *) (start + 53)) = 2; - // KtiFpgaEnable - *((uint8_t *) (start + 55)) = 0; - *((uint8_t *) (start + 56)) = 0; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5354ea1e912fd25f0ac9851edf0461413ad8bb21 Gerrit-Change-Number: 42948 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Michael Niewöhner (Code Review) 02 Jul '20

02 Jul '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 02 Jul 2020 20:04:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/pcengines/apu1/mainboard.c: fix apu1 serial number counting
by Piotr Kleinschmidt (Code Review) 02 Jul '20

02 Jul '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42512 ) Change subject: mb/pcengines/apu1/mainboard.c: fix apu1 serial number counting ...................................................................... mb/pcengines/apu1/mainboard.c: fix apu1 serial number counting PC Engines apu1 platform returns serial number value as -64. It is caused by faulty read of NIC's registers. This patch adjust NIC's bus number to valid value, so NIC's registers can be correctly read and hence NIC's MAC address. TEST=`dmidecode -t 2` command in Linux Debian Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b --- M src/mainboard/pcengines/apu1/mainboard.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42512/1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index a2a78c5..b297061 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -299,9 +299,18 @@ if (!dev) return serial; + /* FIXME: dev->bus->secondary has 0x100 value, while it should + * has 0x001 value, as it is on PCI bridge 1. + * Without this workaround pci_read_config32(dev, 0x18) returns + * incorrect data and hence platform's serial number is incorrect. + * However, shifting dev->bus->secondary 8 bits right is not + * reliable solution, as the problem probably lies earlier. + */ + dev->bus->secondary >>= 8; + /* Read in the last 3 bytes of NIC's MAC address. */ bar18 = pci_read_config32(dev, 0x18); - bar18 &= 0xFFFFFC00; + bar18 &= 0xFFFFFFF0; for (i = 3; i < 6; i++) { mac_addr <<= 8; mac_addr |= read8((u8 *)bar18 + i); -- To view, visit https://review.coreboot.org/c/coreboot/+/42512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b Gerrit-Change-Number: 42512 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: nb/intel/ironlake: Clean up code style (except raminit)
by Angel Pons (Code Review) 02 Jul '20

02 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42701 ) Change subject: nb/intel/ironlake: Clean up code style (except raminit) ...................................................................... nb/intel/ironlake: Clean up code style (except raminit) Reflow lines, correct coding style and align struct members, among other things. As raminit is very large, handle it on a follow-up. Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change. Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/ironlake/northbridge.c M src/northbridge/intel/ironlake/romstage.c 4 files changed, 35 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42701/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 4f221bf..e6e9ace 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -31,8 +31,7 @@ /* halt timer */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, - DEFAULT_PMBASE | 0x60 | 0x06); + outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, "Setting up static northbridge registers..."); @@ -56,7 +55,7 @@ printk(BIOS_DEBUG, " done.\n"); } -static void early_cpu_init (void) +static void early_cpu_init(void) { msr_t m; @@ -121,8 +120,7 @@ elog_boot_notify(s3_resume); /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, - DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); early_cpu_init(); @@ -132,7 +130,7 @@ /* Magic for S3 resume. Must be done early. */ if (s3_resume) { - MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; - MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; + MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; + MCHBAR32(0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; } } diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c index 8baccb2..7d08f31 100644 --- a/src/northbridge/intel/ironlake/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -152,8 +152,7 @@ gma_gfxinit(&lightup_ok); /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, - "$VBT IRONLAKE-MOBILE"); + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); } else { /* PCI Init, will run VBIOS */ pci_dev_init(dev); @@ -208,7 +207,7 @@ }; static const struct pci_driver gma __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 6b631b3..81bb0e7 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -19,16 +19,15 @@ int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = - pci_read_config16(pcidev_on_root(0, 0), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; + uint8_t stepping = cpuid_eax(1) & 0x0f; + uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); + bridge_revision_id = (bridge_id & 0xf0) | stepping; } return bridge_revision_id; } -/* Reserve everything between A segment and 1MB: +/* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) @@ -52,13 +51,12 @@ resource = new_resource(dev, index++); resource->base = (resource_t) 0xfed00000; resource->size = (resource_t) 0x00100000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; - mmio_resource(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); + + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); #if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, @@ -86,11 +84,11 @@ #endif static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, #if CONFIG(HAVE_ACPI_TABLES) - .acpi_name = northbridge_acpi_name, + .acpi_name = northbridge_acpi_name, #endif }; @@ -191,18 +189,18 @@ } static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt = generate_cpu_entries, - .ops_pci = &pci_dev_ops_pci, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt = generate_cpu_entries, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver mc_driver_ard __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Arrandale DRAM controller */ + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0044, /* Arrandale DRAM controller */ }; static struct device_operations cpu_bus_ops = { diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 4a335d8..e5ecafe 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -17,7 +17,8 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> -/* Platform has no romstage entry point under mainboard directory, +/* + * Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(void) @@ -59,7 +60,8 @@ intel_early_me_status(); if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but + /* + * Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ reg32 = inl(DEFAULT_PMBASE + 0x04); -- To view, visit https://review.coreboot.org/c/coreboot/+/42701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737 Gerrit-Change-Number: 42701 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/zork: Generate I2SM ACPI device at runtime
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42971 to review the following change. Change subject: mb/google/zork: Generate I2SM ACPI device at runtime ...................................................................... mb/google/zork: Generate I2SM ACPI device at runtime This change moves the generation of I2SM ACPI device from static asl file to runtime generation by ACP device driver. dmic_select_gpio is set to match version 3+ of Trembyle and Dalboz schematics. In order to maintain backward compatibility, dmic_select_gpio is updated at runtime using variant_audio_update for board versions that are prior to version 3 of reference schematics. The only difference from static generation is that the device I2SM is added under ACPD (i.e. ACP device) instead of CREC (Chrome EC device). It does not make any functional difference from the kernel perspective. BUG=b:157603026 TEST=Verified that the following device gets generated in SSDT: Scope (\_SB.PCI0.PBRA.ACPD) { Device (I2SM) { Name (_HID, "AMDI5682") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "I2S machine driver") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x000D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "dmic-gpios", Package (0x04) { \_SB.PCI0.PBRA.ACPD.I2SM, Zero, Zero, Zero } } } }) } } Verified audio via speakers and mic input. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> --- M src/mainboard/google/zork/mainboard.c M src/mainboard/google/zork/variants/baseboard/Makefile.inc M src/mainboard/google/zork/variants/baseboard/devicetree.cb M src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/zork/variants/baseboard/ramstage_common.c 6 files changed, 42 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/42971/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 283f0e0..f295271 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -132,6 +132,12 @@ override_num_gpios); } +static void mainboard_devtree_update(void) +{ + variant_audio_update(); + variant_devtree_update(); +} + static void mainboard_init(void *chip_info) { const struct sci_source *gpes; @@ -145,7 +151,7 @@ mainboard_configure_gpios(); /* Update DUT configuration */ - variant_devtree_update(); + mainboard_devtree_update(); /* * Some platforms use SCI not generated by a GPIO pin (event above 23). diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 7e4ccae..f01af31 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -23,6 +23,7 @@ ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += fsps_baseboard_dalboz.c ramstage-y += helpers.c ramstage-y += tpm_tis.c +ramstage-y += ramstage_common.c # Add OEM ID table ifeq ($(CONFIG_USE_OEM_BIN),y) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 3cc311b..9324749 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -16,6 +16,16 @@ register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the kernel driver. It does not + # really have a polarity since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and instead treats the GPIO + # selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + # Start : OPN Performance Configuration # (Configuratin that is common for all variants) # For the below fields, 0 indicates use SOC default diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl index ae5663e..b892570 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/audio.asl @@ -3,43 +3,3 @@ Scope (EC0.CREC) { #include <ec/google/chromeec/acpi/codec.asl> } - -/* machine driver */ -Device (I2SM) -{ - Name (_HID, "AMDI5682") - Name (_UID, 1) - Name (_DDN, "I2S machine Driver") - - Name (_CRS, ResourceTemplate () - { -#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ) - /* DMIC select GPIO */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, - IoRestrictionNone, "\\_SB.GPIO", 0x00, - ResourceConsumer,,) { 6 } -#else - /* DMIC select GPIO */ - GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, - IoRestrictionNone, "\\_SB.GPIO", 0x00, - ResourceConsumer,,) { 13 } -#endif - }) - /* Device-Specific Data */ - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () - { - Package () - { - "dmic-gpio", Package () { ^I2SM, 0, 0, 0 } - } - } - - }) - Method (_STA) - { - Return (0xF) - } -} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4f8f225..41b8290 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -28,6 +28,8 @@ void variant_romstage_entry(void); /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +/* Update audio configuration in devicetree during ramstage. */ +void variant_audio_update(void); /* Configure PCIe power and reset lines as per variant sequencing requirements. */ void variant_pcie_power_reset_configure(void); diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c new file mode 100644 index 0000000..6372af6 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> + +void variant_audio_update(void) +{ + struct soc_amd_picasso_config *cfg = config_of_soc(); + uint32_t board_version; + struct acpi_gpio *gpio = &cfg->dmic_select_gpio; + + if (!google_chromeec_cbi_get_board_version(&board_version) && + (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) + return; + + if (CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)) + gpio->pins[0] = GPIO_13; + else + gpio->pins[0] = GPIO_6; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1602c7f719eef9487ddea68e429d27408f9a76 Gerrit-Change-Number: 42971 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add support for generating I2S machine device
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42970 to review the following change. Change subject: soc/amd/picasso: Add support for generating I2S machine device ...................................................................... soc/amd/picasso: Add support for generating I2S machine device This change adds support in ACP device driver to generate I2S machine device(AMDI5682) in SSDT. It expects mainboard to provide chip config `dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the device. BUG=b:157603026 TEST=Verified that I2S machine device is correctly generated for trembyle. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> --- M src/soc/amd/picasso/acp.c M src/soc/amd/picasso/chip.h 2 files changed, 60 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42970/1 diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 1e871e9..5bc1e27 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -40,6 +42,60 @@ return "ACPD"; } +#define AMD_I2S_ACPI_NAME "I2SM" +#define AMD_I2S_ACPI_HID "AMDI5682" +#define AMD_I2S_ACPI_DESC "I2S machine driver" + +static void acp_fill_i2s_machine_dev(const struct device *dev) +{ + const char *scope = acpi_device_path(dev); + const struct soc_amd_picasso_config *cfg = config_of_soc(); + const struct acpi_gpio *dmic_select_gpio = &cfg->dmic_select_gpio; + struct acpi_dp *dsd; + + if (dmic_select_gpio->pin_count == 0) + return; + + acpigen_write_scope(scope); /* Scope */ + acpigen_write_device(AMD_I2S_ACPI_NAME); /* Device */ + acpigen_write_name_string("_HID", AMD_I2S_ACPI_HID); + acpigen_write_name_integer("_UID", 1); + acpigen_write_name_string("_DDN", AMD_I2S_ACPI_DESC); + + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_gpio(dmic_select_gpio); + acpigen_write_resourcetemplate_footer(); + + dsd = acpi_dp_new_table("_DSD"); + /* + * This GPIO is used to select DMIC0 or DMIC1 by the kernel driver. It does not + * really have a polarity since low and high control the selection of DMIC and + * hence does not have an active polarity. + * Kernel driver does not use the polarity field and instead treats the GPIO + * selection as follows: + * Set low (0) = Select DMIC0 + * Set high (1) = Select DMIC1 + */ + acpi_dp_add_gpio(dsd, "dmic-gpios", acpi_device_path_join(dev, AMD_I2S_ACPI_NAME), + 0, /* Index = 0 (There is a single GPIO entry in _CRS). */ + 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ + 0);/* Active low = 0 (Kernel driver does not use active polarity). */ + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static void acp_fill_ssdt(const struct device *dev) +{ + acpi_device_write_pci_dev(dev); + acp_fill_i2s_machine_dev(dev); +} + static struct device_operations acp_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -47,7 +103,7 @@ .init = init, .ops_pci = &pci_dev_ops_pci, .acpi_name = acp_acpi_name, - .acpi_fill_ssdt = acpi_device_write_pci_dev, + .acpi_fill_ssdt = acp_fill_ssdt, }; static const struct pci_driver acp_driver __pci_driver = { diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index f5fbe0f..f11f800 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -46,6 +46,9 @@ uint8_t flags; } irq_override[16]; + /* DMIC select GPIO for I2S machine driver AMDI5682 */ + struct acpi_gpio dmic_select_gpio; + /* Options for these are in src/arch/x86/include/acpi/acpi.h */ uint8_t fadt_pm_profile; uint16_t fadt_boot_arch; -- To view, visit https://review.coreboot.org/c/coreboot/+/42970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f Gerrit-Change-Number: 42970 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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