coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP...
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42969 to review the following change. Change subject: soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP device ...................................................................... soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP device This change adds support for .acpi_name and .acpi_fill_ssdt_generator device operations for the ACP device. BUG=b:157603026 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I84bb8150dada99def85b685535706aa609de227f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> --- M src/soc/amd/picasso/acp.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/42969/1 diff --git a/src/soc/amd/picasso/acp.c b/src/soc/amd/picasso/acp.c index 29b7521..1e871e9 100644 --- a/src/soc/amd/picasso/acp.c +++ b/src/soc/amd/picasso/acp.c @@ -35,12 +35,19 @@ sb_clk_output_48Mhz(); /* Internal connection to I2S */ } +static const char *acp_acpi_name(const struct device *dev) +{ + return "ACPD"; +} + static struct device_operations acp_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = init, .ops_pci = &pci_dev_ops_pci, + .acpi_name = acp_acpi_name, + .acpi_fill_ssdt = acpi_device_write_pci_dev, }; static const struct pci_driver acp_driver __pci_driver = { -- To view, visit https://review.coreboot.org/c/coreboot/+/42969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bb8150dada99def85b685535706aa609de227f Gerrit-Change-Number: 42969 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi_device: Replace polarity with active_low in acpi_gpio for GpioIo
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42968 ) Change subject: acpi_device: Replace polarity with active_low in acpi_gpio for GpioIo ...................................................................... acpi_device: Replace polarity with active_low in acpi_gpio for GpioIo As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the corresponding GPIO should be treated as active low. Thus, if GPIO has active high polarity or if it does not have any polarity associated with it, then the `active_low` argument is supposed to be set to 0. Having a `polarity` field in acpi_gpio seems confusing because GPIOs might not always have polarity associated with them. Example, in case of DMIC-select GPIO where 0 means select DMIC0 and 1 means select DMIC1, there is no polarity associated with the GPIO. Thus, it would be clearer for mainboard to use macros without having to specify a particular polarity. In order to enable mainboards to provide GPIO information without polarity for GpioIo usage, this change also adds `ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros. BUG=b:157603026 Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/acpi/acpigen.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/max98357a/max98357a.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/rt5663/rt5663.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/acpi/usb_acpi.c M src/include/acpi/acpi_device.h 9 files changed, 40 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42968/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index efc5a16..fc6da1b 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1800,15 +1800,15 @@ */ int acpigen_enable_tx_gpio(struct acpi_gpio *gpio) { - if (gpio->polarity == ACPI_GPIO_ACTIVE_HIGH) - return acpigen_soc_set_tx_gpio(gpio->pins[0]); - else + if (gpio->active_low) return acpigen_soc_clear_tx_gpio(gpio->pins[0]); + else + return acpigen_soc_set_tx_gpio(gpio->pins[0]); } int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) { - if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + if (gpio->active_low) return acpigen_soc_set_tx_gpio(gpio->pins[0]); else return acpigen_soc_clear_tx_gpio(gpio->pins[0]); @@ -1818,7 +1818,7 @@ { acpigen_soc_read_rx_gpio(gpio->pins[0]); - if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + if (gpio->active_low) acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } @@ -1826,7 +1826,7 @@ { acpigen_soc_get_tx_gpio(gpio->pins[0]); - if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW) + if (gpio->active_low) acpigen_write_xor(LOCAL0_OP, 1, LOCAL0_OP); } diff --git a/src/drivers/generic/gpio_keys/gpio_keys.c b/src/drivers/generic/gpio_keys/gpio_keys.c index f9d7187..80ac407 100644 --- a/src/drivers/generic/gpio_keys/gpio_keys.c +++ b/src/drivers/generic/gpio_keys/gpio_keys.c @@ -43,7 +43,7 @@ acpi_dp_add_integer(dsd, "debounce-interval", key->debounce_interval); acpi_dp_add_gpio(dsd, "gpios", parent_path, 0, 0, - config->gpio.polarity); + config->gpio.active_low); return dsd; } diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c index 575548b..44f8802 100644 --- a/src/drivers/generic/max98357a/max98357a.c +++ b/src/drivers/generic/max98357a/max98357a.c @@ -51,7 +51,7 @@ path = acpi_device_path(dev); dp = acpi_dp_new_table("_DSD"); acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, - config->sdmode_gpio.polarity); + config->sdmode_gpio.active_low); acpi_dp_add_integer(dp, "sdmode-delay", config->sdmode_delay); acpi_dp_write(dp); diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 5893a6f..18fd55c 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -114,16 +114,15 @@ if (irq_gpio_index != -1) acpi_dp_add_gpio(dsd, "irq-gpios", path, irq_gpio_index, 0, - config->irq_gpio.polarity == - ACPI_GPIO_ACTIVE_LOW); + config->irq_gpio.active_low); if (reset_gpio_index != -1) acpi_dp_add_gpio(dsd, "reset-gpios", path, reset_gpio_index, 0, - config->reset_gpio.polarity); + config->reset_gpio.active_low); if (enable_gpio_index != -1) acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, - config->enable_gpio.polarity); + config->enable_gpio.active_low); /* Add generic property list */ acpi_dp_add_property_list(dsd, config->property_list, config->property_count); diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index da12a4d..272cf78 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -53,7 +53,7 @@ dp = acpi_dp_new_table("_DSD"); if (config->irq_gpio.pin_count) acpi_dp_add_gpio(dp, "irq-gpios", acpi_device_path(dev), 0, 0, - config->irq_gpio.polarity == ACPI_GPIO_ACTIVE_LOW); + config->irq_gpio.active_low); RT5663_DP_INT("dc_offset_l_manual", config->dc_offset_l_manual); RT5663_DP_INT("dc_offset_r_manual", config->dc_offset_r_manual); RT5663_DP_INT("dc_offset_l_manual_mic", config->dc_offset_l_manual_mic); diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 4127f9a..c0e776e 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -139,15 +139,15 @@ if (irq_gpio_index >= 0) acpi_dp_add_gpio(dsd, "irq-gpios", path, irq_gpio_index, 0, - config->irq_gpio.polarity); + config->irq_gpio.active_low); if (reset_gpio_index >= 0) acpi_dp_add_gpio(dsd, "reset-gpios", path, reset_gpio_index, 0, - config->reset_gpio.polarity); + config->reset_gpio.active_low); if (enable_gpio_index >= 0) acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, - config->enable_gpio.polarity); + config->enable_gpio.active_low); acpi_dp_write(dsd); } diff --git a/src/drivers/uart/acpi/acpi.c b/src/drivers/uart/acpi/acpi.c index 9b4d1fa..f9d9d8f 100644 --- a/src/drivers/uart/acpi/acpi.c +++ b/src/drivers/uart/acpi/acpi.c @@ -103,15 +103,15 @@ if (irq_gpio_index >= 0) acpi_dp_add_gpio(dsd, "irq-gpios", path, irq_gpio_index, 0, - config->irq_gpio.polarity); + config->irq_gpio.active_low); if (reset_gpio_index >= 0) acpi_dp_add_gpio(dsd, "reset-gpios", path, reset_gpio_index, 0, - config->reset_gpio.polarity); + config->reset_gpio.active_low); if (enable_gpio_index >= 0) acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, - config->enable_gpio.polarity); + config->enable_gpio.active_low); acpi_dp_write(dsd); } diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index e136df0..d33b7de 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -57,7 +57,7 @@ dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0, - config->reset_gpio.polarity); + config->reset_gpio.active_low); acpi_dp_write(dsd); } diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index e01b6fd..6287ba1 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -158,11 +158,6 @@ ACPI_GPIO_IO_RESTRICT_PRESERVE }; -enum acpi_gpio_polarity { - ACPI_GPIO_ACTIVE_HIGH = 0, - ACPI_GPIO_ACTIVE_LOW = 1, -}; - #define ACPI_GPIO_REVISION_ID 1 #define ACPI_GPIO_MAX_PINS 8 @@ -182,37 +177,43 @@ uint16_t output_drive_strength; /* 1/100 mA */ int io_shared; enum acpi_gpio_io_restrict io_restrict; - enum acpi_gpio_polarity polarity; + /* + * As per ACPI spec, GpioIo does not have any polarity associated with it. Linux kernel + * uses `active_low` argument within GPIO _DSD property to allow BIOS to indicate if the + * corresponding GPIO should be treated as active low. Thus, if the GPIO has active high + * polarity or if it does not have any polarity, then the `active_low` argument is + * supposed to be set to 0. + * + * Reference: + * https://www.kernel.org/doc/html/latest/firmware-guide/acpi/gpio-properties.… + */ + bool active_low; }; /* GpioIo-related macros */ -#define ACPI_GPIO_CFG(_gpio, _io_restrict, _polarity) { \ +#define ACPI_GPIO_CFG(_gpio, _io_restrict, _active_low) { \ .type = ACPI_GPIO_TYPE_IO, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ .io_restrict = _io_restrict, \ - .polarity = _polarity, \ + .active_low = _active_low, \ .pin_count = 1, \ .pins = { (_gpio) } } /* Basic output GPIO with default pull settings */ -#define ACPI_GPIO_OUTPUT_CFG(gpio, polarity) \ - ACPI_GPIO_CFG(gpio, ACPI_GPIO_IO_RESTRICT_OUTPUT, polarity) +#define ACPI_GPIO_OUTPUT_CFG(gpio, active_low) \ + ACPI_GPIO_CFG(gpio, ACPI_GPIO_IO_RESTRICT_OUTPUT, active_low) -#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) \ - ACPI_GPIO_OUTPUT_CFG(gpio, ACPI_GPIO_ACTIVE_HIGH) - -#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) \ - ACPI_GPIO_OUTPUT_CFG(gpio, ACPI_GPIO_ACTIVE_LOW) +#define ACPI_GPIO_OUTPUT(gpio) ACPI_GPIO_OUTPUT_CFG(gpio, 0) +#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) ACPI_GPIO_OUTPUT_CFG(gpio, 0) +#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) ACPI_GPIO_OUTPUT_CFG(gpio, 1) /* Basic input GPIO with default pull settings */ #define ACPI_GPIO_INPUT_CFG(gpio, polarity) \ ACPI_GPIO_CFG(gpio, ACPI_GPIO_IO_RESTRICT_INPUT, polarity) -#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) \ - ACPI_GPIO_INPUT_CFG(gpio, ACPI_GPIO_ACTIVE_HIGH) - -#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) \ - ACPI_GPIO_INPUT_CFG(gpio, ACPI_GPIO_ACTIVE_LOW) +#define ACPI_GPIO_INPUT(gpio) ACPI_GPIO_INPUT_CFG(gpio, 0) +#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) ACPI_GPIO_INPUT_CFG(gpio, 0) +#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) ACPI_GPIO_INPUT_CFG(gpio, 1) /* GpioInt-related macros */ #define ACPI_GPIO_IRQ_CFG(_gpio, _mode, _polarity, _wake) { \ -- To view, visit https://review.coreboot.org/c/coreboot/+/42968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93 Gerrit-Change-Number: 42968 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi_device: Add helper macros for setting acpi_gpio fields
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42967 ) Change subject: acpi_device: Add helper macros for setting acpi_gpio fields ...................................................................... acpi_device: Add helper macros for setting acpi_gpio fields This change adds helper macros for initializing acpi_gpio fields for GpioIo/GpioInt objects. This allows dropping some redundant code for each macro to set the structure fields. Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/include/acpi/acpi_device.h 1 file changed, 61 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42967/1 diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 8cf36e3..e01b6fd 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -185,134 +185,96 @@ enum acpi_gpio_polarity polarity; }; -/* Basic output GPIO with default pull settings */ -#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) { \ +/* GpioIo-related macros */ +#define ACPI_GPIO_CFG(_gpio, _io_restrict, _polarity) { \ .type = ACPI_GPIO_TYPE_IO, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ - .polarity = ACPI_GPIO_ACTIVE_HIGH, \ + .io_restrict = _io_restrict, \ + .polarity = _polarity, \ .pin_count = 1, \ - .pins = { (gpio) } } + .pins = { (_gpio) } } -#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_OUTPUT, \ - .polarity = ACPI_GPIO_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } +/* Basic output GPIO with default pull settings */ +#define ACPI_GPIO_OUTPUT_CFG(gpio, polarity) \ + ACPI_GPIO_CFG(gpio, ACPI_GPIO_IO_RESTRICT_OUTPUT, polarity) + +#define ACPI_GPIO_OUTPUT_ACTIVE_HIGH(gpio) \ + ACPI_GPIO_OUTPUT_CFG(gpio, ACPI_GPIO_ACTIVE_HIGH) + +#define ACPI_GPIO_OUTPUT_ACTIVE_LOW(gpio) \ + ACPI_GPIO_OUTPUT_CFG(gpio, ACPI_GPIO_ACTIVE_LOW) /* Basic input GPIO with default pull settings */ -#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ - .polarity = ACPI_GPIO_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_INPUT_CFG(gpio, polarity) \ + ACPI_GPIO_CFG(gpio, ACPI_GPIO_IO_RESTRICT_INPUT, polarity) -#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_IO, \ +#define ACPI_GPIO_INPUT_ACTIVE_HIGH(gpio) \ + ACPI_GPIO_INPUT_CFG(gpio, ACPI_GPIO_ACTIVE_HIGH) + +#define ACPI_GPIO_INPUT_ACTIVE_LOW(gpio) \ + ACPI_GPIO_INPUT_CFG(gpio, ACPI_GPIO_ACTIVE_LOW) + +/* GpioInt-related macros */ +#define ACPI_GPIO_IRQ_CFG(_gpio, _mode, _polarity, _wake) { \ + .type = ACPI_GPIO_TYPE_INTERRUPT, \ .pull = ACPI_GPIO_PULL_DEFAULT, \ - .io_restrict = ACPI_GPIO_IO_RESTRICT_INPUT, \ - .polarity = ACPI_GPIO_ACTIVE_LOW, \ + .irq.mode = _mode, \ + .irq.polarity = _polarity, \ + .irq.wake = _wake, \ .pin_count = 1, \ - .pins = { (gpio) } } + .pins = { (_gpio) } } + +#define ACPI_GPIO_IRQ_EDGE(gpio, polarity) \ + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, 0) + +#define ACPI_GPIO_IRQ_EDGE_WAKE(gpio, polarity) \ + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_EDGE_TRIGGERED, polarity, ACPI_IRQ_WAKE) + +#define ACPI_GPIO_IRQ_LEVEL(gpio, polarity) \ + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, 0) + +#define ACPI_GPIO_IRQ_LEVEL_WAKE(gpio, polarity) \ + ACPI_GPIO_IRQ_CFG(gpio, ACPI_IRQ_LEVEL_TRIGGERED, polarity, ACPI_IRQ_WAKE) /* Edge Triggered Active High GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_HIGH(gpio) \ + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_HIGH) /* Edge Triggered Active Low GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_LOW(gpio) \ + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_LOW) /* Edge Triggered Active Both GPIO interrupt */ -#define ACPI_GPIO_IRQ_EDGE_BOTH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_BOTH(gpio) \ + ACPI_GPIO_IRQ_EDGE(gpio, ACPI_IRQ_ACTIVE_BOTH) /* Edge Triggered Active High GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_HIGH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_HIGH_WAKE(gpio) \ + ACPI_GPIO_IRQ_EDGE_WAKE(gpio, ACPI_IRQ_ACTIVE_HIGH) /* Edge Triggered Active Low GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_LOW_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_LOW_WAKE(gpio) \ + ACPI_GPIO_IRQ_EDGE_WAKE(gpio, ACPI_IRQ_ACTIVE_LOW) /* Edge Triggered Active Both GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_EDGE_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_BOTH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_EDGE_BOTH_WAKE(gpio) \ + ACPI_GPIO_IRQ_EDGE_WAKE(gpio, ACPI_IRQ_ACTIVE_BOTH) /* Level Triggered Active High GPIO interrupt */ -#define ACPI_GPIO_IRQ_LEVEL_HIGH(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_LEVEL_HIGH(gpio) \ + ACPI_GPIO_IRQ_LEVEL(gpio, ACPI_IRQ_ACTIVE_HIGH) /* Level Triggered Active Low GPIO interrupt */ -#define ACPI_GPIO_IRQ_LEVEL_LOW(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_LEVEL_LOW(gpio) \ + ACPI_GPIO_IRQ_LEVEL(gpio, ACPI_IRQ_ACTIVE_LOW) /* Level Triggered Active High GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_LEVEL_HIGH_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_LEVEL_HIGH_WAKE(gpio) \ + ACPI_GPIO_IRQ_LEVEL_WAKE(gpio, ACPI_IRQ_ACTIVE_HIGH) /* Level Triggered Active Low GPIO interrupt with wake */ -#define ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(gpio) { \ - .type = ACPI_GPIO_TYPE_INTERRUPT, \ - .pull = ACPI_GPIO_PULL_DEFAULT, \ - .irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \ - .irq.polarity = ACPI_IRQ_ACTIVE_LOW, \ - .irq.wake = ACPI_IRQ_WAKE, \ - .pin_count = 1, \ - .pins = { (gpio) } } +#define ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(gpio) \ + ACPI_GPIO_IRQ_LEVEL_WAKE(gpio, ACPI_IRQ_ACTIVE_LOW) /* Write GpioIo() or GpioInt() descriptor to SSDT AML output */ void acpi_device_write_gpio(const struct acpi_gpio *gpio); -- To view, visit https://review.coreboot.org/c/coreboot/+/42967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0a655468759ed3035c6c1e8770e37f1275e344e Gerrit-Change-Number: 42967 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/generic/gpio_regulator: Drop unused driver for gpio_regulator
by Furquan Shaikh (Code Review) 02 Jul '20

02 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42966 ) Change subject: drivers/generic/gpio_regulator: Drop unused driver for gpio_regulator ...................................................................... drivers/generic/gpio_regulator: Drop unused driver for gpio_regulator Proposal for gpio_regulator usage in ACPI never got accepted upstream for Linux kernel. So, the gpio_regulator driver in coreboot remains unused. This change drops this unused driver. Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- D src/drivers/generic/gpio_regulator/Kconfig D src/drivers/generic/gpio_regulator/Makefile.inc D src/drivers/generic/gpio_regulator/chip.h D src/drivers/generic/gpio_regulator/gpio_regulator.c 4 files changed, 0 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/42966/1 diff --git a/src/drivers/generic/gpio_regulator/Kconfig b/src/drivers/generic/gpio_regulator/Kconfig deleted file mode 100644 index c4c83e4..0000000 --- a/src/drivers/generic/gpio_regulator/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config DRIVERS_GENERIC_GPIO_REGULATOR - bool - depends on HAVE_ACPI_TABLES diff --git a/src/drivers/generic/gpio_regulator/Makefile.inc b/src/drivers/generic/gpio_regulator/Makefile.inc deleted file mode 100644 index 232e65e..0000000 --- a/src/drivers/generic/gpio_regulator/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -ramstage-$(CONFIG_DRIVERS_GENERIC_GPIO_REGULATOR) += gpio_regulator.c diff --git a/src/drivers/generic/gpio_regulator/chip.h b/src/drivers/generic/gpio_regulator/chip.h deleted file mode 100644 index 4d9e3ce..0000000 --- a/src/drivers/generic/gpio_regulator/chip.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __DRIVERS_GENERIC_GPIO_REGULATOR_H__ -#define __DRIVERS_GENERIC_GPIO_REGULATOR_H__ - -#include <acpi/acpi_device.h> - -struct drivers_generic_gpio_regulator_config { - const char *name; - struct acpi_gpio gpio; - bool enabled_on_boot; -}; - -#endif /* __DRIVERS_GENERIC_GPIO_REGULATOR_H__ */ diff --git a/src/drivers/generic/gpio_regulator/gpio_regulator.c b/src/drivers/generic/gpio_regulator/gpio_regulator.c deleted file mode 100644 index be71b9d..0000000 --- a/src/drivers/generic/gpio_regulator/gpio_regulator.c +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi_device.h> -#include <acpi/acpigen.h> -#include <device/device.h> -#include <device/path.h> -#include <string.h> - -#include "chip.h" - -static void gpio_regulator_fill_ssdt_generator(const struct device *dev) -{ - struct drivers_generic_gpio_regulator_config *config = dev->chip_info; - const char *scope = acpi_device_scope(dev); - const char *path = acpi_device_path(dev); - struct acpi_dp *dsd; - - if (!dev->enabled || !scope || !path || !config->gpio.pin_count) - return; - - /* Device */ - acpigen_write_scope(scope); - acpigen_write_device(acpi_device_name(dev)); - - /* _HID is set to PRP0001 */ - acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID); - - /* Resources - _CRS */ - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - acpi_device_write_gpio(&config->gpio); - acpigen_write_resourcetemplate_footer(); - - /* DSD */ - dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_string(dsd, "compatible", "regulator-fixed"); - acpi_dp_add_string(dsd, "regulator-name", config->name); - acpi_dp_add_gpio(dsd, "gpio-gpios", path, 0, 0, config->gpio.polarity); - if (config->enabled_on_boot) - acpi_dp_add_string(dsd, "regulator-boot-on", "on"); - if (config->gpio.polarity == ACPI_GPIO_ACTIVE_HIGH) - acpi_dp_add_string(dsd, "enable-active-high", "on"); - acpi_dp_write(dsd); - - acpigen_pop_len(); /* Device */ - acpigen_pop_len(); /* Scope */ -} - -static const char *gpio_regulator_acpi_name(const struct device *dev) -{ - struct drivers_generic_gpio_regulator_config *config = dev->chip_info; - static char name[5]; - - snprintf(name, sizeof(name), "R%03.3X", config->gpio.pins[0]); - name[4] = '\0'; - - return name; -} - -static struct device_operations gpio_regulator_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .acpi_name = gpio_regulator_acpi_name, - .acpi_fill_ssdt = gpio_regulator_fill_ssdt_generator, -}; - -static void gpio_regulator_enable(struct device *dev) -{ - dev->ops = &gpio_regulator_ops; -} - -struct chip_operations drivers_generic_gpio_regulator_ops = { - CHIP_NAME("GPIO Regulator") - .enable_dev = gpio_regulator_enable -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/42966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7 Gerrit-Change-Number: 42966 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 02 Jul '20

02 Jul '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42733 ) Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... Patch Set 7: We have global <gpio.h> requesting <soc/gpio.h>. How should we utilise this with platforms having southbridge/ instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 Jul 2020 17:52:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[4.11_branch]: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a ...
by Philipp Deppenwiese (Code Review) 02 Jul '20

02 Jul '20

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42747 ) Change subject: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD variable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Gerrit-Change-Number: 42747 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 Jul 2020 17:08:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Add entry for src/soc/intel/xeon_sp
by Jonathan Zhang (Code Review) 02 Jul '20

02 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42946 ) Change subject: MAINTAINERS: Add entry for src/soc/intel/xeon_sp ...................................................................... MAINTAINERS: Add entry for src/soc/intel/xeon_sp Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ib8d16057e3882c50bdca454632a64227166016fd --- M MAINTAINERS 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42946/1 diff --git a/MAINTAINERS b/MAINTAINERS index dd98e6d..e1c16c9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -515,6 +515,18 @@ F: /src/soc/intel/braswell F: /src/vendorcode/intel/fsp/fsp1_1/braswell +INTEL Xeon Sacalable Processor Family +M: Jonathan Zhang <jonzhang(a)fb.com> +M: Reddy Chagam <anjaneya.chagam(a)intel.com> +M: Johnny Lin <Johnny_Lin(a)wiwynn.com> +M: Morgan Jang <Morgan_Jang(a)wiwynn.com> +M: Ryback Hung <<Ryback.Hung(a)quantatw.com> +M: Bryant Ou <Bryant.Ou(a)quantatw.com> +S: Supported +F: src/soc/intel/xeon_sp +F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp +F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp + ORPHANED ARM SOCS S: Orphaned F: src/cpu/armltd/ -- To view, visit https://review.coreboot.org/c/coreboot/+/42946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d16057e3882c50bdca454632a64227166016fd Gerrit-Change-Number: 42946 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: Add entry for mb/ocp/deltalake
by Jonathan Zhang (Code Review) 02 Jul '20

02 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42945 ) Change subject: MAINTAINERS: Add entry for mb/ocp/deltalake ...................................................................... MAINTAINERS: Add entry for mb/ocp/deltalake Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ib13ffac064c197c68de4ea7b04fc6ae024f5c099 --- M MAINTAINERS 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42945/1 diff --git a/MAINTAINERS b/MAINTAINERS index edd274b..dd98e6d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -294,6 +294,15 @@ F: src/mainboard/libretrend/lt1000 +OCP DELTALAKE MAINBOARD +M: Jonathan Zhang <jonzhang(a)fb.com> +M: Reddy Chagam <anjaneya.chagam(a)intel.com> +M: Johnny Lin <Johnny_Lin(a)wiwynn.com> +M: Morgan Jang <Morgan_Jang(a)wiwynn.com> +M: Ryback Hung <<Ryback.Hung(a)quantatw.com> +M: Bryant Ou <Bryant.Ou(a)quantatw.com> +S: Supported +F: src/mainboard/ocp/deltalake OCP TIOGAPASS MAINBOARD M: Jonathan Zhang <jonzhang(a)fb.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/42945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib13ffac064c197c68de4ea7b04fc6ae024f5c099 Gerrit-Change-Number: 42945 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: fix SPI bar resource usage
by Aaron Durbin (Code Review) 02 Jul '20

02 Jul '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42959 ) Change subject: soc/amd/common: fix SPI bar resource usage ...................................................................... soc/amd/common: fix SPI bar resource usage The ACPI code was not masking off the correct bits for publishing the SPI bar to the OS. It resulted in a dmesg messagelike: system 00:00: [mem 0xfec10002-0xfec11001] has been reserved And /proc/iomem entry fec10002-fec11001 : pnp 00:00 These addresses are wrong because they are including bits of a register that are not a part of the address. Moreover, the code does not publish the eSPI register area either. The eSPI registers live at 0x10000 added to the SPI bar. Lastly, both regions are less than a page so only report a page of usage for each. Stoney Ridge's SPI bar register defines the address as 31:6 while Picasso's SPI bar register defines the address as 31:8. Use Picasso's valid mask for both cases because no one is assigning addresses that are aligned to less than 256 bytes. With the fixes, dmesg reports: system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved And /proc/iomem indicates: fec10000-fec10fff : pnp 00:00 fec20000-fec20fff : pnp 00:00 BUG=b:160290629 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab --- M src/soc/amd/common/acpi/lpc.asl 1 file changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/42959/1 diff --git a/src/soc/amd/common/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl index 5f290c4..e4b0689 100644 --- a/src/soc/amd/common/acpi/lpc.asl +++ b/src/soc/amd/common/acpi/lpc.asl @@ -26,17 +26,25 @@ { Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address 0x00000000, // Address Base - 0x00000000, // Address Length + 0x00001000, // Address Length BAR0 // Descriptor Name ) + + Memory32Fixed(ReadWrite, // Setup for fixed resource location for eSPI base address + 0x00000000, // Address Base + 0x00001000, // Address Length + BAR1 // Descriptor Name + ) }) Method(_CRS,0,Serialized) { CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address - CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length - Store(BAR,SPIB) // SPI base address mapped - Store(0x1000,SPIL) // 4k space mapped + CreateDwordField(^CRS,^BAR1._BAS,ESPB) // Field to hold eSPI base address + And(BAR, 0xffffff00, Local0) + Store(Local0, SPIB) // SPI base address mapped + Add(Local0, 0x10000, Local1) + Store(Local1, ESPB) // eSPI base address mapped Return(CRS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab Gerrit-Change-Number: 42959 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Ronak Kanabar (Code Review) 02 Jul '20

02 Jul '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 02 Jul 2020 10:46:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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