coreboot-gerrit July 2020

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Change in coreboot[master]: nb/intel/ironlake/northbridge.c: Drop thunk functions
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42696 ) Change subject: nb/intel/ironlake/northbridge.c: Drop thunk functions ...................................................................... nb/intel/ironlake/northbridge.c: Drop thunk functions Just call the called function directly. Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 2 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42696/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index f53b03e..267baf7 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -147,13 +147,7 @@ add_fixed_resources(dev, 10); } -static void mc_set_resources(struct device *dev) -{ - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - -static void northbridge_dmi_init(struct device *dev) +static void northbridge_init(struct device *dev) { u32 reg32; @@ -200,11 +194,6 @@ DMIBAR32(0x88) = reg32; } -static void northbridge_init(struct device *dev) -{ - northbridge_dmi_init(dev); -} - /* Disable unused PEG devices based on devicetree before PCI enumeration */ static void ironlake_init(void *const chip_info) { @@ -229,7 +218,7 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, -- To view, visit https://review.coreboot.org/c/coreboot/+/42696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Gerrit-Change-Number: 42696 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Add support for passive USB-C daughterboard
by Tim Wawrzynczak (Code Review) 01 Jul '20

01 Jul '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42905 ) Change subject: mb/google/volteer: Add support for passive USB-C daughterboard ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… PS1, Line 159: device generic 1 on : probe DB_USB USB4_GEN2 : probe DB_USB USB3_ACTIVE : probe DB_USB USB4_GEN3 : probe DB_USB USB3_NO_A : end : end : chip drivers/intel/pmc_mux/con : register "usb2_port_number" = "4" : register "usb3_port_number" = "2" : # SBU & HSL follow CC : device generic 1 on : probe DB_USB USB3_PASSIVE : end > I think it is ok for now, it is convenient to have the configuration all visible in the devicetree. […] That would certainly be nice to have 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/42905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Gerrit-Change-Number: 42905 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 21:34:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Duncan Laurie <dlaurie(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add support for passive USB-C daughterboard
by Duncan Laurie (Code Review) 01 Jul '20

01 Jul '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42905 ) Change subject: mb/google/volteer: Add support for passive USB-C daughterboard ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… PS1, Line 159: device generic 1 on : probe DB_USB USB4_GEN2 : probe DB_USB USB3_ACTIVE : probe DB_USB USB4_GEN3 : probe DB_USB USB3_NO_A : end : end : chip drivers/intel/pmc_mux/con : register "usb2_port_number" = "4" : register "usb3_port_number" = "2" : # SBU & HSL follow CC : device generic 1 on : probe DB_USB USB3_PASSIVE : end > You would need to get a few device references yes and fix up the values, roughly: […] I think it is ok for now, it is convenient to have the configuration all visible in the devicetree. It should be possible to make it so we can set a register to different values based on a probe rather than needing to duplicate devices, but that will take some sconfig changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/42905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Gerrit-Change-Number: 42905 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 21:10:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Aaron Durbin (Code Review) 01 Jul '20

01 Jul '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42427 ) Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/42427/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42427/6//COMMIT_MSG@7 PS6, Line 7: Pass GNVS as parameter to SMM module The passing is being done in a patch prior to this one. This patch is taking advantage of that work. Overall, the commit description could be better covering what exactly this is doing. -- To view, visit https://review.coreboot.org/c/coreboot/+/42427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 42427 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 20:46:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Pass GNVS as parameter to SMM module
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42427 ) Change subject: arch/x86: Pass GNVS as parameter to SMM module ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Gerrit-Change-Number: 42427 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 19:39:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42426 ) Change subject: sb/intel/i82801gx,ix,jx: Drop invalid GNVS update routine ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407b9b9fd44db027a62356e2470f6c39ed3bff49 Gerrit-Change-Number: 42426 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 19:36:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Benjamin Doron (Code Review) 01 Jul '20

01 Jul '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Jul 2020 19:35:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Move EC wake to happen in ramstage
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42952 ) Change subject: mb/google/zork: Move EC wake to happen in ramstage ...................................................................... mb/google/zork: Move EC wake to happen in ramstage Currently, EC wake signal (GPIO_24) is configured early on in romstage. However, there is no need for that since EC wake is not really required to be configured until ramstage. This change moves GPIO_24 configuration to happen in ramstage. BUG=b:159832123 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42952/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 75a7096..ea85819 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -12,8 +12,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -45,8 +43,6 @@ PAD_GPO(GPIO_5, LOW), /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_6, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -109,6 +105,8 @@ PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_UP), /* */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 4fbc4f0..60f997d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -12,8 +12,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EN_PWR_TOUCHPAD_PS2 - reset */ @@ -41,8 +39,6 @@ PAD_GPO(GPIO_5, LOW), /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_13, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EMMC_RESET - reset (default stuffing unused)*/ @@ -105,6 +101,8 @@ PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_UP), /* EN_PWR_FP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 Gerrit-Change-Number: 42952 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Fix pad configurations for wake signals
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42951 ) Change subject: mb/google/zork: Fix pad configurations for wake signals ...................................................................... mb/google/zork: Fix pad configurations for wake signals This change updates the pad configurations for wake lines as follows: 1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake using GPIO controller block. This is because pen eject signal is not dual routed and the trigger filtering is set by the kernel driver differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and instead has to fall back to using GPIO controller wake. 2. All other wake signals (EC, trackpad, fingerprint) need to be configured as SCI. This allows OS to enable/disable wake from these sources if required. Example: powerd disables wake from trackpad when in tablet mode. Hence, all other wake sources use SCI. BUG=b:159832123 TEST=Verified wake using pen eject and EC. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42951/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 711a94c..75a7096 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -13,7 +13,7 @@ /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -46,7 +46,7 @@ /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_6, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -80,7 +80,7 @@ /* PCIE_WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ - PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* EN_PWR_TOUCHPAD */ @@ -90,8 +90,7 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* EC_IN_RW_OD */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index f7e30ef..4fbc4f0 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -13,7 +13,7 @@ /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EN_PWR_TOUCHPAD_PS2 - reset */ @@ -42,7 +42,7 @@ /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_13, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EMMC_RESET - reset (default stuffing unused)*/ @@ -76,14 +76,13 @@ /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ - PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW), /* I2S_SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* FPMCU_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 Gerrit-Change-Number: 42951 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt
by Felix Held (Code Review) 01 Jul '20

01 Jul '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42846 ) Change subject: soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt ...................................................................... soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/root_complex.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42846/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..af347e7 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -135,6 +135,11 @@ { msr_t msr; + if (!device) { + printk(BIOS_ERR, "Error: %s device is NULL.\n", __func__); + return; + } + acpigen_write_scope(acpi_device_scope(device)); msr = rdmsr(TOP_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/42846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Gerrit-Change-Number: 42846 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020