coreboot-gerrit July 2020

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Change in coreboot[master]: mb/google/dedede: set tcc_offset value to 10
by Sumeet R Pawnikar (Code Review) 01 Jul '20

01 Jul '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42906 ) Change subject: mb/google/dedede: set tcc_offset value to 10 ...................................................................... mb/google/dedede: set tcc_offset value to 10 Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42906/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f95d123..32f6690 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,6 +155,8 @@ # Enable processor thermal control register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90C + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: -- To view, visit https://review.coreboot.org/c/coreboot/+/42906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Gerrit-Change-Number: 42906 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40278 to look at the new patch set (#6). Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... mb/purism/librem_whl: Add new board Librem Mini (WHL-U) Add new librem_whl baseboard and Librem Mini variant Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 --- A src/mainboard/purism/librem_whl/Kconfig A src/mainboard/purism/librem_whl/Kconfig.name A src/mainboard/purism/librem_whl/Makefile.inc A src/mainboard/purism/librem_whl/acpi/mainboard.asl A src/mainboard/purism/librem_whl/board_info.txt A src/mainboard/purism/librem_whl/devicetree.cb A src/mainboard/purism/librem_whl/dsdt.asl A src/mainboard/purism/librem_whl/ramstage.c A src/mainboard/purism/librem_whl/romstage.c A src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt A src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c A src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c A src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h 13 files changed, 687 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/40278/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 6 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 01 Jul '20

01 Jul '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/40278/5/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/Makefile.inc: https://review.coreboot.org/c/coreboot/+/40278/5/src/mainboard/purism/libre… PS5, Line 1: ## : ## : ## > ew, that was from the SPDX replacements. […] I looked at a handful of other Makefiles with the spdx header and they all had it, so figured I should to =P -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 18:27:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/boot: Jump to payload in protected mode
by Patrick Rudolph (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Krystian Hebel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30118 to look at the new patch set (#31). Change subject: arch/x86/boot: Jump to payload in protected mode ...................................................................... arch/x86/boot: Jump to payload in protected mode * On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Makefile.inc M src/arch/x86/boot.c A src/arch/x86/c_exit.S M src/include/assert.h M src/include/program_loading.h 6 files changed, 136 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30118/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 31 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Raul Rangel, Patrick Georgi, Martin Roth, Patrick Rudolph, Arthur Heymans, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30500 to look at the new patch set (#26). Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... arch/x86/postcar: Add x86_64 support * Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Makefile.inc M src/arch/x86/exit_car.S M src/arch/x86/gdt_init.S 4 files changed, 65 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30500/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 26 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/ironlake: Drop copy-pasted and unused macro
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42702 ) Change subject: nb/intel/ironlake: Drop copy-pasted and unused macro ...................................................................... nb/intel/ironlake: Drop copy-pasted and unused macro Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I78856707864563e392626a494f0e77eec9802002 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/finalize.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42702/1 diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 6e0844b..88bc98d 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -2,8 +2,6 @@ #include "ironlake.h" -#define PCI_DEV_SNB PCI_DEV(0, 0, 0) - void intel_ironlake_finalize_smm(void) { MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78856707864563e392626a494f0e77eec9802002 Gerrit-Change-Number: 42702 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Use `pci_update_config32()`
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42700 ) Change subject: nb/intel/ironlake: Use `pci_update_config32()` ...................................................................... nb/intel/ironlake: Use `pci_update_config32()` Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42700/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index acc76da..4f221bf 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -63,8 +63,7 @@ /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, - (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); + pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; -- To view, visit https://review.coreboot.org/c/coreboot/+/42700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Gerrit-Change-Number: 42700 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Simplify BAR handling
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42699 ) Change subject: nb/intel/ironlake: Simplify BAR handling ...................................................................... nb/intel/ironlake: Simplify BAR handling Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42699/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b6c5f0f..acc76da 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -38,15 +38,11 @@ printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, - (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, - (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); - + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, - (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); -- To view, visit https://review.coreboot.org/c/coreboot/+/42699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Gerrit-Change-Number: 42699 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake/ironlake.h: Clean up
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42698 ) Change subject: nb/intel/ironlake/ironlake.h: Clean up ...................................................................... nb/intel/ironlake/ironlake.h: Clean up Align values and drop copy-pasted, wrong and unused definitions. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h 1 file changed, 50 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42698/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 53efced..92ee76c 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -14,64 +14,47 @@ /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define D0F0_CAPID0 0xe0 -#define TSEG 0xac /* TSEG base */ +#define TSEG 0xac /* TSEG base */ /* * D1:F0 PEG */ -#define PEG_CAP 0xa2 -#define SLOTCAP 0xb4 -#define PEGLC 0xec -#define D1F0_VCCAP 0x104 -#define D1F0_VC0RCTL 0x114 +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 /* Chipset types */ -#define IRONLAKE_MOBILE 0 +#define IRONLAKE_MOBILE 0 #define IRONLAKE_DESKTOP 1 -#define IRONLAKE_SERVER 2 - -/* Device ID for SandyBridge and IvyBridge */ -#define BASE_REV_SNB 0x00 -#define BASE_REV_IVB 0x50 -#define BASE_REV_MASK 0x50 - -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ -#define SNB_STEP_D1 (BASE_REV_SNB + 6) -#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 (BASE_REV_IVB + 0) -#define IVB_STEP_B0 (BASE_REV_IVB + 2) -#define IVB_STEP_C0 (BASE_REV_IVB + 4) -#define IVB_STEP_K0 (BASE_REV_IVB + 5) -#define IVB_STEP_D0 (BASE_REV_IVB + 6) +#define IRONLAKE_SERVER 2 /* Northbridge BARs */ #ifndef __ACPI__ @@ -113,28 +96,25 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) \ - (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR16_AND_OR(x, and, or) \ - (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR32_AND_OR(x, and, or) \ - (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -163,9 +143,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -199,9 +179,6 @@ #ifndef __ASSEMBLER__ -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 - void intel_ironlake_finalize_smm(void); int bridge_silicon_revision(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Gerrit-Change-Number: 42698 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Drop copy-pasted and dead code
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42697 ) Change subject: nb/intel/ironlake: Drop copy-pasted and dead code ...................................................................... nb/intel/ironlake: Drop copy-pasted and dead code This function was copy-pasted, comments included, from Sandy Bridge. However, it is only called with 0x0044 as the northbridge's PCI ID. Therefore, `bridge_silicon_revision() & BASE_REV_MASK` will always evaluate to 0x40, which never equals `BASE_REV_SNB`, that is, 0x00. As the condition is always false, treat this code as dead and drop it. Following a similar reasoning, all direct comparisons against SNB steppings will always be true, because `bridge_silicon_revision()` returns at least 0x40 which is always larger than either `SNB_STEP_D0` or `SNB_STEP_D1`. So, drop all but the code path that is actually used. Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 3 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42697/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 267baf7..6b631b3 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -155,39 +155,13 @@ DMIBAR32(0x1c4) = 0xffffffff; DMIBAR32(0x1d0) = 0xffffffff; - /* Steps prior to DMI ASPM */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - reg32 = DMIBAR32(0x250); - reg32 &= ~((1 << 22) | (1 << 20)); - reg32 |= (1 << 21); - DMIBAR32(0x250) = reg32; - } - reg32 = DMIBAR32(0x238); reg32 |= (1 << 29); DMIBAR32(0x238) = reg32; - if (bridge_silicon_revision() >= SNB_STEP_D0) { - reg32 = DMIBAR32(0x1f8); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; - } else if (bridge_silicon_revision() >= SNB_STEP_D1) { - reg32 = DMIBAR32(0x1f8); - reg32 &= ~(1 << 26); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; - - reg32 = DMIBAR32(0x1fc); - reg32 |= (1 << 12) | (1 << 23); - DMIBAR32(0x1fc) = reg32; - } - - /* Enable ASPM on SNB link, should happen before PCH link */ - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - reg32 = DMIBAR32(0xd04); - reg32 |= (1 << 4); - DMIBAR32(0xd04) = reg32; - } + reg32 = DMIBAR32(0x1f8); + reg32 |= (1 << 16); + DMIBAR32(0x1f8) = reg32; reg32 = DMIBAR32(0x88); reg32 |= (1 << 1) | (1 << 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/42697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb Gerrit-Change-Number: 42697 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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