coreboot-gerrit July 2020

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Change in coreboot[master]: util: Compile vboot with CrOS parts disabled
by Patrick Georgi (Code Review) 01 Jul '20

01 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42853 ) Change subject: util: Compile vboot with CrOS parts disabled ...................................................................... util: Compile vboot with CrOS parts disabled With CL:2270096 merged, vboot can be built with CrOS specific support disabled. Use this feature so our build becomes more portable. Fixes https://ticket.coreboot.org/issues/145 Change-Id: Ice1955623779792af4d0b87872827f6fbe687e31 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/Makefile.inc M util/futility/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42853/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f38c825..f41724a 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -133,6 +133,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ + NOCROS=1 \ $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ hostlib diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index ee4ad05..d3f0441 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -7,6 +7,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ + NOCROS=1 \ $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ V=$(V) \ $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/42853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice1955623779792af4d0b87872827f6fbe687e31 Gerrit-Change-Number: 42853 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Don't set any TCC settings if offset is 0
by Tim Wawrzynczak (Code Review) 01 Jul '20

01 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42879 ) Change subject: soc/intel/common/cpu: Don't set any TCC settings if offset is 0 ...................................................................... soc/intel/common/cpu: Don't set any TCC settings if offset is 0 Many previous versions of this function would return early if tcc_offset is 0. This adds that logic back in. Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42879/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0ac8dda..e4ab664 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -260,15 +260,20 @@ const config_t *conf = config_of_soc(); msr_t msr; + if (!conf->tcc_offset) + return; + /* Set TCC activation offset */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & BIT(30)) && conf->tcc_offset) { + if ((msr.lo & BIT(30))) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); msr.lo |= (conf->tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ msr.lo &= ~0x7f; msr.lo |= 0xe6; /* setting 100ms thermal time window */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c Gerrit-Change-Number: 42879 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a ...
by insomniac (Code Review) 01 Jul '20

01 Jul '20

insomniac has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42747 ) Change subject: smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD variable ...................................................................... Patch Set 2: Code-Review+1 For context, this is a backport of https://review.coreboot.org/c/coreboot/+/42029/ to the 4_11 branch. LGTM -- To view, visit https://review.coreboot.org/c/coreboot/+/42747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30 Gerrit-Change-Number: 42747 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 13:22:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade IASL to version 20200214
by HAOUAS Elyes (Code Review) 01 Jul '20

01 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38907 ) Change subject: crossgcc: Upgrade IASL to version 20200214 ...................................................................... crossgcc: Upgrade IASL to version 20200214 Change: https://acpica.org/node/177 Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20200214_iasl.patch D util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38907/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 150e616..b1c930b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20200110 +IASL_VERSION=20200214 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200110_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200214_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20200110_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200214_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum deleted file mode 100644 index 48c0a2f..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50c163d965aa2cbee9a3a5d9244d1a0d16c06ec0 tarballs/acpica-unix2-20200110.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum new file mode 100644 index 0000000..97ef41e --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum @@ -0,0 +1 @@ +70f4e47590c82553287b2f301020352c59db7589 tarballs/acpica-unix2-20200214.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/38907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Gerrit-Change-Number: 38907 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/waddledee: Enable Audio
by Yong Zhi (Code Review) 01 Jul '20

01 Jul '20

Yong Zhi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41765 ) Change subject: mb/google/waddledee: Enable Audio ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… PS2, Line 61: 1 > Yong, Can you please explain this from driver/ACPI perspective? This 1 mapped to RT5682_JD1 which is correct: https://elixir.bootlin.com/linux/latest/source/sound/soc/codecs/rt5682.c#L1… -- To view, visit https://review.coreboot.org/c/coreboot/+/41765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Gerrit-Change-Number: 41765 Gerrit-PatchSet: 4 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirtika Ruchandani <kirtika(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: Yong Zhi <yong.zhi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 12:27:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Maulik V Vaghela (Code Review) 01 Jul '20

01 Jul '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42462 ) Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/42462/4/src/soc/intel/jasperlake/r… PS4, Line 84: SerialIoUartDebugMode > Ok, makes sense. If that is the case, can you just assign the devicetree config here […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 12:16:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
by Maulik V Vaghela (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Krishna P Bhat D, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42462 to look at the new patch set (#6). Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init ...................................................................... soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init Since coreboot is initializing uart for debug logs, fsp should not reinitialize it. Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot BUG=None BRANCH=None TEST=FSP is able to push debug logs on UART with this setting Cq-Depend: TBD Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42462/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/42462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07 Gerrit-Change-Number: 42462 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Refactor single GPIO programming
by Kyösti Mälkki (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42691 to look at the new patch set (#7). Change subject: soc/amd/common: Refactor single GPIO programming ...................................................................... soc/amd/common: Refactor single GPIO programming Make it clearer all the GPIO bank register programming parameters originate from the same soc_amd_gpio entry. Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 13 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/42691/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b Gerrit-Change-Number: 42691 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common: Complete ACPIMMIO GPIO bank separation
by Kyösti Mälkki (Code Review) 01 Jul '20

01 Jul '20

Hello build bot (Jenkins), Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42690 to look at the new patch set (#7). Change subject: soc/amd/common: Complete ACPIMMIO GPIO bank separation ...................................................................... soc/amd/common: Complete ACPIMMIO GPIO bank separation Remove references to separate gpio1 and gpio2 banks. Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 0 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42690/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] tigerlake: add TCC activation functionality
by Sumeet R Pawnikar (Code Review) 01 Jul '20

01 Jul '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41855 ) Change subject: [WIP] tigerlake: add TCC activation functionality ...................................................................... [WIP] tigerlake: add TCC activation functionality This enables to configure the Thermal Control Circuit (TCC) activation value to new value as tcc_offset in degree Celcius. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action before CPU temperature reaches maximum operating temperature TjMax value. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41855/1 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index f5870ec..a61e431 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -30,6 +30,26 @@ fsps_load(romstage_handoff_is_resume()); } +static void configure_thermal_target(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + /* Set TCC activation offset */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ + msr.lo &= ~0x7f; + msr.lo |= 0xe6; /* setting 100ms thermal time window */ + wrmsr(MSR_TEMPERATURE_TARGET, msr); +} + static void configure_isst(void) { config_t *conf = config_of_soc(); @@ -216,4 +236,7 @@ { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_thermal_target(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357..1aeddd6 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -205,6 +205,9 @@ /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; + /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/41855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Gerrit-Change-Number: 41855 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020