coreboot-gerrit July 2020

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Change in coreboot[master]: mb/google/waddledee: Enable Audio
by Maulik V Vaghela (Code Review) 01 Jul '20

01 Jul '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41765 ) Change subject: mb/google/waddledee: Enable Audio ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/waddledee/overridetree.cb: https://review.coreboot.org/c/coreboot/+/41765/2/src/mainboard/google/deded… PS2, Line 61: 1 > How is this 1 translate to HP_INT_ODL i.e. […] Yong, Can you please explain this from driver/ACPI perspective? -- To view, visit https://review.coreboot.org/c/coreboot/+/41765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Gerrit-Change-Number: 41765 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirtika Ruchandani <kirtika(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: Yong Zhi <yong.zhi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 11:41:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/waddledee: Enable Audio
by Maulik V Vaghela (Code Review) 01 Jul '20

01 Jul '20

Hello Furquan Shaikh, Uday M Bhat, Yong Zhi, Subrata Banik, Meera Ravindranath, Krishna P Bhat D, Aamir Bohra, Ronak Kanabar, Kirtika Ruchandani, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/41765 to look at the new patch set (#3). Change subject: mb/google/waddledee: Enable Audio ...................................................................... mb/google/waddledee: Enable Audio 1. Enable HDA Pci device in devicetree 2. Enable I2C4 in devicetree and fill ACPI information 3. Pass correct IRQ GPIO for headset jack BUG=None BRANCH=None TEST=Audio playback and recording works on Waddledee. Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/dedede/variants/waddledee/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/41765/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/41765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Gerrit-Change-Number: 41765 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirtika Ruchandani <kirtika(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Uday M Bhat Gerrit-Reviewer: Yong Zhi <yong.zhi(a)intel.com> Gerrit-CC: Marco Chen <marcochen(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: select PMC support on deltalake
by Tim Chu (Code Review) 01 Jul '20

01 Jul '20

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42963 ) Change subject: mb/ocp/deltalake: select PMC support on deltalake ...................................................................... mb/ocp/deltalake: select PMC support on deltalake Enable PMC support on Deltalake and change the state to S5 state when power is reapplied after power failure. TEST=build for Deltalake and enable CONFIG_POWER_STATE_OFF_AFTER_FAILURE in config table to override POWER_STATE_DEFAULT_ON_AFTER_FAILURE which is select in soc/intel/common/block/pmc/Kconfig Boot the system and check the last bit of GEN_PMCON_B is set to 1 through ITP with command: pch.pm_dump Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I35c029c0aa4b91aa5d5f168daea05a6217d42f81 --- M src/mainboard/ocp/deltalake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/42963/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 0f693d2..2a195a1 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -12,6 +12,10 @@ select IPMI_KCS_ROMSTAGE select IPMI_OCP select OCP_DMI + select REG_SCRIPT + select SOC_INTEL_COMMON_BLOCK_PMC + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select CPU_INTEL_COMMON_SMM config IPMI_KCS_REGISTER_SPACING int -- To view, visit https://review.coreboot.org/c/coreboot/+/42963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35c029c0aa4b91aa5d5f168daea05a6217d42f81 Gerrit-Change-Number: 42963 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad
by Johnny Li (Code Review) 01 Jul '20

01 Jul '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42956 ) Change subject: mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad ...................................................................... mb/google/volteer/variants/volteer : Tune I2C5 params for Trackpad This change updates scl_lcnt,scl_hcnt,scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:157999726 TEST= Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: Ia9c6159565fc5c28ccb3c3f9fb4b2838cde273a0 --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/42956/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 24b869c..7319047 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -161,5 +161,49 @@ end end end # PMC + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9c6159565fc5c28ccb3c3f9fb4b2838cde273a0 Gerrit-Change-Number: 42956 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194
by Karthik Ramasubramanian (Code Review) 01 Jul '20

01 Jul '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42471 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Gerrit-Change-Number: 42471 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 07:21:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Johnny Lin (Code Review) 01 Jul '20

01 Jul '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 52: (1 comment) https://review.coreboot.org/c/coreboot/+/40308/51/src/drivers/ocp/dmi/smbio… File src/drivers/ocp/dmi/smbios.c: https://review.coreboot.org/c/coreboot/+/40308/51/src/drivers/ocp/dmi/smbio… PS51, Line 176: *p+ > Why do we double null terminate here? I simply use the same smbios_add_string() in arch/x86/smbios.c https://review.coreboot.org/c/coreboot/+/42029/18/src/arch/x86/smbios.c#77 but removed the if condition at L98 because that doesn't allow me to add duplicate strings. From the SMBIOS Spec DSP0134 Version 3.0.0, section 6.1.3: "Each string is terminated with a null (00h) BYTE and the set of strings is terminated with an additional null (00h) BYTE." I think always adding two null bytes can be used for both terminating an individual string and a set of strings. -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 52 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 06:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194
by Ronak Kanabar (Code Review) 01 Jul '20

01 Jul '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42471 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/42471/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42471/1//COMMIT_MSG@14 PS1, Line 14: Cq-Depend: TBD > Nit: Leave a blank line between TEST and Cq-Depend lines. Move it immediately above Change-Id line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Gerrit-Change-Number: 42471 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 06:52:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194
by Ronak Kanabar (Code Review) 01 Jul '20

01 Jul '20

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42471 to look at the new patch set (#3). Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2194 The FSP-M/S headers added are generated as per FSP v2194. BUG=b:159193895 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: TBD Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 2 files changed, 4,452 insertions(+), 152 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/42471/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/42471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd84fdb0089bf8ea3f4440e89fdee7f11119751 Gerrit-Change-Number: 42471 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork: update G2 TS RST delay time
by Kevin Chiu (Code Review) 01 Jul '20

01 Jul '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42867 ) Change subject: mb/google/zork: update G2 TS RST delay time ...................................................................... mb/google/zork: update G2 TS RST delay time in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42867/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 18288ec..229469e 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -93,7 +93,7 @@ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.reset_delay_ms" = "1" + register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/42867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Gerrit-Change-Number: 42867 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/mainboard/prodrive/hermes/variants/baseboard: add support for sat...
by Jonas Löffelholz (Code Review) 01 Jul '20

01 Jul '20

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42804 ) Change subject: src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap ...................................................................... src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42804/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 3388239..c4be117 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -19,6 +19,15 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" + register "SataPortsHotPlug[0]" = "1" + register "SataPortsHotPlug[1]" = "1" + register "SataPortsHotPlug[2]" = "1" + register "SataPortsHotPlug[3]" = "1" + register "SataPortsHotPlug[4]" = "1" + register "SataPortsHotPlug[5]" = "1" + register "SataPortsHotPlug[6]" = "1" + register "SataPortsHotPlug[7]" = "1" + register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Gerrit-Change-Number: 42804 Gerrit-PatchSet: 1 Gerrit-Owner: Jonas Löffelholz Gerrit-MessageType: newchange

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coreboot-gerrit July 2020