coreboot-gerrit July 2020

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Change in coreboot[master]: src/mainboard/prodrive/hermes/variants/baseboard: add support for sat...
by Jonas Löffelholz (Code Review) 01 Jul '20

01 Jul '20

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42804 ) Change subject: src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap ...................................................................... src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42804/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 3388239..c4be117 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -19,6 +19,15 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" + register "SataPortsHotPlug[0]" = "1" + register "SataPortsHotPlug[1]" = "1" + register "SataPortsHotPlug[2]" = "1" + register "SataPortsHotPlug[3]" = "1" + register "SataPortsHotPlug[4]" = "1" + register "SataPortsHotPlug[5]" = "1" + register "SataPortsHotPlug[6]" = "1" + register "SataPortsHotPlug[7]" = "1" + register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Gerrit-Change-Number: 42804 Gerrit-PatchSet: 1 Gerrit-Owner: Jonas Löffelholz Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/intel/cannonlake: add support for sata hotswap
by Jonas Löffelholz (Code Review) 01 Jul '20

01 Jul '20

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42803 ) Change subject: src/soc/intel/cannonlake: add support for sata hotswap ...................................................................... src/soc/intel/cannonlake: add support for sata hotswap Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz(a)9elements.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3ebbc5e..ac523d8 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -147,6 +147,7 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; uint8_t SataPortsDevSlpResetConfig[8]; + uint8_t SataPortsHotPlug[8]; /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ uint8_t SlpS0WithGbeSupport; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a3b5588..c43d1b2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + #if CONFIG(SOC_INTEL_COMETLAKE) memcpy(params->SataPortsDevSlpResetConfig, config->SataPortsDevSlpResetConfig, -- To view, visit https://review.coreboot.org/c/coreboot/+/42803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Gerrit-Change-Number: 42803 Gerrit-PatchSet: 1 Gerrit-Owner: Jonas Löffelholz Gerrit-MessageType: newchange

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Change in coreboot[master]: 3rdparty/amd_blobs: Update Picasso PSP files
by Marshall Dawson (Code Review) 01 Jul '20

01 Jul '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42893 ) Change subject: 3rdparty/amd_blobs: Update Picasso PSP files ...................................................................... 3rdparty/amd_blobs: Update Picasso PSP files Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I752804919227c1522374b93e08abee13396b2679 --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42893/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 5d4d09e..1ac6d42 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 5d4d09e984578d129928b74cab78f78d214609e1 +Subproject commit 1ac6d42bf336af639ae849933cbb818e51b1ffd1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I752804919227c1522374b93e08abee13396b2679 Gerrit-Change-Number: 42893 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/skylake: Update ASL syntax in xhci.asl
by Edward O'Callaghan (Code Review) 01 Jul '20

01 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42898 ) Change subject: soc/intel/skylake: Update ASL syntax in xhci.asl ...................................................................... soc/intel/skylake: Update ASL syntax in xhci.asl Use some defines as well for clarity. Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 19 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42898/1 diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 5a877d4..2f5d8b2 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -1,5 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define PORTSCN_OFFSET 0x480 +#define PORTSCXUSB3_OFFSET 0x540 + +#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 +#define RO_BITS_OFF_MASK ~0x80FE0012 + /* * USB Port Wake Enable (UPWE) on usb attach/detach * Arg0 - Port Number @@ -8,8 +14,7 @@ */ Method (UPWE, 3, Serialized) { - /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ - Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + Local0 = Arg1 + ((Arg0 - 1) * 0x10) /* Map ((XMEM << 16) + Local0 in PSCR */ OperationRegion (PSCR, SystemMemory, @@ -18,16 +23,16 @@ { PSCT, 32, } - Store(PSCT, Local0) + Local0 = PSCT /* * And port status/control reg with RO and RWS bits * RO bits: 0, 2:3, 10:13, 24, 28:30 * RWS bits: 5:9, 14:16, 25:27 */ - And (Local0, ~0x80FE0012, Local0) + Local0 = Local0 & RO_BITS_OFF_MASK /* Set WCE and WDE bits */ - Or (Local0, 0x6000000, Local0) - Store(Local0, PSCT) + Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 } /* @@ -38,20 +43,19 @@ */ Method (UWES, 3, Serialized) { - Store (Arg0, Local0) + Local0 = Arg0 While (One) { FindSetRightBit (Local0, Local1) - If (LEqual (Local1, Zero)) { + If (Local1 == Zero) { Break } UPWE (Local1, Arg1, Arg2) /* * Clear the lowest set bit in Local0 since it was * processed. - * Local0 = Local0 & (Local0 - 1) */ - And (Local0, Subtract (Local0, 1), Local0) + Local0 = Local0 & (Local0 - 1) } } @@ -65,9 +69,9 @@ Method (_DSW, 3) { - Store (Arg0, PMEE) - UWES (And (\U2WE, 0x3FF), 0x480, XMEM) - UWES (And (\U3WE, 0x3F), 0x540, XMEM) + PMEE = Arg0 + UWES ((\U2WE & 0x3FF), PORTSCN_OFFSET, XMEM) + UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM) } Name (_S3D, 3) /* D3 supported in S3 */ @@ -221,11 +225,11 @@ // REV: Revision 0x02 for ACPI 5.0 CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + REV = 0x02 // VISI: Port visibility to user per port CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + VISI = Arg0 Return (PCKG) } -- To view, visit https://review.coreboot.org/c/coreboot/+/42898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Gerrit-Change-Number: 42898 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4
by John Zhao (Code Review) 01 Jul '20

01 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42821 ) Change subject: soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4 ...................................................................... soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4 This change adds Platform-Wide _OSC capabilities for native USB4 support. There is Engineering Change Request (ECR) with _OSC addition for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18 as native USB4 support. The OS sets this bit to indicate support for an OSPM-native USB4 Connection Manager which handles USB4 connection events and link management. The OS use the _OSC mechanism and the bit defined in this ECR to obtain configuration and connection management capabilities of USB4 connections. This change also fixs the byte index for the DWord-addressable field CDW3 from the capabilities buffer. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 39 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42821/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 3f51ecc..7434a54 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -139,29 +139,46 @@ Method (_OSC, 4, Serialized) { - /* - * Operating System Capabilities for USB4 - * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} - * Arg1: Revision ID = 1 - * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 - * Arg3: DWORD capabilities buffer: - * First DWORD: The standard definition bits are used to return errors. - * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. - * Third DWORD: OSPM control field for USB4. - * bit 0: USB tunneling - * bit 1: DisplayPort tunneling - * bit 2: PCIe tunneling - * bit 3: Inter-domain USB4 internet protocol - * bit 31:4: reserved - * Return: The platform acknowledges the capabilities buffer by returning - * a buffer of DWORD of the same length. Masked/Cleared bits in the - * control field indicate that the platform does not permit OSPM - * control of the respectively capabilities or features. - */ - Name (CTRL, 0) /* Control field value */ CreateDWordField (Arg3, 0, CDW1) - If (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { - CreateDWordField (Arg3, 2, CDW3) + If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) { + /* Platform-Wide _OSC Capabilities + * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities + * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4 + * support. The OS sets this bit to indicate support for an OSPM-native + * USB4 Connection Manager which handles USB4 connection events and + * link management. + */ + If (Arg1 != REVISION) { + CDW1 |= UNRECOGNIZED_REVISION + } + Return (Arg3) + } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { + /* + * Operating System Capabilities for USB4 + * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. + * Third DWORD: OSPM control field for USB4. + * bit 0: USB tunneling + * bit 1: DisplayPort tunneling + * bit 2: PCIe tunneling + * bit 3: Inter-domain USB4 internet protocol + * bit 31:4: reserved + * Return: The platform acknowledges the capabilities buffer by + * returning a buffer of DWORD of the same length. Masked/Cleared bits + * in the control field indicate that the platform does not permit OSPM + * control of the respectively capabilities or features. + */ + Name (CTRL, 0) /* Control field value */ + CreateDWordField (Arg3, 8, CDW3) CTRL = CDW3 If (Arg1 != REVISION_ID) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad Gerrit-Change-Number: 42821 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Fix a typo in tests/lib/Makefile.inc
by Anna Karas (Code Review) 01 Jul '20

01 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42312 ) Change subject: tests: Fix a typo in tests/lib/Makefile.inc ...................................................................... tests: Fix a typo in tests/lib/Makefile.inc Fix a typo in a comment in Makefile.inc. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I236b040a83700bcd34d99db61e5dad0ff7abb28c --- M tests/lib/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42312/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 565bb31..61f99bf 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -# object filest should be under build/tests/ build/test/src/ build/test/run/ +# object files should be under build/tests/ build/test/src/ build/test/run/ # two examples - first should be simply string.c, second should use -wrap tests-y += string-test -- To view, visit https://review.coreboot.org/c/coreboot/+/42312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I236b040a83700bcd34d99db61e5dad0ff7abb28c Gerrit-Change-Number: 42312 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: set GPIOs to wake-up from touchpad
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42726 to review the following change. Change subject: mb/google/zork: set GPIOs to wake-up from touchpad ...................................................................... mb/google/zork: set GPIOs to wake-up from touchpad This allows the system to wake from the touchpad if the touchpad is powered in S3. BUG=b:154676993 TEST=enter S3 with the follow-on patch and verify that the system can wake from S3. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I222f1de9a25a8aa24d56fde09a487cbf3737446f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Tested-by: Furquan Shaikh <furquan(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42726/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 50c842b..d8a3714 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -101,6 +101,7 @@ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_UP, EDGE_LOW, S3_S4_S5), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* EN_PWR_TOUCHPAD */ @@ -110,8 +111,8 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ PAD_GPI(GPIO_9, PULL_UP), + PAD_WAKE(GPIO_9, PULL_UP, EDGE_LOW, S3_S4_S5), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* EC_IN_RW_OD */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index d3f7ae3..bac5333 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -97,6 +97,7 @@ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_UP, EDGE_LOW, S3_S4_S5), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ @@ -107,8 +108,8 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ PAD_GPI(GPIO_9, PULL_UP), + PAD_WAKE(GPIO_9, PULL_UP, EDGE_LOW, S3_S4_S5), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* FPMCU_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222f1de9a25a8aa24d56fde09a487cbf3737446f Gerrit-Change-Number: 42726 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Kconfig: Fix warning
by Patrick Georgi (Code Review) 01 Jul '20

01 Jul '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42748 ) Change subject: Kconfig: Fix warning ...................................................................... Kconfig: Fix warning Add closing quotation mark to fix Kconfig warning. Change-Id: I75e8d23b81266553d7c40de7f52c6c03107c43de Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42748 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index f192776..eb85cd9 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -235,7 +235,7 @@ may result in a nonbooting coreboot.rom. config USE_QC_BLOBS - bool "Allow QC blobs repository (selecting this agrees to the license!) + bool "Allow QC blobs repository (selecting this agrees to the license!)" depends on USE_BLOBS help This draws in the qc_blobs repository, which contains binary files -- To view, visit https://review.coreboot.org/c/coreboot/+/42748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e8d23b81266553d7c40de7f52c6c03107c43de Gerrit-Change-Number: 42748 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ACPI GNVS: replace smm_get_gnvs() with gnvs()
by Kyösti Mälkki (Code Review) 01 Jul '20

01 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42849 ) Change subject: ACPI GNVS: replace smm_get_gnvs() with gnvs() ...................................................................... ACPI GNVS: replace smm_get_gnvs() with gnvs() Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Documentation/mainboard_io_trap_handler_sample.c M src/mainboard/getac/p470/smihandler.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard_smi.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/smihandler.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/smihandler.c 29 files changed, 98 insertions(+), 103 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42849/1 diff --git a/Documentation/mainboard_io_trap_handler_sample.c b/Documentation/mainboard_io_trap_handler_sample.c index 558e12f..78c3c69 100644 --- a/Documentation/mainboard_io_trap_handler_sample.c +++ b/Documentation/mainboard_io_trap_handler_sample.c @@ -20,7 +20,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; @@ -32,6 +32,6 @@ * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //smm_get_gnvs()->smif = 0; + //gnvs()->smif = 0; return 1; } diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 145c942..d0c5f6d 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -11,11 +11,6 @@ #define MAX_LCD_BRIGHTNESS 0xd8 -/* The southbridge SMI handler checks whether gnvs has a - * valid pointer before calling the trap handler - */ -extern struct global_nvs *gnvs; - int mainboard_io_trap_handler(int smif) { u8 reg8; @@ -64,7 +59,7 @@ break; case 0xd5: printk(BIOS_DEBUG, "Set Brightness\n"); - reg8 = gnvs->brtl; + reg8 = gnvs()->brtl; printk(BIOS_DEBUG, "brtl: %x\n", reg8); ec_write(0x17, reg8); break; @@ -72,7 +67,7 @@ printk(BIOS_DEBUG, "Get Brightness\n"); reg8 = ec_read(0x17); printk(BIOS_DEBUG, "brtl: %x\n", reg8); - gnvs->brtl = reg8; + gnvs()->brtl = reg8; break; case 0xd7: printk(BIOS_DEBUG, "Get ECO mode status\n"); @@ -124,11 +119,11 @@ return 0; } - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; } diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 16565af..56efc62 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -66,7 +66,7 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) { + if (gnvs()->s3u0 == 0) { google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); google_chromeec_set_usb_charge_mode( @@ -79,7 +79,7 @@ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) { + if (gnvs()->s5u0 == 0) { google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c index 4d5bc4f..1c19894d 100644 --- a/src/mainboard/google/butterfly/mainboard_smi.c +++ b/src/mainboard/google/butterfly/mainboard_smi.c @@ -23,7 +23,7 @@ printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ); /* Tell the EC to Enable USB power for S3 if requested */ - if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) + if (gnvs()->s3u0 != 0 || gnvs()->s3u1 != 0) ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB); /* Disable wake on USB, LAN & RTC */ diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 90d5717..71c5b69 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -25,7 +25,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; @@ -38,7 +38,7 @@ * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; + //gnvs()->smif = 0; return 1; } @@ -87,10 +87,10 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) + if (gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) + if (gnvs()->s3u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); @@ -100,10 +100,10 @@ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) + if (gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) + if (gnvs()->s5u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index 1446321..ab1d3ec 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -19,7 +19,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 3a63b39..b811505 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -16,7 +16,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c index e60ceae..1a59f1e 100644 --- a/src/mainboard/google/link/mainboard_smi.c +++ b/src/mainboard/google/link/mainboard_smi.c @@ -49,18 +49,18 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) + if (gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) + if (gnvs()->s3u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); break; case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) + if (gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) + if (gnvs()->s5u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); break; diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c index c179aee..c02d713 100644 --- a/src/mainboard/google/parrot/smihandler.c +++ b/src/mainboard/google/parrot/smihandler.c @@ -63,7 +63,7 @@ /* Tell the EC to Disable USB power */ - if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) { + if (gnvs()->s3u0 == 0 && gnvs()->s3u1 == 0) { ec_kbc_write_cmd(0x45); ec_kbc_write_ib(0xF2); } diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index e6e40aa..96d5bee 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -55,10 +55,10 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) + if (gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) + if (gnvs()->s3u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); @@ -68,10 +68,10 @@ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) + if (gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) + if (gnvs()->s5u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 346866f..ec68686 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -60,10 +60,10 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) + if (gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) + if (gnvs()->s3u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); @@ -78,10 +78,10 @@ break; case ACPI_S4: case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) + if (gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) + if (gnvs()->s5u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 0b6b227..a4af7ca 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -49,7 +49,7 @@ * charge smart phone. * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system. */ - if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) { + if (gnvs()->s3u0 != 0 || gnvs()->s3u1 != 0) { ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00); ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) | 0x01); printk(BIOS_DEBUG, "USB wake from S3 enabled.\n"); @@ -59,7 +59,7 @@ * the XHCI PME to prevent wake when the port power is cut * after the transition into suspend. */ - if (smm_get_gnvs()->xhci) { + if (gnvs()->xhci) { u32 reg32 = pci_read_config32(PCH_XHCI_DEV, 0x74); reg32 &= ~(1 << 8); /* disable PME */ reg32 |= (1 << 15); /* clear PME status */ diff --git a/src/mainboard/intel/cannonlake_rvp/smihandler.c b/src/mainboard/intel/cannonlake_rvp/smihandler.c index 682c33d..391ec7d 100644 --- a/src/mainboard/intel/cannonlake_rvp/smihandler.c +++ b/src/mainboard/intel/cannonlake_rvp/smihandler.c @@ -12,7 +12,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 97f5c43..b2998c0 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -16,7 +16,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 27f8c4f..e813183 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -17,7 +17,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index 703876c..82bc588 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -24,7 +24,7 @@ switch (smif) { case 0x99: printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; + gnvs()->smif = 0; break; default: return 0; @@ -37,7 +37,7 @@ * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; + //gnvs()->smif = 0; return 1; } @@ -83,10 +83,10 @@ /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: - if (smm_get_gnvs()->s3u0 == 0) + if (gnvs()->s3u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) + if (gnvs()->s3u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); @@ -96,10 +96,10 @@ enable_gpe(WAKE_GPIO_EN); break; case ACPI_S5: - if (smm_get_gnvs()->s5u0 == 0) + if (gnvs()->s5u0 == 0) google_chromeec_set_usb_charge_mode( 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) + if (gnvs()->s5u1 == 0) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 30ab2b1..ce44f8f 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -28,11 +28,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -45,7 +45,7 @@ enable_smi(EOS); } -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -228,7 +228,7 @@ u32 reg32; /* LPE Device */ - if (gnvs->dev.lpe_en) { + if (gnvs()->dev.lpe_en) { reg32 = iosf_port58_read(LPE_PCICFGCTR1); reg32 &= ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); @@ -237,7 +237,7 @@ /* SCC Devices */ #define SCC_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ + do { if (gnvs()->dev.scc_en[SCC_NVS_ ## name_]) { \ reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ @@ -249,7 +249,7 @@ /* LPSS Devices */ #define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ + do { if (gnvs()->dev.lpss_en[LPSS_NVS_ ## name_]) { \ reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 12f5347..d3883e1 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -29,11 +29,11 @@ case 0x32: printk(BIOS_DEBUG, "OS Init\n"); /* - * gnvs->smif: + * gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -46,7 +46,7 @@ enable_smi(EOS); } -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 59b4178..cb0c49d 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -31,7 +31,7 @@ * by coreboot. */ static struct global_nvs *gnvs; -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -41,11 +41,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -471,8 +471,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs() && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index e181875..b28f61f 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -126,7 +126,7 @@ pmc_enable_smi(EOS); } -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -211,7 +211,7 @@ case ACPI_S3: printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); - gnvs->uior = uart_is_controller_initialized(); + gnvs()->uior = uart_is_controller_initialized(); /* Invalidate the cache before going to S3 */ wbinvd(); diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 8af9046..69efc60 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -25,16 +25,16 @@ /* Inherited from cpu/x86/smm.h resulting in a different signature */ int southbridge_io_trap_handler(int smif) { - struct global_nvs *gnvs = smm_get_gnvs(); + struct global_nvs *gnvs = gnvs(); switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); /* - * gnvs->smif: + * gnvs()->smif: * - On success, the IO Trap Handler returns 0 * - On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -62,7 +62,7 @@ u32 data, mask = 0; u8 trap_sts; int i; - struct global_nvs *gnvs = smm_get_gnvs(); + struct global_nvs *gnvs = gnvs(); /* TRSR - Trap Status Register */ trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST); @@ -78,8 +78,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); + if (gnvs() && gnvs()->smif) + io_trap_handler(gnvs()->smif); return; } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 2f5d92a..d777f58 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -26,11 +26,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -40,7 +40,7 @@ void southbridge_smi_set_eos(void) { enable_smi(EOS); } -struct global_nvs *smm_get_gnvs(void) { return gnvs; } +struct global_nvs *gnvs(void) { return gnvs; } static void busmaster_disable_on_bus(int bus) { diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 9dad4fc..404b3ee 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -19,7 +19,7 @@ #include "nvs.h" static struct global_nvs *gnvs; -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -29,11 +29,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -150,8 +150,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs() && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } @@ -187,7 +187,7 @@ void southbridge_smm_xhci_sleep(u8 slp_type) { - if (smm_get_gnvs()->xhci) + if (gnvs()->xhci) xhci_sleep(slp_type); } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 7cd5c70..f85c4f2 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -193,11 +193,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -502,8 +502,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 1757872..c085141 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -35,11 +35,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -66,8 +66,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 070b7a6..f0ec1b4 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -21,11 +21,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -60,8 +60,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index af242aa..44a7a98 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -27,11 +27,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -66,8 +66,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index f3a80d9..229d4c7 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -28,7 +28,7 @@ * by coreboot. */ static struct global_nvs *gnvs; -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -38,11 +38,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -120,8 +120,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs() && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 4621c85..0998314 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -26,7 +26,7 @@ * by coreboot. */ static struct global_nvs *gnvs; -struct global_nvs *smm_get_gnvs(void) +struct global_nvs *gnvs(void) { return gnvs; } @@ -36,11 +36,11 @@ switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* gnvs()->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ - gnvs->smif = 0; + gnvs()->smif = 0; return 1; /* IO trap handled */ } @@ -456,8 +456,8 @@ /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { - if (gnvs && gnvs->smif) - io_trap_handler(gnvs->smif); // call function smif + if (gnvs() && gnvs()->smif) + io_trap_handler(gnvs()->smif); // call function smif return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/42849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Gerrit-Change-Number: 42849 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801dx: Drop APM_CNT_MBI_UPDATE
by Kyösti Mälkki (Code Review) 01 Jul '20

01 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42852 ) Change subject: sb/intel/i82801dx: Drop APM_CNT_MBI_UPDATE ...................................................................... sb/intel/i82801dx: Drop APM_CNT_MBI_UPDATE No useful implementation existed. Change-Id: I9a6f9876330fe9f0cdb2925e20f3675fda53d32b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801dx/smihandler.c 1 file changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42852/1 diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 783e6d3..4f3ebd2 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -26,10 +26,6 @@ */ u16 pmbase = PMBASE_ADDR; -unsigned char *mbi = NULL; -u32 mbi_len; -u8 mbi_initialized = 0; - /** * @brief read and clear PM1_STS * @return PM1_STS register @@ -337,17 +333,6 @@ outl(pmctrl, pmbase + PM1_CNT); printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; - case APM_CNT_MBI_UPDATE: // FIXME - if (mbi_initialized) { - printk(BIOS_DEBUG, "SMI#: mbi already registered!\n"); - return; - } - mbi = *(void **)0x500; - mbi_len = *(u32 *)0x504; - mbi_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len); - break; - default: printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a6f9876330fe9f0cdb2925e20f3675fda53d32b Gerrit-Change-Number: 42852 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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