coreboot-gerrit July 2020

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Change in coreboot[master]: util/futility: Check for pkg-config and libcrypto
by Patrick Georgi (Code Review) 01 Jul '20

01 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42881 ) Change subject: util/futility: Check for pkg-config and libcrypto ...................................................................... util/futility: Check for pkg-config and libcrypto When building a configuration that requires futility (e.g. Chrome OS builds), pkg-config and libcrypto are required. Since vboot's build system isn't the most helpful about it, test ourselves and fail out with some actionable message. Tested: - configs that don't need futility don't test for pkg-config, so it's not required for them. - failing pkg-config test leads to the message - working pkg-config test leads to a successful build Fixes https://ticket.coreboot.org/issues/242 Change-Id: I103ce5115284352e0a3a7fdcf8b427f56ce15ba7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/futility/Makefile.inc 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/42881/1 diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index ee4ad05..ed185ce 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -2,15 +2,22 @@ VBOOT_FUTILITY = $(VBOOT_HOST_BUILD)/futility/futility -$(VBOOT_FUTILITY): +HOSTPKGCONFIG ?= pkg-config + +$(VBOOT_FUTILITY): check-openssl-presence @printf " MAKE $(subst $(objutil)/,,$(@))\n" unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ - $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ + PKG_CONFIG="$(HOSTPKGCONFIG)" \ V=$(V) \ $@ +.PHONY: check-openssl-presence +check-openssl-presence: + $(HOSTPKGCONFIG) --exists libcrypto || \ + (echo "Error: Ensure that pkg-config and openssl's libcrypto, including header files, are installed."; exit 1) + $(objutil)/futility/futility: $(VBOOT_FUTILITY) mkdir -p $(dir $@) cp $< $@.tmp -- To view, visit https://review.coreboot.org/c/coreboot/+/42881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103ce5115284352e0a3a7fdcf8b427f56ce15ba7 Gerrit-Change-Number: 42881 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: Defuse vboot's openssl linking
by Patrick Georgi (Code Review) 01 Jul '20

01 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42880 ) Change subject: util/cbfstool: Defuse vboot's openssl linking ...................................................................... util/cbfstool: Defuse vboot's openssl linking Vboot determines openssl through pkgconfig, so pointing its build system to /bin/true makes the build not break unless it needs to use valid information about openssl. Vboot's use of openssl is only for some special features, mostly around PKCS key format parsing and not needed by cbfstool. While cbfstool can link vboot, it can't link with openssl because openssl's license is deliberately incompatible with the GPL. Change-Id: Ia3825f9625a1964d7cefc47ab3c3a8250ceefafb Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/42880/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index f38c825..bc2ff48 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -133,7 +133,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(VBOOT_HOST_BUILD) \ CC="$(HOSTCC)" \ - $(if $(HOSTPKGCONFIG), PKG_CONFIG="$(HOSTPKGCONFIG)") \ + PKG_CONFIG="true" \ V=$(V) \ hostlib -- To view, visit https://review.coreboot.org/c/coreboot/+/42880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3825f9625a1964d7cefc47ab3c3a8250ceefafb Gerrit-Change-Number: 42880 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 5: Code-Review+1 (1 comment) a https://review.coreboot.org/c/coreboot/+/40278/5/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/Makefile.inc: https://review.coreboot.org/c/coreboot/+/40278/5/src/mainboard/purism/libre… PS5, Line 1: ## : ## : ## ew, that was from the SPDX replacements. Where did you copy it from? (it also needs to be removed from there) -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 01 Jul 2020 17:56:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/morphius: Enable support for garaged stylus
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42950 to review the following change. Change subject: mb/google/zork/var/morphius: Enable support for garaged stylus ...................................................................... mb/google/zork/var/morphius: Enable support for garaged stylus This change adds support for pen insert/eject operations in S0 and wake on pen eject from S3 for morphius. BUG=b:158814699,b:158719244 Change-Id: I3530a0aa83ec69559436687205c64524b862799b Signed-off-by: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/morphius/overridetree.cb 3 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42950/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 885de14..3e7756b 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -15,6 +15,7 @@ select VGA_BIOS select BOARD_ROMSIZE_KB_16384 select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index f037b14..f7e30ef 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -72,7 +72,7 @@ /* PCIE_WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ - PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 3faab0d..1240aa6 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -79,6 +79,18 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_4)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end end device mmio 0xfedca000 on -- To view, visit https://review.coreboot.org/c/coreboot/+/42950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3530a0aa83ec69559436687205c64524b862799b Gerrit-Change-Number: 42950 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Drop unused/unnecessary GPIO macros
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42941 ) Change subject: mb/google/zork: Drop unused/unnecessary GPIO macros ...................................................................... mb/google/zork: Drop unused/unnecessary GPIO macros This change drops macros for GPIOs which are unused or don't really require extra indirection (same across all variants). BUG=b:159283649 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281 --- M src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/zork/variants/baseboard/tpm_tis.c 2 files changed, 2 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42941/1 diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h index 4801a5e..84433e0 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h @@ -7,22 +7,6 @@ #include <soc/gpio.h> #include <platform_descriptors.h> -#define H1_PCH_INT GPIO_3 -#define PEN_DETECT_ODL GPIO_4 -#define PEN_POWER_EN GPIO_5 -#define TOUCHPAD_INT_ODL GPIO_9 -#define EC_FCH_WAKE_L GPIO_24 -#define WIFI_PCIE_RESET_L GPIO_26 -#define PCIE_RST1_L GPIO_27 -#define EN_PWR_WIFI GPIO_29 -#define NVME_AUX_RESET_L GPIO_40 -#define WIFI_AUX_RESET_L GPIO_42 -#define EN_PWR_CAMERA GPIO_76 -#define EN_PWR_TOUCHPAD_PS2 GPIO_67 -#define PCIE_0_WIFI_CLKREQ_ODL GPIO_92 -#define PCIE_1_SD_CLKREQ_ODL GPIO_115 -#define BIOS_FLASH_WP_ODL GPIO_137 -#define SD_AUX_RESET_L GPIO_142 #define WLAN_CLKREQ CLK_REQ0 #define SD_CLKREQ CLK_REQ1 @@ -43,28 +27,17 @@ #endif #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE) -#define FPMCU_INT_L GPIO_6 -#define FPMCU_RST_ODL GPIO_11 #define EC_IN_RW_OD GPIO_130 -#define PCIE_4_NVME_CLKREQ_ODL GPIO_132 #define NVME_CLKREQ CLK_REQ4 #else #define EC_IN_RW_OD GPIO_11 -#define PCIE_2_NVME_CLKREQ_ODL GPIO_116 #define NVME_CLKREQ CLK_REQ2 #endif /* SPI Write protect */ -#define CROS_WP_GPIO BIOS_FLASH_WP_ODL +#define CROS_WP_GPIO GPIO_137 #define GPIO_EC_IN_RW EC_IN_RW_OD -/* PCIe reset pins */ -#define PCIE_0_RST WIFI_AUX_RESET_L -#define PCIE_1_RST SD_AUX_RESET_L -#define PCIE_2_RST 0 -#define PCIE_3_RST 0 -#define PCIE_4_RST NVME_AUX_RESET_L - #endif /* _ACPI__ */ /* These define the GPE, not the GPIO. */ diff --git a/src/mainboard/google/zork/variants/baseboard/tpm_tis.c b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c index 52e83cf..46952c3 100644 --- a/src/mainboard/google/zork/variants/baseboard/tpm_tis.c +++ b/src/mainboard/google/zork/variants/baseboard/tpm_tis.c @@ -6,5 +6,5 @@ int tis_plat_irq_status(void) { - return gpio_interrupt_status(H1_PCH_INT); + return gpio_interrupt_status(GPIO_3); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a94327103a419f26b1d7feda4c995363ada7281 Gerrit-Change-Number: 42941 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork/var/ezkinil: Fix GPIO_86 configuration for bid3
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42940 ) Change subject: mb/google/zork/var/ezkinil: Fix GPIO_86 configuration for bid3 ...................................................................... mb/google/zork/var/ezkinil: Fix GPIO_86 configuration for bid3 Board version 3 for Ezkinil follows Trembyle reference v3.51 schematics and hence GPIO_86 does not need a variant specific override. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da --- M src/mainboard/google/zork/variants/ezkinil/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42940/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 2d6ebe7..d8c8edd 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -40,8 +40,6 @@ PAD_GPI(GPIO_11, PULL_UP), /* FPMCU_BOOT0 Change NC */ PAD_GPI(GPIO_69, PULL_UP), - /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ - PAD_GPI(GPIO_86, PULL_UP), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) -- To view, visit https://review.coreboot.org/c/coreboot/+/42940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da Gerrit-Change-Number: 42940 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Drop GPIO_27 configuration for trembyle reference
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42939 ) Change subject: mb/google/zork: Drop GPIO_27 configuration for trembyle reference ...................................................................... mb/google/zork: Drop GPIO_27 configuration for trembyle reference This change drops GPIO_27 configuration for trembyle reference boards since it is unused. BUG=b:159453643 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I57dd78e8abcc61802ca85158e7ff348460ad1d8e --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/42939/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 97ee130..902b714 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -15,8 +15,6 @@ /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST1_L - Variable timings (May remove) */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EN_PWR_TOUCHPAD_PS2 - reset */ @@ -47,8 +45,6 @@ /* EC_FCH_WAKE_L */ PAD_GPI(GPIO_24, PULL_UP), PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), - /* PCIE_RST1_L - Variable timings (May remove) */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EMMC_RESET - reset (default stuffing unused)*/ @@ -310,8 +306,6 @@ static const struct soc_amd_gpio gpio_sleep_table[] = { /* PEN_POWER_EN */ PAD_GPO(GPIO_5, LOW), - /* PCIE_RST1_L */ - PAD_GPO(GPIO_27, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57dd78e8abcc61802ca85158e7ff348460ad1d8e Gerrit-Change-Number: 42939 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Add support for active low wifi power enable
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42938 ) Change subject: mb/google/zork: Add support for active low wifi power enable ...................................................................... mb/google/zork: Add support for active low wifi power enable A late change went into v3+ of reference schematics which inverted EN_PWR_WIFI to meet PCIe reset/power timings for WiFi device. This is incorporated into v3.51+ for Trembyle reference and v3.2+ for Dalboz reference. However, some variants are built with v3+ reference schematics, but without the inversion of EN_PWR_WIFI polarity. Thus, we need to add support for following combinations: 1. Pre-v3 Schematics 2. V3+ Schematics 3. V3+ Schematics + Active low wifi power This change adds a new Kconfig `VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW` that sets the minimum board ID that has EN_PWR_WIFI active low in hardware. Variants that missed this change in V3+ integration (berknip and vilboz) have board IDs set to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS + 1. For others, this defaults to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS. BUG=b:159749536 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6 --- M src/mainboard/google/zork/Kconfig M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 3 files changed, 94 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42938/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a9e9562..885de14 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -141,5 +141,12 @@ default 2 if BOARD_GOOGLE_BERKNIP default 3 if BOARD_GOOGLE_DALBOZ default 2 if BOARD_GOOGLE_VILBOZ + default 256 + +config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW + int + default 3 if BOARD_GOOGLE_BERKNIP + default 3 if BOARD_GOOGLE_VILBOZ + default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 5f007f7..44bffc2 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -219,20 +219,20 @@ return NULL; } -static void wifi_power_reset_configure_v3(void) +static void wifi_power_reset_configure_active_low_power(void) { /* * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device. - * - Enable power to WiFi using EN_PWR_WIFI. + * - Enable power to WiFi using EN_PWR_WIFI_L. * - Wait for 50ms after power to WiFi is enabled. - * - Deassert PERST# to WiFi device by driving WIFI_AUX_RESET low. + * - Deassert WIFI_AUX_RESET. */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET */ PAD_GPO(GPIO_29, HIGH), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); @@ -240,6 +240,41 @@ gpio_set(GPIO_29, 0); } +static void wifi_power_reset_configure_active_high_power(void) +{ + /* + * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET + * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be + * set low before driving it high to trigger a WiFi power cycle to meet PCIe + * requirements. Thus, configure GPIOs such that: + * - WIFI_AUX_RESET is configured first to assert PERST# to WiFi device + * - Disable power to WiFi. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Deassert WIFI_AUX_RESET. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET */ + PAD_GPO(GPIO_29, HIGH), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_42, LOW), + }; + program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_42, 1); + mdelay(50); + gpio_set(GPIO_29, 0); +} + +static void wifi_power_reset_configure_v3(uint32_t board_version) +{ + if (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) + wifi_power_reset_configure_active_low_power(); + else + wifi_power_reset_configure_active_high_power(); +} + static void wifi_power_reset_configure_pre_v3(void) { /* @@ -275,7 +310,7 @@ if (!google_chromeec_cbi_get_board_version(&board_version) && (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) - wifi_power_reset_configure_v3(); + wifi_power_reset_configure_v3(board_version); else wifi_power_reset_configure_pre_v3(); } @@ -285,6 +320,12 @@ PAD_GPO(GPIO_5, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), + /* + * On pre-v3 schematics, GPIO_29 is EN_PWR_WIFI. So, setting to high should be no-op. + * On v3+ schematics, GPIO_29 is WIFI_AUX_RESET. Setting to high ensures that PERST# is + * asserted to WiFi device until coreboot reconfigures GPIO_29 on resume path. + */ + PAD_GPO(GPIO_29, HIGH), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index a395e2e..97ee130 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -214,20 +214,20 @@ return NULL; } -static void wifi_power_reset_configure_v3(void) +static void wifi_power_reset_configure_active_low_power(void) { /* * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. - * - Enable power to WiFi using EN_PWR_WIFI. + * - Enable power to WiFi using EN_PWR_WIFI_L. * - Wait for 50ms after power to WiFi is enabled. * - Deassert WIFI_AUX_RESET_L. */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET_L */ PAD_GPO(GPIO_86, LOW), - /* EN_PWR_WIFI */ - PAD_GPO(GPIO_42, HIGH), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); @@ -235,6 +235,41 @@ gpio_set(GPIO_86, 1); } +static void wifi_power_reset_configure_active_high_power(void) +{ + /* + * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L + * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be + * set low before driving it high to trigger a WiFi power cycle to meet PCIe + * requirements. Thus, configura GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device + * - Disable power to WiFi. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Deassert WIFI_AUX_RESET_L. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, LOW), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_42, LOW), + }; + program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(10); + gpio_set(GPIO_42, 1); + mdelay(50); + gpio_set(GPIO_86, 1); +} + +static void wifi_power_reset_configure_v3(uint32_t board_version) +{ + if (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) + wifi_power_reset_configure_active_low_power(); + else + wifi_power_reset_configure_active_high_power(); +} + static void wifi_power_reset_configure_pre_v3(void) { /* @@ -267,7 +302,7 @@ if (!google_chromeec_cbi_get_board_version(&board_version) && (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) - wifi_power_reset_configure_v3(); + wifi_power_reset_configure_v3(board_version); else wifi_power_reset_configure_pre_v3(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6 Gerrit-Change-Number: 42938 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Move GPIO sleep table to dalboz and trembyle reference
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42937 ) Change subject: mb/google/zork: Move GPIO sleep table to dalboz and trembyle reference ...................................................................... mb/google/zork: Move GPIO sleep table to dalboz and trembyle reference This change moves variant_sleep_gpio_table() definition to dalboz and trembyle references to allow each to make their own changes. BUG=b:159749536, b:159453643 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I15b19cea05f1a540c56b6bc0507306d2348ac17f --- M src/mainboard/google/zork/variants/baseboard/Makefile.inc M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 4 files changed, 36 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42937/1 diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc index 0f025e0..c09fc7e 100644 --- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc @@ -24,7 +24,8 @@ ramstage-y += helpers.c ramstage-y += tpm_tis.c -smm-y += gpio_baseboard_common.c +smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE) += gpio_baseboard_trembyle.c +smm-$(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ) += gpio_baseboard_dalboz.c # Add OEM ID table ifeq ($(CONFIG_USE_OEM_BIN),y) diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c index aacf14b..a4e8648 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c @@ -30,20 +30,3 @@ *size = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct soc_amd_gpio gpio_sleep_table[] = { - /* PEN_POWER_EN */ - PAD_GPO(GPIO_5, LOW), - /* PCIE_RST1_L */ - PAD_GPO(GPIO_27, LOW), - /* NVME_AUX_RESET_L */ - PAD_GPO(GPIO_40, LOW), - /* EN_PWR_CAMERA */ - PAD_GPO(GPIO_76, LOW), -}; - -const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) -{ - *size = ARRAY_SIZE(gpio_sleep_table); - return gpio_sleep_table; -} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 2b6f516..5f007f7 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -279,3 +279,20 @@ else wifi_power_reset_configure_pre_v3(); } + +static const struct soc_amd_gpio gpio_sleep_table[] = { + /* PEN_POWER_EN */ + PAD_GPO(GPIO_5, LOW), + /* PCIE_RST1_L */ + PAD_GPO(GPIO_27, LOW), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 01aef2b..a395e2e 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -271,3 +271,20 @@ else wifi_power_reset_configure_pre_v3(); } + +static const struct soc_amd_gpio gpio_sleep_table[] = { + /* PEN_POWER_EN */ + PAD_GPO(GPIO_5, LOW), + /* PCIE_RST1_L */ + PAD_GPO(GPIO_27, LOW), + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15b19cea05f1a540c56b6bc0507306d2348ac17f Gerrit-Change-Number: 42937 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42936 to review the following change. Change subject: mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz ...................................................................... mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz This change moves PCIE_RST1_L deassertion to happen as part of variant_pcie_power_reset_configure() instead of variant_romstage_entry() since romstage is guaranteed to run 100ms+ after PP3300_NVME is enabled. This is one of the first things that coreboot on x86 does as part of early mainboard configuration. Additionally, this change also drops deassertion of PCIE_RST0_L on bid 1 for dalboz since PCIE_RST0_L is already deasserted much earlier in the boot flow. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Aaron Durbin <adurbin(a)google.com> Commit-Queue: Aaron Durbin <adurbin(a)google.com> Tested-by: Aaron Durbin <adurbin(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/dalboz/Makefile.inc D src/mainboard/google/zork/variants/dalboz/romstage.c 3 files changed, 3 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/42936/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index ba50362..2b6f516 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -270,6 +270,9 @@ { uint32_t board_version; + /* Deassert PCIE_RST1_L */ + gpio_set(GPIO_27, 1); + if (!google_chromeec_cbi_get_board_version(&board_version) && (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) wifi_power_reset_configure_v3(); diff --git a/src/mainboard/google/zork/variants/dalboz/Makefile.inc b/src/mainboard/google/zork/variants/dalboz/Makefile.inc index a616e2f..51d19fe 100644 --- a/src/mainboard/google/zork/variants/dalboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/dalboz/Makefile.inc @@ -2,7 +2,5 @@ subdirs-y += ./spd -romstage-y += romstage.c - ramstage-y += gpio.c ramstage-y += variant.c diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c deleted file mode 100644 index 42e36c4..0000000 --- a/src/mainboard/google/zork/variants/dalboz/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <stddef.h> -#include <soc/romstage.h> -#include <baseboard/variants.h> -#include <ec/google/chromeec/ec.h> -#include <gpio.h> -#include <soc/gpio.h> -#include <variant/gpio.h> - -void variant_romstage_entry(void) -{ - uint32_t board_version; - - if (google_chromeec_cbi_get_board_version(&board_version)) - board_version = 1; - - if (board_version < 2) { - /* SET PCIE_RST0_L HIGH */ - gpio_set(WIFI_PCIE_RESET_L, 1); - } else { - /* SET PCIE_RST1_L HIGH */ - gpio_set(PCIE_RST1_L, 1); - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/42936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2 Gerrit-Change-Number: 42936 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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