coreboot-gerrit July 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Add read CPU PPIN MSR function
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42901 ) Change subject: soc/intel/xeon_sp: Add read CPU PPIN MSR function ...................................................................... soc/intel/xeon_sp: Add read CPU PPIN MSR function Tested on OCP Tioga Pass and Delta Lake. Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/cpu.h 4 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42901/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 386401f..1df5c13 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -188,3 +188,34 @@ /* update numa domain for all cpu devices */ xeonsp_init_cpu_config(); } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 2d12699..1458000 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -4,6 +4,7 @@ #define _SOC_CPU_H #include <device/device.h> +#include <cpu/x86/msr.h> #define CPUID_COOPERLAKE_SP_A0 0x05065a @@ -11,5 +12,6 @@ #define CPU_BCLK 100 void cpx_init_cpus(struct device *dev); +msr_t read_msr_ppin(void); #endif diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index f97c37d..c59edab 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -244,3 +244,34 @@ FUNC_EXIT(); } + +msr_t read_msr_ppin(void) +{ + msr_t ppin = {0}; + msr_t msr; + + /* If MSR_PLATFORM_INFO PPIN_CAP is 0, PPIN capability is not supported */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & MSR_PPIN_CAP) == 0) { + printk(BIOS_ERR, "MSR_PPIN_CAP is 0, PPIN is not supported\n"); + return ppin; + } + + /* Access to MSR_PPIN is permitted only if MSR_PPIN_CTL LOCK is 0 and ENABLE is 1 */ + msr = rdmsr(MSR_PPIN_CTL); + if (msr.lo & MSR_PPIN_CTL_LOCK) { + printk(BIOS_ERR, "MSR_PPIN_CTL_LOCK is 1, PPIN access is not allowed\n"); + return ppin; + } + + if ((msr.lo & MSR_PPIN_CTL_ENABLE) == 0) { + /* Set MSR_PPIN_CTL ENABLE to 1 */ + msr.lo |= MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + } + ppin = rdmsr(MSR_PPIN); + /* Set enable to 0 after reading MSR_PPIN */ + msr.lo &= ~MSR_PPIN_CTL_ENABLE; + wrmsr(MSR_PPIN_CTL, msr); + return ppin; +} diff --git a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h index 0221c7d..c2af265 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/cpu.h @@ -4,6 +4,7 @@ #define _SOC_CPU_H_ #include <device/device.h> +#include <cpu/x86/msr.h> /* SKXSP CPUID */ #define CPUID_SKYLAKE_SP_A0_A1 0x506f0 @@ -15,5 +16,6 @@ int get_cpu_count(void); void xeon_sp_init_cpus(struct device *dev); +msr_t read_msr_ppin(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4 Gerrit-Change-Number: 42901 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: drivers/ipmi: Add IPMI KCS support in romstage
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40234 ) Change subject: drivers/ipmi: Add IPMI KCS support in romstage ...................................................................... drivers/ipmi: Add IPMI KCS support in romstage It's necessary to run IPMI commands in romstage for writing error SEL such as memory initialization error SEL, and also for other usages such as starting FRB2 timer, OEM commands, etc. Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/Kconfig M src/drivers/ipmi/Makefile.inc M src/drivers/ipmi/ipmi_kcs.h A src/drivers/ipmi/ipmi_kcs_ops_premem.c 4 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/40234/1 diff --git a/src/drivers/ipmi/Kconfig b/src/drivers/ipmi/Kconfig index 37cfc0d..0304cb0 100644 --- a/src/drivers/ipmi/Kconfig +++ b/src/drivers/ipmi/Kconfig @@ -18,3 +18,10 @@ IPMB messages are limited to 32-bytes total. When the data size is larger than this value, IPMI can complete reading/writing the data over multiple commands. + +config IPMI_KCS_ROMSTAGE + bool + default n + depends on IPMI_KCS + help + IPMI KCS support in romstage. diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index 973fff8..06a3433 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -2,3 +2,6 @@ ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_ops.c ramstage-$(CONFIG_IPMI_KCS) += ipmi_fru.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs_ops_premem.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_kcs.c +romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi_ops.c diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index 9a04377..5de77ed 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -40,6 +40,9 @@ const unsigned char *inmsg, int inlen, unsigned char *outmsg, int outlen); +/* Run basic IPMI init functions in romstage from the provided PnP device */ +void ipmi_kcs_premem_init(const u16 port, const u16 device); + struct ipmi_rsp { uint8_t lun; uint8_t cmd; diff --git a/src/drivers/ipmi/ipmi_kcs_ops_premem.c b/src/drivers/ipmi/ipmi_kcs_ops_premem.c new file mode 100644 index 0000000..e601041 --- /dev/null +++ b/src/drivers/ipmi/ipmi_kcs_ops_premem.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> + +#include <device/pnp.h> +#include <delay.h> +#include <timer.h> +#include "ipmi_kcs.h" +#include "chip.h" + +static int ipmi_get_bmc_self_test_result(const struct device *dev, + struct ipmi_selftest_rsp *rsp) +{ + int ret; + + ret = ipmi_kcs_message(dev->path.pnp.port, IPMI_NETFN_APPLICATION, 0, + IPMI_BMC_GET_SELFTEST_RESULTS, NULL, 0, (u8 *)rsp, + sizeof(*rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->resp.completion_code); + return 1; + } + if (ret != sizeof(*rsp)) { + printk(BIOS_ERR, "IPMI: %s response truncated\n", __func__); + return 1; + } + + return 0; +} + +void ipmi_kcs_premem_init(const u16 port, const u16 device) +{ + const struct drivers_ipmi_config *conf = NULL; + struct ipmi_selftest_rsp selftestrsp; + uint8_t retry_count; + const struct device *dev; + + /* Find IPMI pnp device from devicetree in romstage */ + dev = dev_find_slot_pnp(port, device); + + if (!dev) { + printk(BIOS_ERR, "IPMI: Cannot find pnp device port: %x, device %x\n", + port, device); + return; + } + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "IPMI: romstage PNP KCS 0x%x\n", dev->path.pnp.port); + if (dev->chip_info) + conf = dev->chip_info; + + if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { + struct stopwatch sw; + stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000); + printk(BIOS_INFO, "IPMI: Waiting for BMC...\n"); + + while (!stopwatch_expired(&sw)) { + if (inb(dev->path.pnp.port) != 0xff) + break; + mdelay(100); + } + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "IPMI: Waiting for BMC timed out\n"); + return; + } + } + + printk(BIOS_INFO, "Get BMC self test result..."); + for (retry_count = 0; retry_count < conf->bmc_boot_timeout; retry_count++) { + if (!ipmi_get_bmc_self_test_result(dev, &selftestrsp)) + break; + + mdelay(1000); + } + + switch (selftestrsp.result) { + case IPMI_APP_SELFTEST_NO_ERROR: /* 0x55 */ + printk(BIOS_DEBUG, "No Error\n"); + break; + case IPMI_APP_SELFTEST_NOT_IMPLEMENTED: /* 0x56 */ + printk(BIOS_DEBUG, "Function Not Implemented\n"); + break; + case IPMI_APP_SELFTEST_ERROR: /* 0x57 */ + printk(BIOS_ERR, "BMC: Corrupted or inaccessible data or device\n"); + /* Don't write tables if communication failed */ + break; + case IPMI_APP_SELFTEST_FATAL_HW_ERROR: /* 0x58 */ + printk(BIOS_ERR, "BMC: Fatal Hardware Error\n"); + /* Don't write tables if communication failed */ + break; + case IPMI_APP_SELFTEST_RESERVED: /* 0xFF */ + printk(BIOS_DEBUG, "Reserved\n"); + break; + + default: /* Other Device Specific Hardware Error */ + printk(BIOS_ERR, "BMC: Device Specific Error\n"); + /* Don't write tables if communication failed */ + break; + } + +} -- To view, visit https://review.coreboot.org/c/coreboot/+/40234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3198965670454b123e570f9056673fdf515f52b Gerrit-Change-Number: 40234 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

7 28

Change in coreboot[master]: soc/intel/tigerlake: Remove unused EHL DID from TGL SoC
by Subrata Banik (Code Review) 04 Jul '20

04 Jul '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43062 ) Change subject: soc/intel/tigerlake: Remove unused EHL DID from TGL SoC ...................................................................... soc/intel/tigerlake: Remove unused EHL DID from TGL SoC TEST=Able to build and boot TGLRVP. Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/tigerlake/bootblock/report_platform.c 1 file changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/43062/1 diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c index a64738d..588c848 100644 --- a/src/soc/intel/tigerlake/bootblock/report_platform.c +++ b/src/soc/intel/tigerlake/bootblock/report_platform.c @@ -36,8 +36,6 @@ { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, - { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, - { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, }; static struct { @@ -76,11 +74,6 @@ { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, - { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, - { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, - { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, - { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, }; static struct { @@ -91,12 +84,6 @@ { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, - { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, - { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/43062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a Gerrit-Change-Number: 43062 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x9scl: Split IPMI support into a variant
by Nico Huber (Code Review) 04 Jul '20

04 Jul '20

Hello Jonathan Kollasch, Angel Pons, Michael Niewöhner, Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43085 to review the following change. Change subject: mb/supermicro/x9scl: Split IPMI support into a variant ...................................................................... mb/supermicro/x9scl: Split IPMI support into a variant The devicetree already mentioned the device, but without the driver selected that didn't do anything. Selecting the driver for all variants isn't an option as that would result in incredibly long timeouts on systems without the hardware. Change-Id: I7cc348135469052c595297226e5e86c040de4746 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/supermicro/x9scl/Kconfig M src/mainboard/supermicro/x9scl/Kconfig.name M src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/variants/x9scl-f/overridetree.cb 4 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/43085/1 diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index fb73683..22a8702 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SUPERMICRO_X9SCL +if BOARD_SUPERMICRO_X9SCL || BOARD_SUPERMICRO_X9SCL_F config BOARD_SPECIFIC_OPTIONS def_bool y @@ -22,6 +22,10 @@ string default "X9SCL/X9SCM" +config OVERRIDE_DEVICETREE + string + default "variants/x9scl-f/overridetree.cb" if BOARD_SUPERMICRO_X9SCL_F + config USBDEBUG_HCD_INDEX int default 1 diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name index e0e91f1..2a3cd13 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig.name +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -1,2 +1,6 @@ config BOARD_SUPERMICRO_X9SCL bool "X9SCL/X9SCM" + +config BOARD_SUPERMICRO_X9SCL_F + bool "X9SCL-F/X9SCM-F (w/ BMC)" + select IPMI_KCS diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 9236f6f..3827379 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -22,7 +22,6 @@ register "c2_latency" = "0x0065" register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) - register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" @@ -104,11 +103,6 @@ device pnp 2e.16 off end # Deep sleep device pnp 2e.17 off end # GPIOA end - chip drivers/ipmi - register "wait_for_bmc" = "1" - register "bmc_boot_timeout" = "60" - device pnp ca2.0 off end # IPMI KCS - end chip superio/nuvoton/wpcm450 device pnp 164e.2 on io 0x60 = 0x03e8 diff --git a/src/mainboard/supermicro/x9scl/variants/x9scl-f/overridetree.cb b/src/mainboard/supermicro/x9scl/variants/x9scl-f/overridetree.cb new file mode 100644 index 0000000..9d713f1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/variants/x9scl-f/overridetree.cb @@ -0,0 +1,14 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + device pci 1f.0 on # LPC bridge + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 off end # IPMI KCS + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/43085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc348135469052c595297226e5e86c040de4746 Gerrit-Change-Number: 43085 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Kollasch <jakllsch(a)kollasch.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: post_code: add defines for missing postcode values
by Sindhoor Tilak (Code Review) 04 Jul '20

04 Jul '20

Hello build bot (Jenkins), Patrick Georgi, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42278 to look at the new patch set (#9). Change subject: post_code: add defines for missing postcode values ...................................................................... post_code: add defines for missing postcode values The change introduces new POST codes missing their respective defines The newly added POST code sets are arranged in logical order of coreboot stages. The change also is an effort to ensure the added defines reflect postcodes at the entry of function. Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc --- M src/include/console/post_codes.h 1 file changed, 304 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42278/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/42278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02d09d0b2bad3f9a93fff54d11a5ba5e53fadbcc Gerrit-Change-Number: 42278 Gerrit-PatchSet: 9 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Jonas Löffelholz (Code Review) 03 Jul '20

03 Jul '20

Jonas Löffelholz has uploaded a new patch set (#60) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This commit adds initial support for the Supermicro X11SCH-F. What is working: * Aspeed AST2500 graphics output * Serial console * SuperIO devicetree config * Boots into Linux 5.5 * Tested payload EDK II * SATA slots * USB slots * IPMI KCS * LinuxBoot * No ACPI error in Windows/Linux * Windows 10 support * TPM Support (w/ patched IFD) - Patch IFD at 0x235=0x03 and 0x13E=0x84 Tested with Intel Xeon E-2186G and 64 GB ECC RAM. Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/memory.c A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/include/variant/variants.h A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 21 files changed, 1,006 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/60 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 60 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Enable CSE Firmware Lite SKU
by Jamie Ryu (Code Review) 03 Jul '20

03 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42070 ) Change subject: mb/google/volteer: Enable CSE Firmware Lite SKU ...................................................................... mb/google/volteer: Enable CSE Firmware Lite SKU BUG=B:158140797 TEST=build and boot volteer with CSE Lite SKU Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/google/volteer/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42070/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 76acb9a..cc00b06 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -25,6 +25,7 @@ select MAINBOARD_HAS_TPM2 select PCIEXP_HOTPLUG select SOC_INTEL_TIGERLAKE + select SOC_INTEL_CSE_LITE_SKU if BOARD_GOOGLE_BASEBOARD_VOLTEER -- To view, visit https://review.coreboot.org/c/coreboot/+/42070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Gerrit-Change-Number: 42070 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

5 24

Change in coreboot[master]: soc/intel/tgl: Disable hybrid storage mode in recovery mode
by Jamie Ryu (Code Review) 03 Jul '20

03 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42282 ) Change subject: soc/intel/tgl: Disable hybrid storage mode in recovery mode ...................................................................... soc/intel/tgl: Disable hybrid storage mode in recovery mode This is WA to initialize NVME with CSE Lite in recovery mode. CSME Lite does not support hybrid storage dynamic configuration in RO. Hence, hybrid storage mode is disabled in recovery mode for CSME Lite until the functionality is supported by CSE Lite RO. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/42282/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c old mode 100644 new mode 100755 index 926d8eb..e931a22 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -10,6 +10,7 @@ #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> +#include <security/vboot/vboot_common.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -251,7 +252,17 @@ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; /* Enable Hybrid storage auto detection */ - params->HybridStorageMode = config->HybridStorageMode; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) { + /* + * Since CSME Lite SKU does not support hybrid storage dynamic + * configuration in recovery boot mode, dynamic configuration is + * disabled as a temporary WA until the fix is available. + */ + printk(BIOS_DEBUG, "cse_lite: recovery mode enabled\n"); + params->HybridStorageMode = 0; + } else { + params->HybridStorageMode = config->HybridStorageMode; + } /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Gerrit-Change-Number: 42282 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

8 40

Change in coreboot[master]: Update vboot submodule to upstream master
by Patrick Georgi (Code Review) 03 Jul '20

03 Jul '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43008 ) Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id c531000f: 2020-05-18 20:55:55 +0000 - (vboot: Add recovery reason code for CSE Lite SKU errors) to commit id 68de90c7: 2020-07-02 11:31:05 +0000 - (Allow building for non-CrOS environments) This brings in 59 new commits. Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43008/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index c531000..68de90c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit c531000f851418520b6873f65c202d21f141eb84 +Subproject commit 68de90c7e2f4a27d3a76489199176d2ab8f56de1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f3c30511ff4acc60e3581bdab89d685dc7beaa5 Gerrit-Change-Number: 43008 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: util/inteltool: Support dumping more BARs on Skylake mobile SoCs
by Angel Pons (Code Review) 03 Jul '20

03 Jul '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42749 ) Change subject: util/inteltool: Support dumping more BARs on Skylake mobile SoCs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43d54ef189d500701872a56e67781a744990328 Gerrit-Change-Number: 42749 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 03 Jul 2020 20:07:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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