coreboot-gerrit July 2020

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Change in coreboot[master]: src/drivers/usb/ehci_debug.c: Add missing include
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43341 ) Change subject: src/drivers/usb/ehci_debug.c: Add missing include ...................................................................... src/drivers/usb/ehci_debug.c: Add missing include Replace unused <stddef.h> by missing <stdint.h>. This needed for 'u64'. Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/usb/ehci_debug.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/43341/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5af8e2e..8641b13 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> +#include <stdint.h> #include <console/console.h> #include <console/usb.h> #include <arch/io.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d Gerrit-Change-Number: 43341 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: src: Remove unused 'include <stdint.h>
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41827 ) Change subject: src: Remove unused 'include <stdint.h> ...................................................................... src: Remove unused 'include <stdint.h> Found using: diff <(git grep -l '#include \(<stdint.h>\|<types.h>\)' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/soundwire.c M src/drivers/intel/soundwire/soundwire.c M src/soc/intel/jasperlake/me.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41827/1 diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index 1151a18..341114a 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -6,7 +6,6 @@ #include <commonlib/helpers.h> #include <device/soundwire.h> #include <stdbool.h> -#include <stdint.h> #include <string.h> /* Specification-defined prefix for SoundWire properties. */ diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index ab09ff4..34ecd86 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -8,7 +8,6 @@ #include <device/path.h> #include <device/soundwire.h> #include <stdbool.h> -#include <stdint.h> #include "soundwire.h" #include "chip.h" diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index c8496f9..0797993 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -5,7 +5,6 @@ #include <intelblocks/cse.h> #include <console/console.h> #include <soc/me.h> -#include <stdint.h> static void dump_me_status(void *unused) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Gerrit-Change-Number: 41827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: src/acpi/soundwire.c: Add missing <stddef.h>
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43340 ) Change subject: src/acpi/soundwire.c: Add missing <stddef.h> ...................................................................... src/acpi/soundwire.c: Add missing <stddef.h> size_t needs <stddef.h>. Replace unused <stdint.h> by <stddef.h>. Change-Id: Ib9ab5555adeeddd9eea7a93dbb166d8479eca42e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/soundwire.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/43340/1 diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index ed3634d..c27c6f2 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -6,7 +6,7 @@ #include <commonlib/helpers.h> #include <device/soundwire.h> #include <stdbool.h> -#include <stdint.h> +#include <stddef.h> /* Specification-defined prefix for SoundWire properties. */ #define SDW_PFX "mipi-sdw-" -- To view, visit https://review.coreboot.org/c/coreboot/+/43340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9ab5555adeeddd9eea7a93dbb166d8479eca42e Gerrit-Change-Number: 43340 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: src: Remove unused 'include <types.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41677 ) Change subject: src: Remove unused 'include <types.h>' ...................................................................... src: Remove unused 'include <types.h>' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/include/armv7.h M src/cpu/intel/model_206ax/common.c M src/drivers/generic/bayhub/bh720.h M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c M src/drivers/lenovo/hybrid_graphics/romstage.c M src/drivers/uart/util.c M src/include/timer.h M src/mainboard/emulation/qemu-i440fx/acpi_tables.c M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/google/auron/ec.c M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/beltino/variants/mccloud/led.c M src/mainboard/google/beltino/variants/monroe/led.c M src/mainboard/google/beltino/variants/panther/led.c M src/mainboard/google/beltino/variants/tricky/led.c M src/mainboard/google/beltino/variants/zako/led.c M src/mainboard/google/cyan/ec.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/google/jecht/led.c M src/mainboard/google/link/ec.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/rambi/acpi_tables.c M src/mainboard/google/rambi/ec.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/google/slippy/ec.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/emeraldlake2/acpi_tables.c M src/mainboard/intel/emeraldlake2/ec.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/intel/strago/acpi_tables.c M src/mainboard/intel/strago/ec.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/mainboard/samsung/lumpy/ec.c M src/mainboard/samsung/stumpy/acpi_tables.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/mainboard/ti/beaglebone/bootblock.c M src/northbridge/intel/sandybridge/common.c M src/security/memory/memory.c M src/soc/amd/picasso/include/soc/soc_util.h M src/soc/cavium/cn81xx/include/soc/twsi.h M src/soc/intel/common/vbt.h M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/qualcomm/ipq806x/include/soc/clock.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/sc7180/uart_bitbang.c M src/soc/qualcomm/sdm845/uart_bitbang.c M src/southbridge/intel/lynxpoint/acpi.c 57 files changed, 0 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/41677/1 diff --git a/src/arch/arm/include/armv7.h b/src/arch/arm/include/armv7.h index 1223d9b..0d7a8cf 100644 --- a/src/arch/arm/include/armv7.h +++ b/src/arch/arm/include/armv7.h @@ -2,7 +2,6 @@ #ifndef ARMV7_H #define ARMV7_H -#include <types.h> /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P1 0x410FC091 diff --git a/src/cpu/intel/model_206ax/common.c b/src/cpu/intel/model_206ax/common.c index 216160b..a881314 100644 --- a/src/cpu/intel/model_206ax/common.c +++ b/src/cpu/intel/model_206ax/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <cpu/x86/msr.h> #include "model_206ax.h" diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h index d8c3196..ac07f8b 100644 --- a/src/drivers/generic/bayhub/bh720.h +++ b/src/drivers/generic/bayhub/bh720.h @@ -2,7 +2,6 @@ /* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */ -#include <types.h> enum { BH720_PROTECT = 0xd0, diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index 22b825b..ce6aa86 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <device/smbus.h> #include <console/console.h> diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index ec9f995..8f0e7bd 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <option.h> #include <device/device.h> diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index 3d14646..e62215d 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <option.h> #include <device/device.h> diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 1ac994e..b761dd7 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/uart.h> -#include <types.h> #include <timer.h> /* Calculate divisor. Do not floor but round to nearest integer. */ diff --git a/src/include/timer.h b/src/include/timer.h index 9b7a05e..d2c67f64f 100644 --- a/src/include/timer.h +++ b/src/include/timer.h @@ -2,7 +2,6 @@ #ifndef TIMER_H #define TIMER_H -#include <types.h> #define NSECS_PER_SEC 1000000000 #define USECS_PER_SEC 1000000 diff --git a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c index c78de52..1f10837 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi_tables.c +++ b/src/mainboard/emulation/qemu-i440fx/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 3abf8aa..e36c70b 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <string.h> #include <console/console.h> #include <acpi/acpi.h> diff --git a/src/mainboard/google/auron/ec.c b/src/mainboard/google/auron/ec.c index 8448358..5be20c0 100644 --- a/src/mainboard/google/auron/ec.c +++ b/src/mainboard/google/auron/ec.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index d2f7f45..3275fd2 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e343d68..6d9d500 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/io.h> #include <device/device.h> diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index 2ba84d9..da5002f 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/monroe/led.c b/src/mainboard/google/beltino/variants/monroe/led.c index c67632f..5f6932d 100644 --- a/src/mainboard/google/beltino/variants/monroe/led.c +++ b/src/mainboard/google/beltino/variants/monroe/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/beltino/variants/panther/led.c b/src/mainboard/google/beltino/variants/panther/led.c index 54e4458..3fe93b4 100644 --- a/src/mainboard/google/beltino/variants/panther/led.c +++ b/src/mainboard/google/beltino/variants/panther/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/beltino/variants/tricky/led.c b/src/mainboard/google/beltino/variants/tricky/led.c index 475e4b6..49d7918 100644 --- a/src/mainboard/google/beltino/variants/tricky/led.c +++ b/src/mainboard/google/beltino/variants/tricky/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "../../onboard.h" diff --git a/src/mainboard/google/beltino/variants/zako/led.c b/src/mainboard/google/beltino/variants/zako/led.c index 16c0d9f..0c83657 100644 --- a/src/mainboard/google/beltino/variants/zako/led.c +++ b/src/mainboard/google/beltino/variants/zako/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "../../onboard.h" void set_power_led(int state) diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c index f69d4c4..3862434 100644 --- a/src/mainboard/google/cyan/ec.c +++ b/src/mainboard/google/cyan/ec.c @@ -5,7 +5,6 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> void mainboard_ec_init(void) { diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index c70716a..b8105fd 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -18,7 +18,6 @@ #include <soc/trustzone.h> #include <soc/wakeup.h> #include <timestamp.h> -#include <types.h> #include "exynos5250.h" diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 1ac44fa..ab7bc8c 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -4,7 +4,6 @@ #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> -#include <types.h> #include <boardid.h> void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned int count) diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 3e8cc20..9170f0b 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c index 054f0aa..8a6a304 100644 --- a/src/mainboard/google/jecht/led.c +++ b/src/mainboard/google/jecht/led.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c index e3f68e1..6f87f1d 100644 --- a/src/mainboard/google/link/ec.c +++ b/src/mainboard/google/link/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 62722ec..203f29f 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index c4c1788..65e6af4 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c index 0d7d110..7588eff 100644 --- a/src/mainboard/google/rambi/ec.c +++ b/src/mainboard/google/rambi/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index ba55647..338aa94 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/google/slippy/ec.c b/src/mainboard/google/slippy/ec.c index b646b9c..5761a7c 100644 --- a/src/mainboard/google/slippy/ec.c +++ b/src/mainboard/google/slippy/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include "ec.h" diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 9cab3a1..141a869 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <smbios.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 08bd4cd..f477080 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index 24edfea..ebbaf41 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 67299fd..ef59110 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 36d0d66..0312f60 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/intel/emeraldlake2/ec.c b/src/mainboard/intel/emeraldlake2/ec.c index f6819c7..5c088a3 100644 --- a/src/mainboard/intel/emeraldlake2/ec.c +++ b/src/mainboard/intel/emeraldlake2/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index c97face..6291d60 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 1351e62..3b4f14a 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index e97d9c1..b1b3ccd 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -6,7 +6,6 @@ #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/nvs.h> -#include <types.h> #include <boardid.h> #include "onboard.h" diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c index f69d4c4..3862434 100644 --- a/src/mainboard/intel/strago/ec.c +++ b/src/mainboard/intel/strago/ec.c @@ -5,7 +5,6 @@ #include <ec/google/chromeec/ec.h> #include "ec.h" #include <vendorcode/google/chromeos/chromeos.h> -#include <types.h> void mainboard_ec_init(void) { diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 87cb965..edc5a8b 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <device/device.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 180a362..b271d53 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> #include <acpi/acpi.h> diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index aafbdb6..9d27b1c 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c index a53d033..7aac479 100644 --- a/src/mainboard/samsung/lumpy/ec.c +++ b/src/mainboard/samsung/lumpy/ec.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <types.h> #include <console/console.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index b66e4dd..b9730c9 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 1351e62..3b4f14a 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <acpi/acpi.h> #include <device/device.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 7e69a3d..6e9538b 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <types.h> #include <bootblock_common.h> #include <console/uart.h> #include <cpu/ti/am335x/clock.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index d64a740..b27911d 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <console/console.h> #include <device/device.h> #include "sandybridge.h" diff --git a/src/security/memory/memory.c b/src/security/memory/memory.c index 664e7c1..7b9b2ff 100644 --- a/src/security/memory/memory.c +++ b/src/security/memory/memory.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include "memory.h" /** diff --git a/src/soc/amd/picasso/include/soc/soc_util.h b/src/soc/amd/picasso/include/soc/soc_util.h index 6515761..e89bcda 100644 --- a/src/soc/amd/picasso/include/soc/soc_util.h +++ b/src/soc/amd/picasso/include/soc/soc_util.h @@ -3,7 +3,6 @@ #ifndef __PICASSO_SOC_UTIL_H__ #define __PICASSO_SOC_UTIL_H__ -#include <types.h> enum socket_type { SOCKET_FP5 = 0, diff --git a/src/soc/cavium/cn81xx/include/soc/twsi.h b/src/soc/cavium/cn81xx/include/soc/twsi.h index 9756c6a..6a7923d 100644 --- a/src/soc/cavium/cn81xx/include/soc/twsi.h +++ b/src/soc/cavium/cn81xx/include/soc/twsi.h @@ -1,5 +1,4 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <device/i2c.h> #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index e5b0066..5cbb2c7 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -4,7 +4,6 @@ #define _INTEL_COMMON_VBT_H_ #include <commonlib/region.h> -#include <types.h> /* * Returns VBT pointer and mapping after checking prerequisites for Pre OS diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index e6bc1d4..ef1d1d4 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -3,7 +3,6 @@ #ifndef __SOC_MEDIATEK_MT6358_H__ #define __SOC_MEDIATEK_MT6358_H__ -#include <types.h> enum { PMIC_SWCID = 0x000a, diff --git a/src/soc/qualcomm/ipq806x/include/soc/clock.h b/src/soc/qualcomm/ipq806x/include/soc/clock.h index d7cb3c4..e9460d4 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/clock.h +++ b/src/soc/qualcomm/ipq806x/include/soc/clock.h @@ -5,7 +5,6 @@ #define __IPQ860X_CLOCK_H_ #include <soc/iomap.h> -#include <types.h> /* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index fb17102..945a85c 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -4,7 +4,6 @@ #define _SOC_QUALCOMM_QCS405_SYMBOLS_H_ #include <symbols.h> -#include <types.h> DECLARE_REGION(ssram); DECLARE_REGION(bsram); diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c index b671fec..b3a6cd5 100644 --- a/src/soc/qualcomm/sc7180/uart_bitbang.c +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -2,7 +2,6 @@ #include <console/uart.h> #include <gpio.h> -#include <types.h> #include <boot/coreboot_tables.h> #define UART_TX_PIN GPIO(44) diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c index 6bcc5ba..b78db83 100644 --- a/src/soc/qualcomm/sdm845/uart_bitbang.c +++ b/src/soc/qualcomm/sdm845/uart_bitbang.c @@ -2,7 +2,6 @@ #include <console/uart.h> #include <gpio.h> -#include <types.h> #define UART_TX_PIN GPIO(4) diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c index d63af6c..a568b74 100644 --- a/src/southbridge/intel/lynxpoint/acpi.c +++ b/src/southbridge/intel/lynxpoint/acpi.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <cbmem.h> -#include <types.h> #include <string.h> #include <version.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Gerrit-Change-Number: 41677 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 22

Change in coreboot[master]: src: Remove unused 'include <string.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41913 ) Change subject: src: Remove unused 'include <string.h>' ...................................................................... src: Remove unused 'include <string.h>' Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<' Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/soundwire.c M src/mainboard/dell/optiplex_9010/sch5545_ec.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/41913/1 diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index 341114a..701fe2a 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -6,7 +6,6 @@ #include <commonlib/helpers.h> #include <device/soundwire.h> #include <stdbool.h> -#include <string.h> /* Specification-defined prefix for SoundWire properties. */ #define SDW_PFX "mipi-sdw-" diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index 4013452..2719460 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -2,7 +2,6 @@ #include <cbfs.h> #include <cf9_reset.h> -#include <string.h> #include <option.h> #include <arch/io.h> #include <cpu/x86/msr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/41913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d Gerrit-Change-Number: 41913 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: Zork: Splits devicetree between baseboards
by Rob Barnes (Code Review) 14 Jul '20

14 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42741 ) Change subject: Zork: Splits devicetree between baseboards ...................................................................... Zork: Splits devicetree between baseboards Splits zork baseboard devicetree between dalboz and trembyle. The devicetree is simply duplicated, no other changes in this commit. BUG=b:158096224 BRANCH=none TEST=Build coreboot for zork Signed-off-by: Rob Barnes <robbarnes(a)google.com> Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 --- M src/mainboard/google/zork/Kconfig A src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb A src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 3 files changed, 390 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42741/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a226cd8..87713a2 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -77,7 +77,8 @@ config DEVICETREE string - default "variants/baseboard/devicetree.cb" + default "variants/baseboard/devicetree_trembyle.cb" if BOARD_GOOGLE_BASEBOARD_TREMBYLE + default "variants/baseboard/devicetree_dalboz.cb" if BOARD_GOOGLE_BASEBOARD_DALBOZ config OVERRIDE_DEVICETREE string diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb new file mode 100644 index 0000000..18c3783 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb new file mode 100644 index 0000000..18c3783 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -0,0 +1,194 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_MOBILE" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_REMOTE_POWER_ON" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time" = "20" #mS + + # Lower die temperature limit + register "thermctl_limit" = "100" #degrees C + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit" = "18000" #mA + register "psi0_soc_current_limit" = "12000" #mA + register "vddcr_soc_voltage_margin" = "0" #mV + register "vddcr_vdd_voltage_margin" = "0" #mV + + # VRM Limits + register "vrm_maximum_current_limit" = "0" #mA + register "vrm_soc_maximum_current_limit" = "0" #mA + register "vrm_current_limit" = "0" #mA + register "vrm_soc_current_limit" = "0" #mA + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "sd_emmc_config" = "SD_EMMC_EMMC_HS400" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_66M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL112, + }" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_LOW(1) | ESPI_VW_IRQ_LEVEL_LOW(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + register "irq_override" = "{ + /* PS/2 keyboard IRQ1 override */ + {1, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + + /* PS/2 mouse IRQ12 override */ + {12, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH}, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Internal GPP Bridge 0 to Bus B + device pci 0.0 on end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(62)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + end + end + end + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/42741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 Gerrit-Change-Number: 42741 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini
by Chen Wisley (Code Review) 14 Jul '20

14 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43284 ) Change subject: mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini ...................................................................... mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini Applied CL (cb:38212) to reduce acoustic noise, and observed that screen flicked on vt2 on some devices after idle a perior of time. Remove SSR (1/8) setting for SA to default SSR 1/2, issue disappeared, and didn't affect noise much. BUG=none TEST=build dratini, observe that screen flick issue disapppered Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/43284/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 0bada7d..2bfcc26 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -23,7 +23,6 @@ register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "2" register "FastPkgCRampDisableIa" = "1" register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index a3bb782..fc3bb85 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -23,7 +23,6 @@ register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" register "SlowSlewRateForGt" = "2" - register "SlowSlewRateForSa" = "2" register "FastPkgCRampDisableIa" = "1" register "FastPkgCRampDisableGt" = "1" register "FastPkgCRampDisableSa" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/43284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 Gerrit-Change-Number: 43284 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: mainboard/volteer: Enable SaGv
by Shreesh Chhabbi (Code Review) 14 Jul '20

14 Jul '20

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42483 ) Change subject: mainboard/volteer: Enable SaGv ...................................................................... mainboard/volteer: Enable SaGv Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/42483/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926c..6dbc415 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -36,7 +36,7 @@ register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 -- To view, visit https://review.coreboot.org/c/coreboot/+/42483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Gerrit-Change-Number: 42483 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: mb/google/kukui: Add new configs 'Cerise' and 'Stern'
by Xinxiong Xu (Code Review) 14 Jul '20

14 Jul '20

Xinxiong Xu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43320 ) Change subject: mb/google/kukui: Add new configs 'Cerise' and 'Stern' ...................................................................... mb/google/kukui: Add new configs 'Cerise' and 'Stern' New boards introduced to Kukui family. BUG=None TEST=make # select Cerise and Stern Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/43320/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 4c8ebbf..7a1990e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -47,6 +47,8 @@ default "Juniper" if BOARD_GOOGLE_JUNIPER default "Kappa" if BOARD_GOOGLE_KAPPA default "Damu" if BOARD_GOOGLE_DAMU + default "Cerise" if BOARD_GOOGLE_CERISE + default "Stern" if BOARD_GOOGLE_STERN config DRIVER_TPM_SPI_BUS hex diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 4b12034..22130e5 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -35,3 +35,11 @@ config BOARD_GOOGLE_DAMU bool "-> Damu" select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_CERISE + bool "-> Cerise" + select BOARD_GOOGLE_KUKUI_COMMON + +config BOARD_GOOGLE_STERN + bool "-> Stern" + select BOARD_GOOGLE_KUKUI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/43320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 Gerrit-Change-Number: 43320 Gerrit-PatchSet: 1 Gerrit-Owner: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: sb/intel/lynxpoint: Define SerialIO devfns
by Angel Pons (Code Review) 14 Jul '20

14 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43367 ) Change subject: sb/intel/lynxpoint: Define SerialIO devfns ...................................................................... sb/intel/lynxpoint: Define SerialIO devfns This reduces differences with Broadwell. Tested with BUILD_TIMELESS=1, Google Panther remains identical. Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/serialio.c 2 files changed, 19 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43367/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c59878e..e30f149 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -140,6 +140,17 @@ #define PCH_PCS 0x84 #define PCH_PCS_PS_D3HOT 3 +/* SerialIO */ +#define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0) +#define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1) +#define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2) +#define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3) +#define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4) +#define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5) +#define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6) + +#define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0) + #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 77da535..08f69fb 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -151,51 +151,51 @@ serialio_enable_clock(bar0); switch (dev->path.pci.devfn) { - case PCI_DEVFN(21, 0): /* SDMA */ + case PCH_DEVFN_SDMA: /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 1): /* I2C0 */ + case PCH_DEVFN_I2C0: /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 2): /* I2C1 */ + case PCH_DEVFN_I2C1: /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 3): /* SPI0 */ + case PCH_DEVFN_SPI0: /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 4): /* SPI1 */ + case PCH_DEVFN_SPI1: /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 5): /* UART0 */ + case PCH_DEVFN_UART0: /* UART0 */ sio_index = SIO_ID_UART0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 6): /* UART1 */ + case PCH_DEVFN_UART1: /* UART1 */ sio_index = SIO_ID_UART1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(23, 0): /* SDIO */ + case PCH_DEVFN_SDIO: /* SDIO */ sio_index = SIO_ID_SDIO; serialio_d23_ltr(bar0); serialio_d23_mode(config->sio_acpi_mode); -- To view, visit https://review.coreboot.org/c/coreboot/+/43367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487 Gerrit-Change-Number: 43367 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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