Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43367 )
Change subject: sb/intel/lynxpoint: Define SerialIO devfns ......................................................................
sb/intel/lynxpoint: Define SerialIO devfns
This reduces differences with Broadwell.
Tested with BUILD_TIMELESS=1, Google Panther remains identical.
Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/serialio.c 2 files changed, 19 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43367/1
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index c59878e..e30f149 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -140,6 +140,17 @@ #define PCH_PCS 0x84 #define PCH_PCS_PS_D3HOT 3
+/* SerialIO */ +#define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0) +#define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1) +#define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2) +#define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3) +#define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4) +#define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5) +#define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6) + +#define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0) + #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 77da535..08f69fb 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -151,51 +151,51 @@ serialio_enable_clock(bar0);
switch (dev->path.pci.devfn) { - case PCI_DEVFN(21, 0): /* SDMA */ + case PCH_DEVFN_SDMA: /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 1): /* I2C0 */ + case PCH_DEVFN_I2C0: /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 2): /* I2C1 */ + case PCH_DEVFN_I2C1: /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 3): /* SPI0 */ + case PCH_DEVFN_SPI0: /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 4): /* SPI1 */ + case PCH_DEVFN_SPI1: /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 5): /* UART0 */ + case PCH_DEVFN_UART0: /* UART0 */ sio_index = SIO_ID_UART0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 6): /* UART1 */ + case PCH_DEVFN_UART1: /* UART1 */ sio_index = SIO_ID_UART1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(23, 0): /* SDIO */ + case PCH_DEVFN_SDIO: /* SDIO */ sio_index = SIO_ID_SDIO; serialio_d23_ltr(bar0); serialio_d23_mode(config->sio_acpi_mode);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43367 )
Change subject: sb/intel/lynxpoint: Define SerialIO devfns ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43367/1/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/serialio.c:
https://review.coreboot.org/c/coreboot/+/43367/1/src/southbridge/intel/lynxp... PS1, Line 154: case PCH_DEVFN_SDMA: /* SDMA */ The comments could now be removed in a follow-up commit.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43367 )
Change subject: sb/intel/lynxpoint: Define SerialIO devfns ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43367/1/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/serialio.c:
https://review.coreboot.org/c/coreboot/+/43367/1/src/southbridge/intel/lynxp... PS1, Line 154: case PCH_DEVFN_SDMA: /* SDMA */
The comments could now be removed in a follow-up commit.
Yes, I will remove them from both lynxpoint and broadwell
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43367 )
Change subject: sb/intel/lynxpoint: Define SerialIO devfns ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43367 )
Change subject: sb/intel/lynxpoint: Define SerialIO devfns ......................................................................
sb/intel/lynxpoint: Define SerialIO devfns
This reduces differences with Broadwell.
Tested with BUILD_TIMELESS=1, Google Panther remains identical.
Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43367 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/serialio.c 2 files changed, 19 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 896454f..db3d92a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -143,6 +143,17 @@ #define PCH_PCS 0x84 #define PCH_PCS_PS_D3HOT 3
+/* SerialIO */ +#define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0) +#define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1) +#define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2) +#define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3) +#define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4) +#define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5) +#define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6) + +#define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0) + #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 77da535..08f69fb 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -151,51 +151,51 @@ serialio_enable_clock(bar0);
switch (dev->path.pci.devfn) { - case PCI_DEVFN(21, 0): /* SDMA */ + case PCH_DEVFN_SDMA: /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 1): /* I2C0 */ + case PCH_DEVFN_I2C0: /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 2): /* I2C1 */ + case PCH_DEVFN_I2C1: /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 3): /* SPI0 */ + case PCH_DEVFN_SPI0: /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 4): /* SPI1 */ + case PCH_DEVFN_SPI1: /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 5): /* UART0 */ + case PCH_DEVFN_UART0: /* UART0 */ sio_index = SIO_ID_UART0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 6): /* UART1 */ + case PCH_DEVFN_UART1: /* UART1 */ sio_index = SIO_ID_UART1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(23, 0): /* SDIO */ + case PCH_DEVFN_SDIO: /* SDIO */ sio_index = SIO_ID_SDIO; serialio_d23_ltr(bar0); serialio_d23_mode(config->sio_acpi_mode);