coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: Enable SATA Port Dito Config
by Shaunak Saha (Code Review) 15 Jul '20

15 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42415 ) Change subject: mb/google/volteer: Enable SATA Port Dito Config ...................................................................... mb/google/volteer: Enable SATA Port Dito Config Enable SataPortsEnableDitoConfig for port 0 and 1. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42415/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8ff790e..baf4c97 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -98,6 +98,8 @@ register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[0]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/42415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 Gerrit-Change-Number: 42415 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: soc/intel/tigerlake: SATA Port Enable Dito Config
by Shaunak Saha (Code Review) 15 Jul '20

15 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42214 ) Change subject: soc/intel/tigerlake: SATA Port Enable Dito Config ...................................................................... soc/intel/tigerlake: SATA Port Enable Dito Config SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to assert the DEVSLP signal as soon as there are no commands outstanding to the device and the port specific Device Sleep idle timer has expired. And the Device Sleep Idle Timeout value (PxDEVSLP.DITO and PxDEVSLP.DM) is a port specific timeout value used by the HBA for determining when to assert the DEVSLP signal. It provides a mechanism for the HBA to apply a programmable amount of hysteresis so as to prevent the HBA from asserting the DEVSLP signal too quickly which may result in undesirable latencies. *PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier. Default is 15. *PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer and TGL RVP. Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42214/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index ed09aaa..d920fc9 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -98,6 +98,18 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; + + /* + * SATA Port Enable Dito Config. + * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). + */ + uint8_t SataPortsEnableDitoConfig[8]; + /* Audio related */ uint8_t PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; @@ -308,11 +320,6 @@ */ uint8_t DmiPwrOptimizeDisable; - /* - * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. - * Default 0. Setting this to 1 disables the SATA Power Optimizer. - */ - uint8_t SataPwrOptimizeDisable; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357..c2c963f 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -202,6 +202,18 @@ params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* + * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. + * SataPortsDmVal is the DITO multiplier. Default is 15. + * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625. + */ + for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { + if (config->SataPortsEnableDitoConfig[i]) { + params->SataPortsDmVal[i] = 15; + params->SataPortsDitoVal[1] = 625; + } + } + /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/42214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db Gerrit-Change-Number: 42214 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

7 16

Change in coreboot[master]: mb/google/oak: Add new DRAM part number for oak.
by Wuxy - (Code Review) 15 Jul '20

15 Jul '20

Wuxy - has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42184 ) Change subject: mb/google/oak: Add new DRAM part number for oak. ...................................................................... mb/google/oak: Add new DRAM part number for oak. This change adds the following memory parts to oak: 1.K4E8E304ED-2GB 2.K4E6E304ED-4GB BUG=b:157702981a BRANCH=none TEST=none Signed-off-by: Xingyu Wu <wuxy(a)bitland.corp-partner.google.com> Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 --- M src/mainboard/google/oak/sdram_configs.c A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc A src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc 3 files changed, 234 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42184/1 diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c index 60b212a..2b9fc14 100644 --- a/src/mainboard/google/oak/sdram_configs.c +++ b/src/mainboard/google/oak/sdram_configs.c @@ -14,8 +14,8 @@ #include "sdram_inf/sdram-lpddr3-MT52L512M32D2PF-4GB.inc" /* ram_code = 0110 */ #include "sdram_inf/sdram-lpddr3-H9CCNNNBJTALAR-4GB.inc" /* ram_code = 0111 */ #include "sdram_inf/sdram-lpddr3-MT52L256M32D1PF-2GB.inc" /* ram_code = 1000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */ diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc new file mode 100644 index 0000000..e6c3a83 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E6E304ED-4GB.inc @@ -0,0 +1,116 @@ +{ /* 4GB (16Gb + 16Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 3, + [CHANNEL_B] = 3 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 10, 6, 8}, + [CHANNEL_B] = { 9, 9, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 27, 64}, + { 27, 72} + }, + [CHANNEL_B] = { + { 27, 72}, + { 27, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x50a350a7, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc new file mode 100644 index 0000000..4c58286 --- /dev/null +++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-K4E8E304ED-2GB.inc @@ -0,0 +1,116 @@ +{ /* 2GB (8Gb + 8Gb) for dual rank dram setting */ + { + .impedance_drvp = 0x9, + .impedance_drvn = 0xa, + .datlat_ucfirst = 18, + + .ca_train = { + [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0}, + [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7} + }, + + .ca_train_center = { + [CHANNEL_A] = 3, + [CHANNEL_B] = 3 + }, + + .wr_level = { + [CHANNEL_A] = { 8, 10, 6, 8}, + [CHANNEL_B] = { 9, 9, 7, 6} + }, + + .gating_win = { + [CHANNEL_A] = { + { 27, 64}, + { 27, 72} + }, + [CHANNEL_B] = { + { 27, 72}, + { 27, 72} + } + }, + + .rx_dqs_dly = { + [CHANNEL_A] = 0x08080908, + [CHANNEL_B] = 0x0b0b060b + }, + + .rx_dq_dly = { + [CHANNEL_A] = { + 0x01010300, + 0x06030002, + 0x01010201, + 0x03020002, + 0x00010103, + 0x02010201, + 0x02040200, + 0x02020201 + }, + [CHANNEL_B] = { + 0x00020202, + 0x02020202, + 0x01020201, + 0x01010100, + 0x01010101, + 0x01000002, + 0x02000201, + 0x00010101, + } + }, + }, + { + .actim = 0xaafd478c, + .actim1 = 0x91001f59, + .actim05t = 0x000025e1, + .conf1 = 0x00048403, + .conf2 = 0x030000a9, + .ddr2ctl = 0x000063b1, + .gddr3ctl1 = 0x11000000, + .misctl0 = 0x21000000, + .pd_ctrl = 0xd1976442, + .rkcfg = 0x002156c1, + .test2_3 = 0xbfc70401, + .test2_4 = 0x2801110d + }, + { + .cona = 0x50535057, + .conb = 0x17283544, + .conc = 0x0a1a0b1a, + .cond = 0x00000000, + .cone = 0xffff0848, + .conf = 0x08420000, + .cong = 0x2b2b2a38, + .conh = 0x00000000, + .conm_1 = 0x40000500, + .conm_2 = 0x400005ff, + .mdct_1 = 0x80030303, + .mdct_2 = 0x34220c3f, + .test0 = 0xcccccccc, + .test1 = 0xcccccccc, + .testb = 0x00060124, + .testc = 0x38470000, + .testd = 0x00000000, + .arba = 0x7f077a49, + .arbc = 0xa0a070dd, + .arbd = 0x07007046, + .arbe = 0x40407046, + .arbf = 0xa0a070c6, + .arbg = 0xffff7047, + .arbi = 0x20406188, + .arbj = 0x9719595e, + .arbk = 0x64f3fc79, + .slct_1 = 0x00010800, + .slct_2 = 0xff03ff00, + .bmen = 0x00ff0001 + }, + { + .mrs_1 = 0x00830001, + .mrs_2 = 0x001c0002, + .mrs_3 = 0x00010003, + .mrs_10 = 0x00ff000a, + .mrs_11 = 0x0000000b, + .mrs_63 = 0x0000003f + }, + .type = TYPE_LPDDR3, + .dram_freq = 896 * MHz, +}, -- To view, visit https://review.coreboot.org/c/coreboot/+/42184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Gerrit-Change-Number: 42184 Gerrit-PatchSet: 1 Gerrit-Owner: Wuxy - <wuxy(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

5 42

Change in coreboot[master]: mb/volteer: Update Aux settings for USB3 Daughterboard
by Brandon Breitenstein (Code Review) 14 Jul '20

14 Jul '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42075 ) Change subject: mb/volteer: Update Aux settings for USB3 Daughterboard ...................................................................... mb/volteer: Update Aux settings for USB3 Daughterboard On certain volteer board configs the daughter card can have no retimer there will need to be a way to verify if this is the case and then correctly config the aux orientation settings This is a WIP and will need some changes but pushing the initial changes for testing and USB3 verification on certain Volteer configs Change-Id: Id0db1b684cfb8b9df6ac8007aee243d3315270bb Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/gpio.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/42075/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index a55ef7d..0dbcea5 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -147,11 +147,11 @@ # TCSS USB3 register "TcssXhciEn" = "1" - register "TcssAuxOri" = "1" + register "TcssAuxOri" = "5" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" - register "IomTypeCPortPadCfg[2]" = "0x0" - register "IomTypeCPortPadCfg[3]" = "0x0" + register "IomTypeCPortPadCfg[2]" = "0x090E0016" + register "IomTypeCPortPadCfg[3]" = "0x090E0017" register "IomTypeCPortPadCfg[4]" = "0x0" register "IomTypeCPortPadCfg[5]" = "0x0" register "IomTypeCPortPadCfg[6]" = "0x0" diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 3290f44..588ea91 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -239,9 +239,9 @@ /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E22, NONE), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ - PAD_NC(GPP_E23, NONE), + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/42075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0db1b684cfb8b9df6ac8007aee243d3315270bb Gerrit-Change-Number: 42075 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/zork: Add USB to baseboard devicetree
by Rob Barnes (Code Review) 14 Jul '20

14 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42799 ) Change subject: mb/google/zork: Add USB to baseboard devicetree ...................................................................... mb/google/zork: Add USB to baseboard devicetree Add USB ports, USB user-facing camera and USB bluetooth to devicetree. WF/AR USB camera left out of this commit. USB ports 4 and 5 are duplicated for picasso and dali. This results in benign AE_NOT_FOUND errors during boot. This will be resolved in follow on patch. BUG=b:158096224 TEST=Boot Trembyle and Dalboz, Dump acpi tables Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb 2 files changed, 153 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42799/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 664e379..d541529 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -124,6 +124,72 @@ device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on # USB 3.1 + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.3 on end + end + end + end + end device pci 0.5 on end # Audio device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 3cc311b..563c95a 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -126,6 +126,93 @@ device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on # USB 3.1 + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + + # The following devices are only enabled on Dali SKUs + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end + device pci 0.4 on # USB 3.1 (Picasso Only) + chip drivers/usb/acpi + # The following devices are only enabled on Picasso SKUs + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.1 on end + end + end + end + end device pci 0.5 on end # Audio device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device -- To view, visit https://review.coreboot.org/c/coreboot/+/42799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87 Gerrit-Change-Number: 42799 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42080 ) Change subject: arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>' ...................................................................... arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>' Change-Id: I5a36f5729a1a5ad5819ebb3c46b775ba52237d65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/postcar_loader.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/42080/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 084384e..241ba8c 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -3,7 +3,6 @@ #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a36f5729a1a5ad5819ebb3c46b775ba52237d65 Gerrit-Change-Number: 42080 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42395 ) Change subject: cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include ...................................................................... cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include Change-Id: Ib721e667144d6803261f3761a077570e0e27391d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/model_1067x/model_1067x_init.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42395/1 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 7230213..cd774d3 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/mp.h> #include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib721e667144d6803261f3761a077570e0e27391d Gerrit-Change-Number: 42395 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: src: Drop unused <cpu/x86/tsc.h> include
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42393 ) Change subject: src: Drop unused <cpu/x86/tsc.h> include ...................................................................... src: Drop unused <cpu/x86/tsc.h> include Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/pc80/pc/spkmodem.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/skylake/acpi.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42393/1 diff --git a/src/drivers/pc80/pc/spkmodem.c b/src/drivers/pc80/pc/spkmodem.c index 7b88c0a..ced544e 100644 --- a/src/drivers/pc80/pc/spkmodem.c +++ b/src/drivers/pc80/pc/spkmodem.c @@ -2,7 +2,6 @@ #include <arch/io.h> #include <console/spkmodem.h> -#include <cpu/x86/tsc.h> #define SPEAKER_PIT_FREQUENCY 0x1234dd diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index d008dd8..43d0e90 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -9,7 +9,6 @@ #include <cpu/x86/smm.h> #include <types.h> #include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> #include <cpu/intel/turbo.h> #include <soc/acpi.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0bac42c..03e7c05 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -9,7 +9,6 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/tsc.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index fce2e45..bc99441 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -11,7 +11,6 @@ #include <string.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 5e5bc49..882f888 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <console/console.h> #include <console/streams.h> -#include <cpu/x86/tsc.h> #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index bdfacd3..71ecd0b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> #include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57 Gerrit-Change-Number: 42393 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: src: Remove unused 'include <cpu/x86/msr.h>'
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41969 ) Change subject: src: Remove unused 'include <cpu/x86/msr.h>' ...................................................................... src: Remove unused 'include <cpu/x86/msr.h>' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/speedstep/acpi.c M src/cpu/x86/lapic/apic_timer.c M src/drivers/intel/gma/intel_ddi.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/intel/harcuvar/acpi_tables.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/scaleway/tagada/acpi_tables.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/ironlake/northbridge.c M src/security/intel/stm/SmmStm.h M src/soc/amd/common/block/psp/psp.c M src/soc/amd/picasso/romstage.c M src/soc/intel/apollolake/car.c M src/soc/intel/apollolake/chip.c M src/soc/intel/baytrail/include/soc/pattrs.h M src/soc/intel/braswell/include/soc/pattrs.h M src/soc/intel/broadwell/cpu_info.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/denverton_ns/include/soc/pattrs.h M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/southbridge/amd/pi/hudson/early_setup.c 23 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/41969/1 diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 3955614..2beb890 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -5,7 +5,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <cpu/intel/fsb.h> #include <cpu/intel/speedstep.h> #include <device/device.h> diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 97c28bd..01a67fa 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <delay.h> #include <thread.h> -#include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> void init_timer(void) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index a04789b..3893664 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -8,7 +8,6 @@ #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> #include <edid.h> #include <drivers/intel/gma/i915.h> diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index ce4a63c..b26722a 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_def.h> -#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> /********************************************** diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 3b4f14a..66fddd3 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <device/device.h> -#include <cpu/x86/msr.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index b8f44b5..669577e 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -4,7 +4,6 @@ #include <stdint.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> -#include <cpu/x86/msr.h> #include <device/pci_def.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index 5f0ad45..e4c854c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -7,7 +7,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <cpu/x86/msr.h> void mainboard_fill_pei_data(struct pei_data *pei_data) { diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 3b4f14a..66fddd3 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <device/device.h> -#include <cpu/x86/msr.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index b87ba6e..63642d7 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -19,7 +19,6 @@ #include <lib.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <assert.h> #include <spd.h> #include <sdram_mode.h> diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index d98af9e..7894dd3 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -6,7 +6,6 @@ #include <stdint.h> #include <delay.h> #include <cpu/intel/model_2065x/model_2065x.h> -#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h index c12b034..0447a9e 100644 --- a/src/security/intel/stm/SmmStm.h +++ b/src/security/intel/stm/SmmStm.h @@ -3,7 +3,6 @@ #ifndef _SMM_STM_H_ #define _SMM_STM_H_ -#include <cpu/x86/msr.h> #include "StmApi.h" /* diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 0e03174..2787b73 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <cpu/x86/msr.h> #include <bootstate.h> #include <console/console.h> #include <amdblocks/psp.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 0bbceec..80bfa0a 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,7 +3,6 @@ #include <arch/cpu.h> #include <acpi/acpi.h> #include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <console/uart.h> #include <cbmem.h> diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c index cbc43d5..fc6691b 100644 --- a/src/soc/intel/apollolake/car.c +++ b/src/soc/intel/apollolake/car.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <cpu/x86/msr.h> #include <intelblocks/msr.h> #include <program_loading.h> #include <soc/cpu.h> diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index cc190ba..3558956 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -5,7 +5,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mp.h> -#include <cpu/x86/msr.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/baytrail/include/soc/pattrs.h b/src/soc/intel/baytrail/include/soc/pattrs.h index c1ca7f4..7c1be28 100644 --- a/src/soc/intel/baytrail/include/soc/pattrs.h +++ b/src/soc/intel/baytrail/include/soc/pattrs.h @@ -4,7 +4,6 @@ #define _PATTRS_H_ #include <stdint.h> -#include <cpu/x86/msr.h> enum { IACORE_MIN, diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 5cad6d0..89c6861 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -4,7 +4,6 @@ #define _SOC_PATTRS_H_ #include <stdint.h> -#include <cpu/x86/msr.h> enum { IACORE_MIN, diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c index 5542f17..506b1a7 100644 --- a/src/soc/intel/broadwell/cpu_info.c +++ b/src/soc/intel/broadwell/cpu_info.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/systemagent.h> diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 70a9cac..6570c5c 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -8,7 +8,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/msr.h> #include <cpu/x86/smm.h> #include <intelblocks/acpi.h> #include <intelblocks/msr.h> diff --git a/src/soc/intel/denverton_ns/include/soc/pattrs.h b/src/soc/intel/denverton_ns/include/soc/pattrs.h index 224c56d..47bb1e7 100644 --- a/src/soc/intel/denverton_ns/include/soc/pattrs.h +++ b/src/soc/intel/denverton_ns/include/soc/pattrs.h @@ -4,7 +4,6 @@ #define _DENVERTON_NS_PATTRS_H_ #include <stdint.h> -#include <cpu/x86/msr.h> enum { IACORE_MIN, IACORE_LFM, IACORE_MAX, IACORE_TURBO, IACORE_END }; diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 31df09d..1f186f7 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -4,7 +4,6 @@ #define _QUARK_REG_ACCESS_H_ #include <cpu/x86/cr.h> -#include <cpu/x86/msr.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index dc97d5e..f69f0b9 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -3,7 +3,6 @@ #include <assert.h> #include <commonlib/sort.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <delay.h> #include <device/pci.h> #include <hob_iiouds.h> diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 8bca42b..14bb5e2 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -16,7 +16,6 @@ #if CONFIG(HUDSON_UART) -#include <cpu/x86/msr.h> #include <delay.h> void configure_hudson_uart(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/41969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Gerrit-Change-Number: 41969 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused 'include <stdint.h>
by HAOUAS Elyes (Code Review) 14 Jul '20

14 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41827 ) Change subject: src: Remove unused 'include <stdint.h> ...................................................................... src: Remove unused 'include <stdint.h> Found using: diff <(git grep -l '#include \(<stdint.h>\|<types.h>\)' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/soundwire.c M src/drivers/intel/soundwire/soundwire.c M src/soc/intel/jasperlake/me.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/41827/1 diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index 1151a18..341114a 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -6,7 +6,6 @@ #include <commonlib/helpers.h> #include <device/soundwire.h> #include <stdbool.h> -#include <stdint.h> #include <string.h> /* Specification-defined prefix for SoundWire properties. */ diff --git a/src/drivers/intel/soundwire/soundwire.c b/src/drivers/intel/soundwire/soundwire.c index ab09ff4..34ecd86 100644 --- a/src/drivers/intel/soundwire/soundwire.c +++ b/src/drivers/intel/soundwire/soundwire.c @@ -8,7 +8,6 @@ #include <device/path.h> #include <device/soundwire.h> #include <stdbool.h> -#include <stdint.h> #include "soundwire.h" #include "chip.h" diff --git a/src/soc/intel/jasperlake/me.c b/src/soc/intel/jasperlake/me.c index c8496f9..0797993 100644 --- a/src/soc/intel/jasperlake/me.c +++ b/src/soc/intel/jasperlake/me.c @@ -5,7 +5,6 @@ #include <intelblocks/cse.h> #include <console/console.h> #include <soc/me.h> -#include <stdint.h> static void dump_me_status(void *unused) { -- To view, visit https://review.coreboot.org/c/coreboot/+/41827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Gerrit-Change-Number: 41827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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