coreboot-gerrit June 2020

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Change in coreboot[master]: mb/google/volteer: Convert static ASL files to new DPTF implementation
by Tim Wawrzynczak (Code Review) 12 Jul '20

12 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41895 ) Change subject: mb/google/volteer: Convert static ASL files to new DPTF implementation ...................................................................... mb/google/volteer: Convert static ASL files to new DPTF implementation This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/variants/baseboard/devicetree.cb D src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl D src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl D src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl 8 files changed, 93 insertions(+), 151 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/41895/1 diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 63e70c5..7bb6d64 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -5,6 +5,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_SX9310 + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c6a2e8b..a02d30f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -224,7 +224,98 @@ #From EDS(575683) device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF 0x9A03 + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + register "policies.enabled.passive" = "1" + register "policies.enabled.critical" = "1" + register "policies.enabled.active" = "1" + + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={ + {.temp=85, .fan_pct=90}, + {.temp=80, .fan_pct=69}, + {.temp=75, .fan_pct=56}, + {.temp=70, .fan_pct=46}, + {.temp=65, .fan_pct=36}}}" + register "policies.active[1]" = "{.target=DPTF_TSR0, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + register "policies.active[2]" = "{.target=DPTF_TSR1, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + register "policies.active[3]" = "{.target=DPTF_TSR2, .thresholds={ + {.temp=50, .fan_pct=90}, + {.temp=47, .fan_pct=69}, + {.temp=45, .fan_pct=56}, + {.temp=42, .fan_pct=46}, + {.temp=39, .fan_pct=36}}}" + + ## Passive Policy + register "policies.passive[0]" = "{.source=DPTF_CPU, .target=DPTF_CPU, .temp=95, .period=5000}" + register "policies.passive[1]" = "{.source=DPTF_CPU, .target=DPTF_TSR0, .temp=65, .period=6000}" + register "policies.passive[2]" = "{.source=DPTF_CHARGER, .target=DPTF_TSR1, .temp=65, .period=6000}" + register "policies.passive[3]" = "{.source=DPTF_CPU, .target=DPTF_TSR2, .temp=65, .period=6000}" + + ## Critical Policy + register "policies.critical[0]" = "{.source=DPTF_CPU, .temp=105, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[1]" = "{.source=DPTF_TSR0, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[2]" = "{.source=DPTF_TSR1, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + register "policies.critical[3]" = "{.source=DPTF_TSR2, .temp=75, .type=DPTF_CRITICAL_SUSPEND}" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28s interval + # PL2 is fixed at 64W, avg over 28s interval + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28000, + .time_window_max = 32000, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28000, + .time_window_max = 32000, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + # TSR hysteresis + register "options.tsr[0].hysteresis" = "2" + register "options.tsr[1].hysteresis" = "2" + register "options.tsr[2].hysteresis" = "2" + register "options.tsr[3].hysteresis" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 device pci 06.0 off end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl deleted file mode 100644 index cef895b..0000000 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#define DPTF_CPU_PASSIVE 95 -#define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 85 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 75 -#define DPTF_CPU_ACTIVE_AC3 70 -#define DPTF_CPU_ACTIVE_AC4 65 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 - -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR1_ACTIVE_AC0 50 -#define DPTF_TSR1_ACTIVE_AC1 47 -#define DPTF_TSR1_ACTIVE_AC2 45 -#define DPTF_TSR1_ACTIVE_AC3 42 -#define DPTF_TSR1_ACTIVE_AC4 39 - -#define DPTF_TSR2_SENSOR_ID 1 -#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor 3" -#define DPTF_TSR2_PASSIVE 65 -#define DPTF_TSR2_CRITICAL 75 -#define DPTF_TSR2_ACTIVE_AC0 50 -#define DPTF_TSR2_ACTIVE_AC1 47 -#define DPTF_TSR2_ACTIVE_AC2 45 -#define DPTF_TSR2_ACTIVE_AC3 42 -#define DPTF_TSR2_ACTIVE_AC4 39 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - }, - Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0, - 0, 0, 0 - } -}) - - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on TSR0 sensor */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - - /* Charger Throttle Effect on Charger (TSR1) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on TSR2 sensor */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 15000, /* PowerLimitMinimum */ - 60000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl deleted file mode 100644 index 189cafe..0000000 --- a/src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl deleted file mode 100644 index 726e381..0000000 --- a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,7 +0,0 @@ -/* - * - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include <baseboard/acpi/dptf.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/41895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Gerrit-Change-Number: 41895 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4
by Brandon Breitenstein (Code Review) 12 Jul '20

12 Jul '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41543 ) Change subject: mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ...................................................................... mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4. BUG=b:149186922 Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/intel/tglrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/41543/1 diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index d60918f..edbd486 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_TIGERLAKE select INTEL_LPSS_UART_FOR_CONSOLE select DRIVERS_INTEL_ISH + select PCIEXP_HOTPLUG config CHROMEOS bool @@ -49,6 +50,18 @@ int default 8 +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c00000 # 448 MiB + config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/41543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db Gerrit-Change-Number: 41543 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: [WIP]chromeos: share "EC in RW" GPIO with depthcharge
by Shaunak Saha (Code Review) 12 Jul '20

12 Jul '20

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40861 ) Change subject: [WIP]chromeos: share "EC in RW" GPIO with depthcharge ...................................................................... [WIP]chromeos: share "EC in RW" GPIO with depthcharge BUG=None BRANCH=None TEST=Build and boot TGL RVP. Check recovery works with crossystem recovery_request. Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/mainboard/intel/tglrvp/chromeos.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40861/1 diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index c479c89..0d0d7be 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -13,6 +13,7 @@ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/40861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e Gerrit-Change-Number: 40861 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: mb/google/dedede/var/drawcia: support internal usb camera
by Chen Wisley (Code Review) 12 Jul '20

12 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42929 ) Change subject: mb/google/dedede/var/drawcia: support internal usb camera ...................................................................... mb/google/dedede/var/drawcia: support internal usb camera BUG=none TEST=build drawcia, and check camera can be regconized Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/42929/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 38690f7..bc10e1f 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -1,5 +1,8 @@ chip soc/intel/jasperlake + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -37,6 +40,17 @@ }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/42929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f Gerrit-Change-Number: 42929 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: mb/google/dedede/var/drawcia: Audio support for ALC5682 codec and MX9...
by Chen Wisley (Code Review) 12 Jul '20

12 Jul '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42928 ) Change subject: mb/google/dedede/var/drawcia: Audio support for ALC5682 codec and MX98360A ...................................................................... mb/google/dedede/var/drawcia: Audio support for ALC5682 codec and MX98360A drawcia support ALC5682 codec and MX98360A spk amp BUG=b:158202026 TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/dedede/Kconfig.name M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42928/1 diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 4e2a450..5db6675 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -8,6 +8,7 @@ select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_DRAWCIA bool "Drawcia" diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 3b67510..38690f7 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -61,5 +61,26 @@ device i2c 10 on end end end # I2C 2 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C 4 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)" + device generic 0 on end + end + end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6 Gerrit-Change-Number: 42928 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstage
by Johnny Lin (Code Review) 12 Jul '20

12 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42903 ) Change subject: mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstage ...................................................................... mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstage Read VPD variable 'FSP_LOG' to decide enabling FSP log or not. With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and would be set to enabled if both places cannot find it. Tested=On OCP Delta Lake, use vpd to create and set FSP_LOG and verified the results are expected. Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/romstage.c 1 file changed, 24 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42903/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index f56f7c7..5bca0bd 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_kcs.h> +#include <drivers/vpd/vpd.h> #include <fsp/api.h> #include <FspmUpd.h> #include <soc/romstage.h> @@ -9,6 +10,28 @@ #include "cpxsp_dl_iio.h" #include "ipmi.h" +/* Define the VPD keys for UPD variables that can be overwritten */ +#define FSP_LOG "FSP_LOG" + +/* + * Search for VPD_RW first then VPD_RO for UPD config variables, + * overwrites them from VPD if it's found. + */ +static void mainboard_config_upd(FSPM_UPD *mupd) +{ + uint8_t val; + + /* Send FSP log message to SOL */ + if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) + mupd->FspmConfig.SerialIoUartDebugEnable = val; + else { + printk(BIOS_ERR, "Failed to get VPD %s, default set SerialIoUartDebugEnable to 1\n", + FSP_LOG); + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + } + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; +} + /* Update bifurcation settings according to different Configs */ static void oem_update_iio(FSPM_UPD *mupd) { @@ -54,10 +77,6 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { - /* Send FSP log message to SOL */ - mupd->FspmConfig.SerialIoUartDebugEnable = 1; - mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; - /* Enable only PCH: PCIE[8:11] */ for (uint8_t i = 0; i < 20; i++) { if (i >= 8 && i <= 11) @@ -102,4 +121,5 @@ mainboard_config_gpios(mupd); mainboard_config_iio(mupd); + mainboard_config_upd(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Gerrit-Change-Number: 42903 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Set SkipCpuReplacementCheck for Volteer platform
by Jamie Ryu (Code Review) 12 Jul '20

12 Jul '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42789 ) Change subject: mb/google/volteer: Set SkipCpuReplacementCheck for Volteer platform ...................................................................... mb/google/volteer: Set SkipCpuReplacementCheck for Volteer platform Enable SkipCpuReplacementCheck for Volteer to avoid forced MRC traning Test=build and verified with volteer Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42789/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 705da1d..4deb29d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -63,6 +63,9 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera + # CPU replacement check + register "SkipCpuReplacementCheck" = "1" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" -- To view, visit https://review.coreboot.org/c/coreboot/+/42789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1 Gerrit-Change-Number: 42789 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add Type-C IOM device
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41762 ) Change subject: soc/intel/tigerlake: Add Type-C IOM device ...................................................................... soc/intel/tigerlake: Add Type-C IOM device This adds Type-C IO Manageability Engine device with HID INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600. Kernel IOM driver refers to this memory resource for port operations. BUG=:b:156016218 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3 --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/41762/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index abdcb51..6ae5582 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -130,6 +130,18 @@ Scope (\_SB.PCI0) { + Device (IOM) + { + Name (_HID, "INTC1072") + Name (_DDN, "Intel(R) Tiger Lake IO Manageability Engine") + /* + * IOM preserved MMIO range from 0xFBC10000 to 0xFBC11600. + */ + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) + }) + } + /* * Operation region defined to access the IOM REGBAR. Get the MCHBAR in offset * 0x48 in B0:D0:F0. REGBAR Base address is in offset 0x7110 of MCHBAR. -- To view, visit https://review.coreboot.org/c/coreboot/+/41762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3 Gerrit-Change-Number: 41762 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Configure Type-C IOM base address and size
by John Zhao (Code Review) 12 Jul '20

12 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41759 ) Change subject: soc/intel/tigerlake: Configure Type-C IOM base address and size ...................................................................... soc/intel/tigerlake: Configure Type-C IOM base address and size This adds Type-C IO Manageability engine base address and size. IOM register base is in offset 0x7110 from MCHBAR and its port ID is 0xc1. IOM has base address 0xfbc10000 with size 0x1600. BUG=:b:156016218 TEST=Built and booted on Volteer. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 --- M src/soc/intel/tigerlake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/1 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 282092f..cd964f0 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -84,6 +84,8 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) +#define IOM_BASE_ADDRESS 0xfbc10000 +#define IOM_BASE_SIZE 0x1600 /* * I/O port address space -- To view, visit https://review.coreboot.org/c/coreboot/+/41759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907 Gerrit-Change-Number: 41759 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

7 17

Change in coreboot[master]: mb/asrock/b85m_pro4: Reduce Super I/O ACPI code
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42430 ) Change subject: mb/asrock/b85m_pro4: Reduce Super I/O ACPI code ...................................................................... mb/asrock/b85m_pro4: Reduce Super I/O ACPI code We only need ACPI for the PS/2 devices. Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/acpi/superio.asl 1 file changed, 1 insertion(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42430/1 diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl index 4bdb4b9..ee2eabe 100644 --- a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -1,12 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#define SUPERIO_DEV SIO0 -#define SUPERIO_PNP_BASE 0x2e -#define NCT6776_SHOW_PP -#define NCT6776_SHOW_SP1 -#define NCT6776_SHOW_KBC -#define NCT6776_SHOW_HWM - -#undef NCT6776_SHOW_GPIO - -#include <superio/nuvoton/nct6776/acpi/superio.asl> +#include <drivers/pc80/pc/ps2_controller.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/42430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Gerrit-Change-Number: 42430 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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