coreboot-gerrit June 2020

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Change in coreboot[master]: mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m
by Maxim Polyakov (Code Review) 11 Jul '20

11 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42919 ) Change subject: mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m ...................................................................... mb/supermicro/x11-lga1151: 5/5 Rewrite pad config using intelp2m Take into account the remapping of reset sources [1] for the Sunrice Point PCH, to fix Reset Config fields (bit 31:30) in the corresponding macros. The intelp2m utility does this remapping automatically, but these changes in a separate patch to pay attention to them. [1] src/soc/intel/skylake/gpio.c#n9 Change-Id: I388d39ca8314de60610588223d024e1bb1681264 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42919/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index d005d8b..114095a 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -284,7 +284,7 @@ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, ACPI), /* GPP_D23 - GPIO */ PAD_NC(GPP_D23, NONE), @@ -398,7 +398,7 @@ PAD_NC(GPP_F22, NONE), /* GPP_F23 - GPIO */ - PAD_CFG_GPO(GPP_F23, 0, PWROK), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), /* GPP_G0 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h index 4f16424..df13a21 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h @@ -298,7 +298,7 @@ PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), /* GPP_D22 - GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PWROK, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, RSMRST, OFF, DRIVER), /* GPP_D23 - GPIO */ PAD_NC(GPP_D23, NONE), @@ -416,7 +416,7 @@ PAD_NC(GPP_F22, NONE), /* GPP_F23 - GPIO */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, PWROK, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), /* GPIO Group GPP_G */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I388d39ca8314de60610588223d024e1bb1681264 Gerrit-Change-Number: 42919 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: soc/amd/picasso: Switch to using xhci common block
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41901 ) Change subject: soc/amd/picasso: Switch to using xhci common block ...................................................................... soc/amd/picasso: Switch to using xhci common block BUG=b:154756391 TEST=Boot trembyle and look at ACPI table Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/acpi/sb_pci0_fch.asl D src/soc/amd/picasso/acpi/usb.asl D src/soc/amd/picasso/usb.c 5 files changed, 1 insertion(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/41901/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ddbc6c3..0b17c25 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -40,6 +40,7 @@ select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_XHCI select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d0046ea..d1ff319 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -56,7 +56,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c ramstage-$(CONFIG_PICASSO_UART) += uart.c -ramstage-y += usb.c ramstage-y += tsc_freq.c ramstage-y += finalize.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 751c178..c7c424f 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -27,8 +27,6 @@ Name(_ADR, 0x00140000) } /* end SBUS */ -#include "usb.asl" - /* 0:14.2 - I2S Audio */ /* 0:14.3 - LPC */ diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl deleted file mode 100644 index f902100..0000000 --- a/src/soc/amd/picasso/acpi/usb.asl +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:12.0 - EHCI */ -Device(EHC0) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() { 0xb, 3 }) - Device (RHUB) { - Name (_ADR, Zero) - Device (HS01) { Name (_ADR, 1) } - Device (HS02) { Name (_ADR, 2) } - Device (HS03) { Name (_ADR, 3) } - Device (HS04) { Name (_ADR, 4) } - Device (HS05) { Name (_ADR, 5) } - Device (HS06) { Name (_ADR, 6) } - Device (HS07) { Name (_ADR, 7) } - Device (HS08) { Name (_ADR, 8) } - } - - Method(_S0W,0) { - Return(0) - } - - Method(_S3W,0) { - Return(4) - } - - Method(_S4W,0) { - Return(4) - } -} /* end EHC0 */ - - -/* 0:10.0 - XHCI 0*/ -Device(XHC0) { - Name(_ADR, 0x00100000) - Name(_PRW, Package() { 0xb, 3 }) - Device (SS01) { Name (_ADR, 1) } - Device (SS02) { Name (_ADR, 2) } - Device (SS03) { Name (_ADR, 3) } - - Method(_S0W,0) { - Return(0) - } - - Method(_S3W,0) { - Return(4) - } - - Method(_S4W,0) { - Return(4) - } - -} /* end XHC0 */ diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c deleted file mode 100644 index a507956..0000000 --- a/src/soc/amd/picasso/usb.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include <soc/acpi.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> - -static void picasso_usb_init(struct device *dev) -{ - /* USB overcurrent configuration is programmed inside the FSP */ - - printk(BIOS_DEBUG, "%s\n", __func__); -} - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = picasso_usb_init, - .scan_bus = scan_static_bus, - .acpi_name = soc_acpi_name, - .ops_pci = &lops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, - PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, - PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, - 0 -}; - -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 Gerrit-Change-Number: 41901 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41900 ) Change subject: soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes ...................................................................... soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes We can use xhci_for_each_ext_cap to inspect the xHC so we generate the correct number of device nodes. BUG=b:154756391 TEST=Boot trembyle and look at ACPI table. See all xHCI nodes. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1 --- A src/soc/amd/common/block/xhci/Kconfig A src/soc/amd/common/block/xhci/Makefile.inc A src/soc/amd/common/block/xhci/xhci.c 3 files changed, 128 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/41900/1 diff --git a/src/soc/amd/common/block/xhci/Kconfig b/src/soc/amd/common/block/xhci/Kconfig new file mode 100644 index 0000000..5751907 --- /dev/null +++ b/src/soc/amd/common/block/xhci/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_XHCI + bool + default n + help + Select this option to use AMD common xhci driver support. diff --git a/src/soc/amd/common/block/xhci/Makefile.inc b/src/soc/amd/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..2387450 --- /dev/null +++ b/src/soc/amd/common/block/xhci/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_XHCI) += xhci.c diff --git a/src/soc/amd/common/block/xhci/xhci.c b/src/soc/amd/common/block/xhci/xhci.c new file mode 100644 index 0000000..72bb9bb --- /dev/null +++ b/src/soc/amd/common/block/xhci/xhci.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <amdblocks/gpio_banks.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_ehci.h> +#include <soc/acpi.h> +#include <soc/pci_devs.h> +#include <soc/smi.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <device/xhci.h> + +#define XHCI_GEVENT GEVENT_31 + +struct port_counts { + unsigned int high_speed; + unsigned int super_speed; +}; + +static void handle_xhci_ext_cap(void *context, const struct xhci_ext_cap *cap) +{ + const struct xhci_supported_protocol *data; + const char *format; + char buf[16]; + struct port_counts *counts = context; + unsigned int *dev_num; + + if (cap->cap_id != XHCI_ECP_CAP_ID_SUPP) + return; + + data = &cap->supported_protocol; + + if (memcmp(data->name, "USB ", 4)) { + printk(BIOS_INFO, "%s: Unknown Protocol: %.*s\n", __func__, + (int)sizeof(data->name), data->name); + return; + } + + if (data->major_rev == 3) { + format = "SS%02d"; + dev_num = &counts->super_speed; + } else if (data->major_rev == 2) { + format = "HS%02d"; + dev_num = &counts->high_speed; + } else { + printk(BIOS_INFO, "%s: Unknown USB Version: %#x\n", __func__, data->major_rev); + return; + } + + for (unsigned int i = 0; i < data->port_count; ++i) { + snprintf(buf, sizeof(buf), format, ++(*dev_num)); + acpigen_write_device(buf); + acpigen_write_name_byte("_ADR", data->port_offset + i); + acpigen_pop_len(); + } +} + +static void xhci_add_devices(const struct device *device) +{ + struct port_counts counts = {0, 0}; + + acpigen_write_device("RHUB"); + acpigen_write_name_integer("_ADR", 0x00000000); + + xhci_for_each_ext_cap(device, &counts, handle_xhci_ext_cap); + + /* Exit RHUB device */ + acpigen_pop_len(); +} + +static void xhci_fill_ssdt_generator(const struct device *device) +{ + printk(BIOS_INFO, "xHCI SSDT generation\n"); + + /* Write SSDT entry for xHCI controller */ + acpigen_write_scope(acpi_device_scope(device)); + acpigen_write_device(acpi_device_name(device)); + acpigen_write_ADR_pci_device(device); + acpigen_write_STA(acpi_device_status(device)); + acpigen_write_PRW(XHCI_GEVENT, 3); + + xhci_add_devices(device); + + acpigen_write_name_integer("_S0W", 0); + acpigen_write_name_integer("_S3W", 4); + acpigen_write_name_integer("_S4W", 4); + + acpigen_pop_len(); // xHCI device + + acpigen_pop_len(); // Bridge scope +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, + .acpi_fill_ssdt = xhci_fill_ssdt_generator, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0, + PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1, + PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0, + 0 +}; + +static const struct pci_driver usb_0_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/41900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1 Gerrit-Change-Number: 41900 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: mb/google/zork: Enable xHCI Gevents
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41973 ) Change subject: mb/google/zork: Enable xHCI Gevents ...................................................................... mb/google/zork: Enable xHCI Gevents This allows the xHCI to wake the system from S3. BUG=b:154756391 TEST=Boot trembyle and inspect the smi registers. S3 doesn't currently work upstream, so I can't fully test. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41973/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index b5b2847..d7a2db8 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/smi.h> +#include <soc/xhci.h> #include <stdlib.h> #include <boardid.h> #include <variant/gpio.h> @@ -225,6 +226,15 @@ return gpio_set_stage_ram; } +static const struct sci_source gpe_table[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI. Normally this function @@ -234,5 +244,6 @@ */ const __weak struct sci_source *get_gpe_table(size_t *num) { - return NULL; + *num = ARRAY_SIZE(gpe_table); + return gpe_table; } diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 6101330..456ac40 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> #include <soc/smi.h> +#include <soc/xhci.h> #include <stdlib.h> #include <boardid.h> #include <variant/gpio.h> @@ -234,6 +235,21 @@ return gpio_set_stage_ram; } +static const struct sci_source gpe_table[] = { + { + .scimap = SMITYPE_XHC0_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + }, + { + .scimap = SMITYPE_XHC1_PME, + .gpe = XHCI_GEVENT, + .direction = SMI_SCI_LVL_HIGH, + .level = SMI_SCI_EDG + } +}; + /* * This function is still needed for boards that sets gevents above 23 * that will generate SCI or SMI. Normally this function @@ -243,5 +259,6 @@ */ const __weak struct sci_source *get_gpe_table(size_t *num) { - return NULL; + *num = ARRAY_SIZE(gpe_table); + return gpe_table; } -- To view, visit https://review.coreboot.org/c/coreboot/+/41973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 Gerrit-Change-Number: 41973 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

7 23

Change in coreboot[master]: mb/google/zork: Disable unsupported SOC usb ports
by Rob Barnes (Code Review) 10 Jul '20

10 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42800 ) Change subject: mb/google/zork: Disable unsupported SOC usb ports ...................................................................... mb/google/zork: Disable unsupported SOC usb ports Disable USB ports that are not supported by the SOC. Handles Dali, Picasso and Pollock. BUG=b:158096224 TEST=Boot Picasso Ezkinil, observe ports disabled Change-Id: Ie37e2ac6a3a26edf77823193e592310eb10b9f9c Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/soc/amd/picasso/chip.c 1 file changed, 30 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42800/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index c510efe..fb5fb98 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -9,6 +9,7 @@ #include <soc/data_fabric.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> #include "chip.h" #include <fsp/api.h> @@ -127,12 +128,40 @@ } } +/** + * Disables USB ports not supported on the SOC variant. + */ +static void disable_unsupported_usb_ports(void) { + struct device *bus_a, *xhci0, *xhci1, *hub, *port; + + bus_a = pcidev_path_on_root(PCI_DEVFN(8, 1)); + xhci0 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,3)); + hub = xhci0->link_list->children; + port = NULL; + while ((port = dev_bus_each_child(hub->link_list, port)) != NULL) { + unsigned int port_id = port->path.usb.port_id; + /* Picasso SOC only has 4 USB ports on XHCI0 */ + if(!soc_is_raven2() && port->enabled && port_id > 3) { + printk(BIOS_INFO,"Disabling XHCI0 USB port %s because it is not supported on this SOC\n", dev_path(port)); + dev_set_enabled(port, 0); + } + } + + xhci1 = pcidev_path_behind(bus_a->link_list, PCI_DEVFN(0,4)); + hub = xhci1->link_list->children; + /* Dali and Pollock do not have USB ports on XHCI1 */ + if(soc_is_raven2() && hub->enabled) { + printk(BIOS_INFO,"Disabling XHCI1 USB hub because it is not supported on this SOC\n"); + disable_children(hub->bus); + } +} + static void soc_init(void *chip_info) { default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; fsp_silicon_init(acpi_is_wakeup_s3()); - + disable_unsupported_usb_ports(); data_fabric_set_mmio_np(); southbridge_init(chip_info); } -- To view, visit https://review.coreboot.org/c/coreboot/+/42800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie37e2ac6a3a26edf77823193e592310eb10b9f9c Gerrit-Change-Number: 42800 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: arch/x86/exception: Print stack on exception
by Raul Rangel (Code Review) 10 Jul '20

10 Jul '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42884 ) Change subject: arch/x86/exception: Print stack on exception ...................................................................... arch/x86/exception: Print stack on exception It's useful to see the stack when an exception happens so you can see the variables on the stack, and also manually recreate the back trace. If you need to recreate the back trace, you will need to add -fno-omit-frame-pointer to the CFLAGS. BUG=b:159081993 TEST=Caused an exception and saw the stack dumped. Then I manually recreated the back trace. 0xcc6fff6c: 0xcc6ce02e <- 0xcc6ce02e is in dev_initialize 0xcc6fff68: 0xcc6fff88 <-- frame 1 0xcc6fff64: 0x00000005 0xcc6fff60: 0x000000dc 0xcc6fff5c: 0x00000000 0xcc6fff58: 0x00000200 0xcc6fff54: 0x00000000 0xcc6fff50: 0x00000400 0xcc6fff4c: 0xcc6d72d4 <- 0xcc6d72d4 is in setup_default_ebdad 0xcc6fff48: 0xcc6fff68 <-ebp 0xcc6fff44: 0x00000005 0xcc6fff40: 0xcc6f571c <-esp Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef --- M src/arch/x86/exception.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/42884/1 diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 46ba370..3a921c0 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -517,7 +517,18 @@ printk(BIOS_EMERG, "\n%p:\t", code + i); printk(BIOS_EMERG, "%.2x ", code[i]); } - die(""); + + /* Align to 4-byte boundary and up the stack. */ + u32 *ptr = (u32 *)(((uintptr_t)info->esp & ~0x3) + MDUMP_SIZE - 4); + for (i = 0; i < MDUMP_SIZE / sizeof(u32); ++i, --ptr) { + printk(BIOS_EMERG, "\n%p:\t0x%08x", ptr, *ptr); + if ((uintptr_t)ptr == info->ebp) + printk(BIOS_EMERG, " <-ebp"); + else if ((uintptr_t)ptr == info->esp) + printk(BIOS_EMERG, " <-esp"); + } + + die("\n"); #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/42884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef Gerrit-Change-Number: 42884 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Avoid NULL pointer dereference
by John Zhao (Code Review) 10 Jul '20

10 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42837 ) Change subject: soc/amd/picasso: Avoid NULL pointer dereference ...................................................................... soc/amd/picasso: Avoid NULL pointer dereference Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. BUG=CID 1429980 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 --- M src/soc/amd/picasso/root_complex.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42837/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..807e205 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -134,8 +134,11 @@ static void root_complex_fill_ssdt(const struct device *device) { msr_t msr; + const char *scope = acpi_device_scope(device); + if (!scope) + return; - acpigen_write_scope(acpi_device_scope(device)); + acpigen_write_scope(scope); msr = rdmsr(TOP_MEM); acpigen_write_name_dword("TOM1", msr.lo); -- To view, visit https://review.coreboot.org/c/coreboot/+/42837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 Gerrit-Change-Number: 42837 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/sandybridge: Remove unused <model_206ax.h>
by HAOUAS Elyes (Code Review) 10 Jul '20

10 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42351 ) Change subject: nb/sandybridge: Remove unused <model_206ax.h> ...................................................................... nb/sandybridge: Remove unused <model_206ax.h> Change-Id: I05a0a968f39e88aa8e05c8124f6390a943429840 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/sandybridge.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42351/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1652b09..43d460b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <cpu/intel/model_206ax/model_206ax.h> /* Chipset types */ enum platform_type { -- To view, visit https://review.coreboot.org/c/coreboot/+/42351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05a0a968f39e88aa8e05c8124f6390a943429840 Gerrit-Change-Number: 42351 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix/Makefile.inc: Sort entries
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42649 ) Change subject: sb/intel/i82801ix/Makefile.inc: Sort entries ...................................................................... sb/intel/i82801ix/Makefile.inc: Sort entries Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/Makefile.inc 1 file changed, 16 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42649/1 diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 5844b91..91ac65b 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -2,31 +2,32 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y) -ramstage-y += i82801ix.c +bootblock-y += bootblock.c +bootblock-y += early_init.c + +romstage-y += dmi_setup.c +romstage-y += early_init.c +romstage-y += early_smbus.c + ramstage-y += fadt.c -ramstage-y += pci.c -ramstage-y += lpc.c -ramstage-y += pcie.c -ramstage-y += usb_ehci.c -ramstage-y += sata.c ramstage-y += hdaudio.c -ramstage-y += thermal.c +ramstage-y += i82801ix.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c +smm-y += smihandler.c + ifeq ($(CONFIG_SMM_ASEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S endif -smm-y += smihandler.c - -bootblock-y += bootblock.c -bootblock-y += early_init.c - -romstage-y += early_init.c -romstage-y += early_smbus.c -romstage-y += dmi_setup.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4 Gerrit-Change-Number: 42649 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/Makefile.inc: Sort entries
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42648 ) Change subject: sb/intel/i82801jx/Makefile.inc: Sort entries ...................................................................... sb/intel/i82801jx/Makefile.inc: Sort entries Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/Makefile.inc 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/42648/1 diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 253a5a1..8edbf4f 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -5,23 +5,23 @@ bootblock-y += bootblock.c bootblock-y += early_init.c -ramstage-y += i82801jx.c +romstage-y += early_init.c +romstage-y += early_smbus.c + ramstage-y += fadt.c -ramstage-y += pci.c -ramstage-y += lpc.c -ramstage-y += pcie.c -ramstage-y += usb_ehci.c -ramstage-y += sata.c ramstage-y += hdaudio.c -ramstage-y += thermal.c +ramstage-y += i82801jx.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c ramstage-y += smbus.c +ramstage-y += thermal.c +ramstage-y += usb_ehci.c ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c smm-y += smihandler.c -romstage-y += early_init.c -romstage-y += early_smbus.c - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Gerrit-Change-Number: 42648 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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