coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/lynxpoint/me_9.x.c: Drop dead code
by Angel Pons (Code Review) 10 Jul '20

10 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42628 ) Change subject: sb/intel/lynxpoint/me_9.x.c: Drop dead code ...................................................................... sb/intel/lynxpoint/me_9.x.c: Drop dead code Those functions are not being build-tested. Drop them. Change-Id: I285c82712389ef7857001d339e4f8e37537d4199 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/me_9.x.c 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42628/1 diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index cdae271..77b3573 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -515,32 +515,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -static int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { @@ -892,22 +866,6 @@ (me.buffer_depth - 1); } -#if 0 -/* This function is not yet being used, keep it in for the future. */ -static u32 host_to_me_words_room(void) -{ - struct mei_csr csr; - - read_me_csr(&csr); - if (!csr.ready) - return 0; - - read_host_csr(&csr); - return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & - (csr.buffer_depth - 1); -} -#endif - struct mbp_payload { mbp_header header; u32 data[0]; -- To view, visit https://review.coreboot.org/c/coreboot/+/42628 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I285c82712389ef7857001d339e4f8e37537d4199 Gerrit-Change-Number: 42628 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Add Super I/O GPIO table
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42404 ) Change subject: mb/asrock/b85m_pro4: Add Super I/O GPIO table ...................................................................... mb/asrock/b85m_pro4: Add Super I/O GPIO table Information taken from the boardviews. We are not configuring any GPIO in bootblock, but we may want to do so in the future. Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42404/1 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index ad2a4c3..3bf4c3e 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -9,6 +9,41 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) +/* + * Asrock B85M Pro4 Super I/O GPIOs + * + * +------+-----+---------------------------+ + * | GPIO | Pin | Description | + * +------+-----+---------------------------+ + * | GP00 | 2 | N/C | + * | GP01 | 4 | CPU Fan 4-pin tach enable | + * | GP02 | 5 | CPU Fan 3-pin tach enable | + * | GP03 | 8 | CPU Fan 3-pin FON# signal | + * | GP04 | 9 | N/C | + * | GP05 | 11 | N/C (+1.05V_PCH_GPIO) | + * | GP06 | 12 | N/C (+1.5V_PCH_GPIO) | + * | GP07 | 13 | N/C | + * +------+-----+---------------------------+ + * | GP10 | 123 | N/C (VCCM_OV1) | + * | GP11 | 122 | N/C (VCCM_OV2) | + * | GP12 | 121 | N/C (VCCM_OV3) | + * | GP13 | 120 | N/C (VCCM_STEP) | + * | GP14 | 119 | Assert HDA_SDO (SIO_GP14) | + * | GP15 | 118 | N/C (PWM_THROTTLE) | + * | GP16 | 117 | OTP for VCORE (OTE_GATE1) | + * | GP17 | 116 | N/C (IMON_GPIO) | + * +------+-----+---------------------------+ + * | GP70 | 93 | PWR_FANIN | + * | GP71 | 92 | N/C | + * | GP72 | 91 | N/C (SIO_PIN91) | + * | GP73 | 90 | CHA2_FANIN | + * | GP74 | 89 | N/C (SIO_PIN89) | + * | GP75 | 88 | N/C (SIO_PIN88) | + * | GP76 | 87 | HDA reset gate (GP76) | + * | GP77 | 86 | HDD_LED gate | + * +------+-----+---------------------------+ + */ + void mainboard_config_superio(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); -- To view, visit https://review.coreboot.org/c/coreboot/+/42404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Gerrit-Change-Number: 42404 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Properly select muxed functions
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42403 ) Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ...................................................................... mb/asrock/b85m_pro4: Properly select muxed functions The old values were completely out of whack. Use the same settings as vendor firmware. Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42403/1 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52..ad2a4c3 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV); -- To view, visit https://review.coreboot.org/c/coreboot/+/42403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Gerrit-Change-Number: 42403 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: post_code: reorganize order of postcode defines
by Sindhoor Tilak (Code Review) 09 Jul '20

09 Jul '20

Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42606 ) Change subject: post_code: reorganize order of postcode defines ...................................................................... post_code: reorganize order of postcode defines Currently, the certain postcode values aren't in increasing order of values. The change, just reorganzies the defines in increasing order of the values Signed-off-by: Sindhoor Tilak <sindhoor(a)sin9yt.net> Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 --- M src/include/console/post_codes.h 1 file changed, 31 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42606/1 diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 0c6655c..ee74dcb 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -59,7 +59,6 @@ */ #define POST_RAMSTAGE_IS_PREPARED 0x12 - /** * \brief Entry into c_start * @@ -84,21 +83,6 @@ #define POST_MEM_PREINIT_PREP_END 0x36 /** - * \brief Pre call to RAM stage main() - * - * POSTed right before RAM stage main() is called from c_start.S - */ -#define POST_PRE_HARDWAREMAIN 0x79 - -/** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - -/** * \brief Console is initialized * * The console is initialized and is ready for usage @@ -191,6 +175,21 @@ #define POST_BS_WRITE_TABLES 0x79 /** + * \brief Pre call to RAM stage main() + * + * POSTed right before RAM stage main() is called from c_start.S + */ +#define POST_PRE_HARDWAREMAIN 0x79 + +/** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** * \brief Load Payload * * Boot State Machine: bs_payload_load() @@ -303,22 +302,6 @@ #define POST_FSP_MULTI_PHASE_SI_INIT_EXIT 0xa1 /** - * \brief Entry into elf boot - * - * This POST code is called right before invoking jmp_to_elf_entry() - * jmp_to_elf_entry() invokes the payload, and should never return - */ -#define POST_ENTER_ELF_BOOT 0xf8 - -/** - * \brief Jumping to payload - * - * Called right before jumping to a payload. If the boot sequence stops with - * this code, chances are the payload freezes. - */ -#define POST_JUMPING_TO_PAYLOAD 0xf3 - -/** * \brief Invalid or corrupt ROM * * Set if firmware failed to find or validate a resource that is stored in ROM. @@ -387,6 +370,22 @@ #define POST_RESUME_FAILURE 0xef /** + * \brief Jumping to payload + * + * Called right before jumping to a payload. If the boot sequence stops with + * this code, chances are the payload freezes. + */ +#define POST_JUMPING_TO_PAYLOAD 0xf3 + +/** + * \brief Entry into elf boot + * + * This POST code is called right before invoking jmp_to_elf_entry() + * jmp_to_elf_entry() invokes the payload, and should never return + */ +#define POST_ENTER_ELF_BOOT 0xf8 + +/** * \brief Final code before OS resumes * * Called right before jumping to the OS resume vector. -- To view, visit https://review.coreboot.org/c/coreboot/+/42606 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f0ddc4593f689829ab9a7fdeebd5f66939bf79 Gerrit-Change-Number: 42606 Gerrit-PatchSet: 1 Gerrit-Owner: Sindhoor Tilak <sindhoor(a)sin9yt.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: chromeos: remove get_write_protect_state function
by Joel Kitching (Code Review) 09 Jul '20

09 Jul '20

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39340 ) Change subject: chromeos: remove get_write_protect_state function ...................................................................... chromeos: remove get_write_protect_state function Remove the only use of this function from mrc_cache.c, meaning that SPI flash protection is solely determined by SPI itself. We should consider removing VBOOT_NO_BOARD_SUPPORT in a subsequent patch. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Iea461262bf6ae5cd7b7dd74b3287e1bbc813efbb Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/drivers/mrc_cache/mrc_cache.c M src/ec/lenovo/h8/vboot.c M src/include/bootmode.h M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cheza/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/dedede/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/drallion/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/hatch/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/kahlee/chromeos.c M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/octopus/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/rambi/chromeos.c M src/mainboard/google/reef/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/trogdor/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/google/volteer/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/jasperlake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/intel/tglrvp/chromeos.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/security/vboot/Kconfig M src/security/vboot/bootmode.c 60 files changed, 5 insertions(+), 382 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39340/1 diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d4a4aab..2881a6f 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -426,7 +426,6 @@ static int nvm_is_write_protected(void) { u8 sr1; - u8 wp_gpio; u8 wp_spi; if (!CONFIG(CHROMEOS)) @@ -435,9 +434,6 @@ if (!CONFIG(BOOT_DEVICE_SPI_FLASH)) return 0; - /* Read Write Protect GPIO if available */ - wp_gpio = get_write_protect_state(); - /* Read Status Register 1 */ if (spi_flash_status(boot_device_spi_flash(), &sr1) < 0) { printk(BIOS_ERR, "Failed to read SPI status register 1\n"); @@ -445,10 +441,9 @@ } wp_spi = !!(sr1 & 0x80); - printk(BIOS_DEBUG, "SPI flash protection: WPSW=%d SRP0=%d\n", - wp_gpio, wp_spi); + printk(BIOS_DEBUG, "SPI flash protection: SRP0=%d\n", wp_spi); - return wp_gpio && wp_spi; + return wp_spi; } /* Apply protection to a range of flash */ diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c index 3b9f74a..c2e57dc 100644 --- a/src/ec/lenovo/h8/vboot.c +++ b/src/ec/lenovo/h8/vboot.c @@ -44,12 +44,3 @@ return h8_get_fn_key(); } - -/** - * Only used if CONFIG_CHROMEOS is set. - * Always zero as the #WP pin of the flash is tied high. - */ -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 3ae8746..c7ee355 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -18,7 +18,6 @@ /* functions implemented per mainboard: */ void init_bootmode_straps(void); -int get_write_protect_state(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); int clear_recovery_mode_switch(void); diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index a3174b5..f8f016c 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -30,11 +30,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index cbe3c72..4d42bbd 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -39,12 +39,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 10b4618..f9dc6de 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -45,11 +45,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(WP_GPIO); -} - int get_lid_switch(void) { return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 6f713fe..e20f1b1 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -17,11 +17,6 @@ #include <bootmode.h> #include "board.h" -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 9b3b5c0..6de959f 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -20,12 +20,6 @@ #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -/* The WP status pin lives on MF_ISH_GPIO_4 */ -#define WP_STATUS_PAD_CFG0 0x4838 -#define WP_STATUS_PAD_CFG1 0x483C - -#define WP_GPIO GP_E_22 - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 @@ -39,34 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ -#if ENV_ROMSTAGE - if (CONFIG(BOARD_GOOGLE_CYAN)) { - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), - (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), - PAD_CONFIG1_DEFAULT0); - } else { - gpio_input_pullup(WP_GPIO); - } -#endif - - /* WP is enabled when the pin is reading high. */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) - & PAD_VAL_HIGH); - } else { - return !!gpio_get(WP_GPIO); - } -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index e24d8b1..745f084 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -45,8 +45,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_D16); -} diff --git a/src/mainboard/google/dedede/chromeos.c b/src/mainboard/google/dedede/chromeos.c index c2729a1..a8c1e16 100644 --- a/src/mainboard/google/dedede/chromeos.c +++ b/src/mainboard/google/dedede/chromeos.c @@ -22,12 +22,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 2982a20..8dfaec9 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -34,12 +34,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/drallion/chromeos.c b/src/mainboard/google/drallion/chromeos.c index c584bcb..637405f 100644 --- a/src/mainboard/google/drallion/chromeos.c +++ b/src/mainboard/google/drallion/chromeos.c @@ -72,11 +72,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8b40ddd..c3d4740 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -33,12 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index c57fa7e..1ed20c8 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -33,12 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index dc7b738..05d9e86 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -45,8 +45,3 @@ return 0; #endif } - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 5c5a20c..7636ce7 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -165,8 +165,3 @@ { return get_switch_state() == wipeout_req; } - -int get_write_protect_state(void) -{ - return !read_gpio(get_wp_status_gpio_pin()); -} diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 5b340db..a705b09 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index 05930dd..17a981f 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -21,14 +21,6 @@ #include "board.h" -static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ? - ACTIVE_LOW : ACTIVE_HIGH; - -int get_write_protect_state(void) -{ - return gpio_get(GPIO_WP) ^ !wp_polarity; -} - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c index 151977c..363988c 100644 --- a/src/mainboard/google/hatch/chromeos.c +++ b/src/mainboard/google/hatch/chromeos.c @@ -33,11 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *cros_gpios; diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b16e325b..672e88f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -40,12 +40,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 3be023e..8e2a7b2 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !gpio_get(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index b001c81..347e154 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -41,11 +41,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} - int tis_plat_irq_status(void) { return gpio_eint_poll(CR50_IRQ); diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index f7f39de..9693e01 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -36,11 +36,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(57); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 710c9e1..57d5fb8 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 697b7b1..04ff0a0 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 697b7b1..04ff0a0 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO(R1)); -} diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index c0b2571..3c54f33 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -42,8 +42,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT); -} diff --git a/src/mainboard/google/octopus/chromeos.c b/src/mainboard/google/octopus/chromeos.c index 795dcb1..9025b17 100644 --- a/src/mainboard/google/octopus/chromeos.c +++ b/src/mainboard/google/octopus/chromeos.c @@ -33,11 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index d60bd53..deb92af 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -49,11 +49,6 @@ return get_gpio(15); } -int get_write_protect_state(void) -{ - return !get_gpio(70); -} - int get_recovery_mode_switch(void) { u8 gpio = !get_gpio(68); diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index c229ed6..a82f50f 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -45,8 +45,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get_value(GPIO_X30); -} diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 34aad93..65abe65 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -38,12 +38,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index ebced06..38a69d6 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -31,22 +31,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. - */ - if (ENV_ROMSTAGE) - ssus_disable_internal_pull(WP_STATUS_PAD); - - /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 681008d..4dcd036 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 9077d86..0e135cb 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -70,11 +70,6 @@ chromeos_acpi_gpio_generate(cros_gpios, num_gpios); } -int get_write_protect_state(void) -{ - return cros_get_gpio_value(CROS_GPIO_WP); -} - int get_recovery_mode_switch(void) { static enum rec_mode_state saved_rec_mode = REC_MODE_UNINITIALIZED; diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index a3245de..f0621ee 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -29,11 +29,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return get_gpio(58); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 8f76f11..1d8c737 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -27,8 +27,3 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } - -int get_write_protect_state(void) -{ - return !gpio_get(WRITE_PROTECT_L); -} diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index 744572e..dcc08a8 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -136,8 +136,3 @@ { return get_switch_state() == wipeout_req; } - -int get_write_protect_state(void) -{ - return !read_gpio(WP_SW); -} diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 482de98..73b4621 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -45,11 +45,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return !get_gpio(7); -} - int get_lid_switch(void) { /* hard-code to open */ diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 6f713fe..e20f1b1 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -17,11 +17,6 @@ #include <bootmode.h> #include "board.h" -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP_STATE); -} - void setup_chromeos_gpios(void) { gpio_input_pullup(GPIO_EC_IN_RW); diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index e1e232b..e14e2e5 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -64,8 +64,3 @@ return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 79ca8ef..f0c9a03 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -42,8 +42,3 @@ { return !gpio_get(GPIO_RECOVERY); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 21c741f..7898f56 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -52,8 +52,3 @@ return !(gpio_get(GPIO_RECOVERY_SERVO) && gpio_get(GPIO_RECOVERY_PUSHKEY)); } - -int get_write_protect_state(void) -{ - return !gpio_get(GPIO_WP); -} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c index 2bcb4ec..86edb71 100644 --- a/src/mainboard/google/volteer/chromeos.c +++ b/src/mainboard/google/volteer/chromeos.c @@ -24,12 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 72886d2..c00168f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -47,12 +47,6 @@ return get_gpio(69); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(22); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 6815193..5020e9b 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -42,12 +42,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 55669bb..0933fe6 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -41,12 +41,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index ebf51e3..cd0ed02 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -44,12 +44,6 @@ return !get_gpio(22); } -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(48); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index 3ec5bb3..fda7431 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -29,12 +29,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* Not write protected */ - return 0; -} - void verstage_mainboard_init(void) { const struct reg_script *script; diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 1cf3580..b71022c 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -32,11 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index be1e291..0882e88 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -41,12 +41,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.c b/src/mainboard/intel/jasperlake_rvp/chromeos.c index 930f748..6ad0b39 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.c +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.c @@ -40,12 +40,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index d7b9837..c47301b 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -61,12 +61,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index ffdfa37..ea7c519 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -32,12 +32,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 654906f..1bf2934 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -33,22 +33,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - /* - * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ -#if ENV_ROMSTAGE - gpio_input_pullup(WP_GPIO); -#endif - - /* WP is enabled when the pin is reading high. */ - return !!gpio_get(WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c index 930f748..6ad0b39 100644 --- a/src/mainboard/intel/tglrvp/chromeos.c +++ b/src/mainboard/intel/tglrvp/chromeos.c @@ -40,12 +40,6 @@ return 0; } -int get_write_protect_state(void) -{ - /* No write protect */ - return 0; -} - void mainboard_chromeos_acpi_generate(void) { const struct cros_gpio *gpios; diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index d64d9ef..16ea993 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -37,11 +37,6 @@ return REC_MODE_SETTING; } -int get_write_protect_state(void) -{ - return 0; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 5b58144..95a2ecf 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -54,12 +54,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 36efb8a..90fcc1c 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -50,12 +50,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -int get_write_protect_state(void) -{ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e366cc4..6ffb065 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -220,10 +220,9 @@ bool "Allow the use of vboot without board support" default n help - Enable weak functions for get_write_protect_state and - get_recovery_mode_switch in order to proceed with refactoring - of the vboot2 code base. Later on this code is removed and replaced - by interfaces. + Enable weak function for get_recovery_mode_switch in order to + proceed with refactoring of the vboot2 code base. Later on this + code is removed and replaced by interfaces. config RO_REGION_ONLY string "Additional files that should not be copied to RW" diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 2363bf9..78c4320 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -77,15 +77,6 @@ } #if CONFIG(VBOOT_NO_BOARD_SUPPORT) -/** - * TODO: Create flash protection interface which implements get_write_protect_state. - * get_recovery_mode_switch should be implemented as default function. - */ -int __weak get_write_protect_state(void) -{ - return 0; -} - int __weak get_recovery_mode_switch(void) { return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea461262bf6ae5cd7b7dd74b3287e1bbc813efbb Gerrit-Change-Number: 39340 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: src: Update more makefiles to exclude files from psp_verstage
by Martin Roth (Code Review) 09 Jul '20

09 Jul '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42808 ) Change subject: src: Update more makefiles to exclude files from psp_verstage ...................................................................... src: Update more makefiles to exclude files from psp_verstage These are files controlled by options that aren't needed for psp_verstage. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I63942ad896d205c327d65bb8083da817b972962b --- M src/drivers/pc80/rtc/Makefile.inc M src/soc/amd/common/block/acpimmio/Makefile.inc 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/42808/1 diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index c0dd127..33d97c0 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_ARCH_X86),y) bootblock-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c -verstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c +verstage_x86-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c postcar-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc_boot.c @@ -13,14 +13,14 @@ smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c bootblock-$(CONFIG_USE_OPTION_TABLE) += option.c -verstage-$(CONFIG_USE_OPTION_TABLE) += option.c +verstage_x86-$(CONFIG_USE_OPTION_TABLE) += option.c postcar-$(CONFIG_USE_OPTION_TABLE) += option.c romstage-$(CONFIG_USE_OPTION_TABLE) += option.c ramstage-$(CONFIG_USE_OPTION_TABLE) += option.c smm-$(CONFIG_USE_OPTION_TABLE) += option.c bootblock-$(CONFIG_CMOS_POST) += post.c -verstage-$(CONFIG_CMOS_POST) += post.c +verstage_x86-$(CONFIG_CMOS_POST) += post.c postcar-$(CONFIG_CMOS_POST) += post.c romstage-$(CONFIG_CMOS_POST) += post.c ramstage-$(CONFIG_CMOS_POST) += post.c diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 69253b9..553d9e2 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -6,7 +6,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/42808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63942ad896d205c327d65bb8083da817b972962b Gerrit-Change-Number: 42808 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeup
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42431 ) Change subject: mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeup ...................................................................... mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeup This results in a wake from S5 as well. Since the PS/2 keyboard now works, this behavior is annoying and, therefore, undesired. Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42431/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index a5c275d..a044d0a 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -96,7 +96,6 @@ irq 0xe0 = 0xff # + GPIO7 direction end device pnp 2e.a on # ACPI - irq 0xe0 = 0x41 # + Enable KBC wakeup irq 0xe4 = 0x10 # + Power RAM in S3 irq 0xf0 = 0x20 end -- To view, visit https://review.coreboot.org/c/coreboot/+/42431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978 Gerrit-Change-Number: 42431 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/asrock/b85m_pro4: Correct GP01 output level
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42402 ) Change subject: mb/asrock/b85m_pro4: Correct GP01 output level ...................................................................... mb/asrock/b85m_pro4: Correct GP01 output level This allows the CPU fan tach signal to reach the Super I/O. Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42402/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index cb7df0a..a5c275d 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -79,7 +79,7 @@ device pnp 2e.8 off end # WDT device pnp 2e.108 on # GPIO0 irq 0xe0 = 0xf9 # + GPIO0 direction - irq 0xe1 = 0xfb # + GPIO0 value + irq 0xe1 = 0xfd # + GPIO0 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base -- To view, visit https://review.coreboot.org/c/coreboot/+/42402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae Gerrit-Change-Number: 42402 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42401 ) Change subject: mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree ...................................................................... mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree Otherwise, there are complaints about it from the allocator. Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/42401/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 54234e0..cb7df0a 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -103,6 +103,7 @@ device pnp 2e.b on # HWM, LED irq 0x30 = 0xe1 # + Fan RPM sense pins io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 end device pnp 2e.d off end # VID device pnp 2e.e off end # CIR wake-up -- To view, visit https://review.coreboot.org/c/coreboot/+/42401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Gerrit-Change-Number: 42401 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/asrock/b85m_pro4: Correct Super I/O GPIOs
by Angel Pons (Code Review) 08 Jul '20

08 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42400 ) Change subject: mb/asrock/b85m_pro4: Correct Super I/O GPIOs ...................................................................... mb/asrock/b85m_pro4: Correct Super I/O GPIOs GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings under the correct PnP device. Confirmed findings against boardviews. Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb 1 file changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42400/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 0655a32..54234e0 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -80,20 +80,21 @@ device pnp 2e.108 on # GPIO0 irq 0xe0 = 0xf9 # + GPIO0 direction irq 0xe1 = 0xfb # + GPIO0 value - irq 0xf0 = 0xf1 # + GPIO1 direction - irq 0xf1 = 0xf1 # + GPIO1 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base - device pnp 2e.109 on end # GPIO1 - device pnp 2e.209 on # GPIO2 - irq 0xe0 = 0xff # + GPIO2 direction + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value end + device pnp 2e.209 off end # GPIO2 device pnp 2e.309 off end # GPIO3 device pnp 2e.409 off end # GPIO4 device pnp 2e.509 off end # GPIO5 device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end device pnp 2e.a on # ACPI irq 0xe0 = 0x41 # + Enable KBC wakeup irq 0xe4 = 0x10 # + Power RAM in S3 -- To view, visit https://review.coreboot.org/c/coreboot/+/42400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Gerrit-Change-Number: 42400 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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