coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: soc/amd/common: Determine # of I2C controllers at runtime
by Felix Held (Code Review) 07 Jul '20

07 Jul '20

Hello Raul Rangel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/40247 to review the following change. Change subject: soc/amd/common: Determine # of I2C controllers at runtime ...................................................................... soc/amd/common: Determine # of I2C controllers at runtime Dali only has 3 I2C controllers, while Pollock has 5. Both boards use the same socket. So we determine at runtime how many I2C controllers are available. I2C0 and I2C1 are not documented in the PPR, so I took a guess at the addressed. BUG=b:149572620 BRANCH=none TEST=Booted dalboz firmware on trembyle. Saw only three controllers initialized. Touchscreen was still working. Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 --- A src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/iomap.h 6 files changed, 63 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/40247/1 diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h new file mode 100644 index 0000000..f1ffa71 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef __AMDBLOCKS_I2C_H__ +#define __AMDBLOCKS_I2C_H__ + +#include <device/resource.h> + +/* Some systems can only determine the number of i2c controllers at runtime. */ +void soc_update_i2c_resource(struct resource *res); + +#endif /* __AMDBLOCKS_I2C_H__ */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5346356..e84594b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,6 +16,7 @@ #include <pc80/i8259.h> #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> +#include <amdblocks/i2c.h> #include <soc/acpi.h> #include <soc/southbridge.h> #include <soc/nvs.h> @@ -24,6 +25,8 @@ /* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } +void __weak soc_update_i2c_resource(struct resource *res) { } + static void lpc_init(struct device *dev) { u8 byte; @@ -118,12 +121,14 @@ res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* I2C devices (all 4 devices) */ + /* I2C devices */ res = new_resource(dev, 4); res->base = I2C_BASE_ADDRESS; res->size = I2C_DEVICE_SIZE * I2C_DEVICE_COUNT; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + soc_update_i2c_resource(res); + compact_resources(dev); /* Allocate ACPI NVS in CBMEM */ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5cef9ba..0ded6dd 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -42,6 +42,7 @@ bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c +bootblock-y += soc_util.c romstage-y += i2c.c romstage-y += romstage.c diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index b2ff9d8..adc9160 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -9,11 +9,10 @@ #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <arch/acpi_device.h> #include <FspsUpd.h> -#define PICASSO_I2C_DEV_MAX 4 - struct soc_amd_picasso_config { /* * If sb_reset_i2c_slaves() is called, this devicetree register @@ -24,7 +23,7 @@ * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ u8 i2c_scl_reset; - struct dw_i2c_bus_config i2c[PICASSO_I2C_DEV_MAX]; + struct dw_i2c_bus_config i2c[I2C_DEVICE_COUNT]; enum { I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 6bbc7a7..2bd3116 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -7,34 +7,41 @@ #include <delay.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/i2c.h> +#include <soc/i2c.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> -#include <soc/i2c.h> #include "chip.h" /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev); static const uintptr_t i2c_bus_address[] = { + APU_I2C0_BASE, + APU_I2C1_BASE, APU_I2C2_BASE, APU_I2C3_BASE, APU_I2C4_BASE, /* slave device only */ }; +_Static_assert(ARRAY_SIZE(i2c_bus_address) == I2C_DEVICE_COUNT, + "ARRAY_SIZE(i2c_bus_address) must equal I2C_DEVICE_COUNT"); + uintptr_t dw_i2c_base_address(unsigned int bus) { - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(i2c_bus_address)) return 0; - return i2c_bus_address[bus - APU_I2C_MIN_BUS]; + return i2c_bus_address[bus]; } const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; - if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + if (bus >= ARRAY_SIZE(config->i2c)) return NULL; config = get_soc_config(); @@ -47,6 +54,10 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + return "I2C0"; + case APU_I2C1_BASE: + return "I2C1"; case APU_I2C2_BASE: return "I2C2"; case APU_I2C3_BASE: @@ -61,6 +72,10 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { + case APU_I2C0_BASE: + return 0; + case APU_I2C1_BASE: + return 1; case APU_I2C2_BASE: return 2; case APU_I2C3_BASE: @@ -73,6 +88,14 @@ __weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } +/* Pollock has access to I2C0 and I2C1. */ +static unsigned int i2c_start_index(void) +{ + if (soc_is_pollock()) + return 0; + return 2; +} + static void dw_i2c_soc_init(bool is_early_init) { size_t i; @@ -85,7 +108,7 @@ if (config == NULL) return; - for (i = 0; i < ARRAY_SIZE(config->i2c); i++) { + for (i = i2c_start_index(); i < ARRAY_SIZE(config->i2c); i++) { const struct dw_i2c_bus_config *cfg = &config->i2c[i]; if (cfg->early_init != is_early_init) @@ -126,6 +149,15 @@ dw_i2c_soc_init(false); } +void soc_update_i2c_resource(struct resource *res) +{ + unsigned int index = i2c_start_index(); + unsigned int count = ARRAY_SIZE(i2c_bus_address) - index; + + res->base = dw_i2c_base_address(index); + res->size = I2C_DEVICE_SIZE * count; +} + struct device_operations picasso_i2c_mmio_ops = { /* TODO(teravest): Move I2C resource info here. */ .read_resources = DEVICE_NOOP, diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 0a6e1a1..3f539a2 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -18,15 +18,15 @@ /* Reserved 0xfecd1000-0xfedc3fff */ +/* I2C0 and I2C1 are only available on Pollock */ +#define APU_I2C0_BASE 0xfedc2000 +#define APU_I2C1_BASE 0xfedc3000 #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_BASE_ADDRESS APU_I2C0_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 +#define I2C_DEVICE_COUNT 5 #define APU_DMAC0_BASE 0xfedc7000 #define APU_DMAC1_BASE 0xfedc8000 -- To view, visit https://review.coreboot.org/c/coreboot/+/40247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Gerrit-Change-Number: 40247 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

9 28

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and ad...
by Jonathan Zhang (Code Review) 07 Jul '20

07 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42840 ) Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc ...................................................................... vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc CPX-SP FSP ww26 release added UPD to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf --- M src/mainboard/ocp/deltalake/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 3 files changed, 27 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42840/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index b6ea3ec..ebe2c80 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -14,6 +14,10 @@ static void mainboard_config_iio(FSPM_UPD *mupd) { + /* Send FSP log message to SOL */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; + /* Enable only PCH: PCIE[8:11] */ for (uint8_t i = 0; i < 20; i++) { if (i >= 8 && i <= 11) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index fd84f1a..18f8167 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -594,7 +594,7 @@ **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0100 - PchAdrEn +/** Offset 0x0100 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; @@ -633,7 +633,23 @@ **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x0140 +/** Offset 0x0140 - SerialIoUartDebugEnable + Enable SerialIo Uart debug library in FSP. + 0:Disable, 1:Enable +**/ + UINT8 SerialIoUartDebugEnable; + +/** Offset 0x0141 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x0142 - ISA Serial Base selection + Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 + 0x3F8, 0x2F8 +**/ + UINT16 SerialIoUartDebugIoBase; + +/** Offset 0x0144 **/ UINT8 ReservedMemoryInitUpd[16]; } FSP_M_CONFIG; @@ -654,9 +670,9 @@ **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0150 +/** Offset 0x0154 **/ - UINT8 UnusedUpdSpace3[6]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x0156 **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index e9c7dbf..ee86a6d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -85,7 +85,7 @@ /* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ typedef struct SystemMemoryMapHob { - UINT8 reserved1[61]; + UINT8 reserved1[58]; UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. @@ -99,11 +99,11 @@ UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; - UINT8 reserved3[24417]; + UINT8 reserved3[24514]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved4[10]; + UINT8 reserved4[2]; } SYSTEM_MEMORY_MAP_HOB; -- To view, visit https://review.coreboot.org/c/coreboot/+/42840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Gerrit-Change-Number: 42840 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/amd/picasso: Enable eSPI capability for Picasso
by Furquan Shaikh (Code Review) 07 Jul '20

07 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41075 ) Change subject: soc/amd/picasso: Enable eSPI capability for Picasso ...................................................................... soc/amd/picasso: Enable eSPI capability for Picasso This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables the capability for using eSPI on Picasso. BUG=b:153675913,b:154445472 Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/41075/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3d69966..a304819 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ select UDELAY_TSC select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS -- To view, visit https://review.coreboot.org/c/coreboot/+/41075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d Gerrit-Change-Number: 41075 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: vendorcode/google/chromeos: Add vendor_dptf_* functions
by Tim Wawrzynczak (Code Review) 07 Jul '20

07 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41894 ) Change subject: vendorcode/google/chromeos: Add vendor_dptf_* functions ...................................................................... vendorcode/google/chromeos: Add vendor_dptf_* functions This patch adds in the rest of the missing pieces from what is in the static DPTF ASL implementation. Much of it seems written for ChromeOS systems, making assumptions about \_SB.PCI0.LPCB.EC0.* methods that may exist on other systems. Seeing also that they were only used for ChromeOS devices in coreboot, the corresponding generation of the AML was moved to vendorcode/google/chromeos. BUG=b:143539650 TEST=compiles Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/dptf.c 2 files changed, 308 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/41894/1 diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index fc00374..936a298 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -13,6 +13,7 @@ ramstage-$(CONFIG_USE_SAR) += sar.c ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c +ramstage-$(CONFIG_DRIVERS_INTEL_DPTF) += dptf.c bootblock-y += watchdog.c verstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/dptf.c b/src/vendorcode/google/chromeos/dptf.c new file mode 100644 index 0000000..cbf7b48 --- /dev/null +++ b/src/vendorcode/google/chromeos/dptf.c @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpigen_dptf.h> +#include <device/device.h> + +/* DPTF Event types */ +enum { + TRIP_POINTS_CHANGED_EVENT = 0x81, + THERMAL_EVENT = 0x90, +}; + +/* EC constants */ +enum { + EC_FAN_DUTY_AUTO = 0xFF, +}; + +static void write_charger_PPPC(void) +{ + acpigen_write_method_serialized("PPPC", 0); + + /* + * Convert size of PPSS table to index + * + * Store (SizeOf (PPSS), Local0) + * Decrement (Local0) + */ + acpigen_write_store(); + acpigen_emit_byte(SIZEOF_OP); + acpigen_emit_namestring("PPSS"); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL0_OP); + + /* + * Check if charging is disabled (AC removed) + * + * If (\_SB.PCI0.LPCB.EC0.ACEX () = Zero) { + * Return (Local0) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.ACEX"); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* If */ + + /* + * Return highest power state + * + * Return (0) + */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(ZERO_OP); + + acpigen_pop_len(); /* Method */ +} + +static void write_charger_SPPC(void) +{ + /* + * SPPC - Set charger current limit + * Method(SPPC, 1) { + * Store (DeRefOf (Index (DeRefOf (Index + * (PPSS, ToInteger (Arg0))), 4)), Local0) + * \_SB.PCI0.LPCB.EC0.CHGS (Local0) + * } + */ + + acpigen_write_method_serialized("SPPC", 1); + + /* Retrieve Control (index 4) for specified PPSS level */ + acpigen_emit_byte(STORE_OP); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("PPSS"); + acpigen_write_to_integer(ARG0_OP, ZERO_OP); + acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */ + acpigen_write_integer(4); /* Index */ + acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */ + acpigen_emit_byte(LOCAL0_OP); + + /* Pass Control value to EC to limit charging */ + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.CHGS"); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* Method */ +} + +static void write_fan_fst(void) +{ + /* TFST is a package that is used to store data from FAND */ + acpigen_write_name("TFST"); + acpigen_write_package(3); + acpigen_write_integer(0); /* Revision */ + acpigen_write_integer(0); /* Control */ + acpigen_write_integer(0); /* Speed */ + acpigen_pop_len(); /* Package */ + + /* _FST */ + acpigen_write_method_serialized("_FST", 0); + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.FAND"); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("TFST"); + acpigen_write_integer(1); + acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("TFST"); + acpigen_pop_len(); /* Method _FST */ +} + +static void write_fan_fsl(void) +{ + /* _FSL */ + acpigen_write_method_serialized("_FSL", 1); + acpigen_write_store(); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.FAND"); + acpigen_pop_len(); /* Method _FSL */ +} + +/* Note: requires manual insertion of acpigen_pop_len() for the If */ +static void write_is_policy_enabled(unsigned int index, bool enabled) +{ + /* + * If (And (LEqual (Deref (Index (IDSP, index)), Arg0)) + * (LEqual (Arg1, enabled))) + */ + acpigen_write_if(); + acpigen_emit_byte(LAND_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(DEREF_OP); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("IDSP"); + acpigen_write_integer(index); + acpigen_emit_byte(ZERO_OP); /* 3rd arg of index - unused */ + acpigen_emit_byte(ARG0_OP); /* end lequal */ + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG1_OP); + acpigen_write_integer(enabled ? 1 : 0); +} + +static void write_dptf_OSC(bool active_policy_enabled) +{ + /* + * Arg0: Buffer containing UUID + * Arg1: "Integer containing Revision ID of buffer format", but Linux passes whether + * it is enabling (1) or disabling (0) the policy in Arg1. + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + acpigen_write_method_serialized("_OSC", 4); + + /* Is the OS passing us the Passive Policy? */ + write_is_policy_enabled(0, true); + acpigen_emit_namestring("^TINI"); + acpigen_emit_namestring("^TCHG.INIT"); + acpigen_pop_len(); /* If */ + + /* If the Active Policy is disabled, disable DPTF fan control in the EC */ + if (active_policy_enabled) { + write_is_policy_enabled(2, false); + acpigen_write_store(); + acpigen_write_integer(EC_FAN_DUTY_AUTO); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.FAND"); + acpigen_pop_len(); /* If */ + } + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_pop_len(); /* Method _OSC */ +} + +void vendor_dptf_write_dppm_methods(bool active_policy_enabled, bool tsr_en[4]) +{ + enum dptf_participant p; + char name[16]; + int i; + + acpigen_write_scope("\\_SB.DPTF"); + write_dptf_OSC(active_policy_enabled); + + /* TEVT */ + if (CONFIG(EC_SUPPORTS_DPTF_TEVT)) { + acpigen_write_method("TEVT", 0); + + /* Local0 = ToInteger(Arg0) */ + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + for (p = DPTF_TSR0, i = 0; p <= DPTF_TSR3; ++p, ++i) { + if (!tsr_en[i]) + continue; + + snprintf(name, sizeof(name), "^TSR%1d", i); + + /* If (Local0 = i) Notify (TSRx, 0x90) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(i); /* TMPI */ + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(name); + acpigen_write_integer(THERMAL_EVENT); + acpigen_pop_len(); /* If */ + } + + acpigen_pop_len(); /* Method */ + } + + /* TINI */ + acpigen_write_method("TINI", 0); + for (i = 0; i < DPTF_MAX_TSR; ++i) { + if (!tsr_en[i]) + continue; + snprintf(name, sizeof(name), "^TSR%1d.PATD", i); + acpigen_emit_namestring(name); + } + + acpigen_pop_len(); /* Method */ + + /* TPET */ + acpigen_write_method("TPET", 0); + for (p = DPTF_TSR0, i = 0; p <= DPTF_TSR3; ++p, ++i) { + if (!tsr_en[i]) + continue; + + snprintf(name, sizeof(name), "^TSR%1d", i); + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(name); + acpigen_write_integer(TRIP_POINTS_CHANGED_EVENT); + } + + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Scope */ +} + +static void write_charger_init(void) +{ + /* Initialize charger participant */ + acpigen_write_method_serialized("INIT", 0); + + /* Disable charge limit */ + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.CHGD"); + acpigen_pop_len(); /* Method */ +} + +void vendor_dptf_write_charger_methods(void) +{ + dptf_write_scope(DPTF_CHARGER); + + write_charger_PPPC(); + write_charger_SPPC(); + write_charger_init(); + + acpigen_pop_len(); /* Scope */ +} + +void vendor_dptf_write_fan_methods(void) +{ + dptf_write_scope(DPTF_FAN); + + write_fan_fsl(); + write_fan_fst(); + + acpigen_pop_len(); /* Scope */ +} + +void vendor_dptf_write_thermal_methods(int tsr_index) +{ + dptf_write_scope((enum dptf_participant)(DPTF_TSR0 + tsr_index)); + + /* _TMP - read temperature from EC */ + acpigen_write_method_serialized("_TMP", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.TSRD"); + acpigen_emit_namestring("TMPI"); + acpigen_pop_len(); /* Method _TMP */ + + /* PATC - Aux trip point count */ + acpigen_write_name_integer("PATC", 2); + + /* PAT0 - Set Aux trip point 0 */ + acpigen_write_method_serialized("PAT0", 1); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.PAT0"); + acpigen_emit_namestring("TMPI"); + acpigen_emit_byte(ARG0_OP); + acpigen_pop_len(); /* Method PAT0 */ + + /* PAT1 - Set Aux trip point 1 */ + acpigen_write_method_serialized("PAT1", 1); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.PAT1"); + acpigen_emit_namestring("TMPI"); + acpigen_emit_byte(ARG0_OP); + acpigen_pop_len(); /* Method PAT0 */ + + /* PATD - Disable Aux trip point */ + acpigen_write_method_serialized("PATD", 0); + acpigen_emit_namestring("\\_SB.PCI0.LPCB.EC0.PATD"); + acpigen_emit_namestring("TMPI"); + acpigen_pop_len(); /* Method PAT0 */ + + acpigen_pop_len(); /* Scope */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/41894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib30072d1d0748b31bcab240a0fd0e2f12d34aaa4 Gerrit-Change-Number: 41894 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: acpigen: Add acpigen_notify
by Tim Wawrzynczak (Code Review) 07 Jul '20

07 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42102 ) Change subject: acpigen: Add acpigen_notify ...................................................................... acpigen: Add acpigen_notify A fairly common thing in ACPI is notifying a device when some kind of device-specific event happens; this function simplifies writing this pattern. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42102/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index efc5a16..d687a33 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -1953,3 +1953,10 @@ (((uint64_t)address->part_id & 0xffff) << 8) | (((uint64_t)address->class & 0xff))); } + +void acpigen_notify(const char *namestr, int value) +{ + acpigen_emit_byte(NOTIFY_OP); + acpigen_emit_namestring(namestr); + acpigen_write_integer(value); +} diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index dffde85..e0519ab 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -508,4 +508,7 @@ void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); +/* Emits Notify(namestr, value) */ +void acpigen_notify(const char *namestr, int value); + #endif /* __ACPI_ACPIGEN_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f18db9cc836ec9249604452f03ed9b4c6478827 Gerrit-Change-Number: 42102 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/common/block: Add new block DTT
by Tim Wawrzynczak (Code Review) 07 Jul '20

07 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41893 ) Change subject: soc/intel/common/block: Add new block DTT ...................................................................... soc/intel/common/block: Add new block DTT Intel Dynamic Tuning Technology is the name of a PCI device on some Intel SoCs. This minimal PCI driver is only used now for SSDT generation on TGL devices. Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/device/pci_ids.h A src/soc/intel/common/block/dtt/Kconfig A src/soc/intel/common/block/dtt/Makefile.inc A src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/tigerlake/Kconfig 5 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/41893/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 4b17567..054088d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3714,6 +3714,9 @@ #define PCI_DEVICE_ID_GrP_6SERIES_1_WIFI 0x51f0 #define PCI_DEVICE_ID_GrP_6SERIES_2_WIFI 0x7af0 +/* Intel Dynamic Tuning Technology Device */ +#define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 + #define PCI_VENDOR_ID_COMPUTONE 0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 #define PCI_DEVICE_ID_COMPUTONE_PG 0x0302 diff --git a/src/soc/intel/common/block/dtt/Kconfig b/src/soc/intel/common/block/dtt/Kconfig new file mode 100644 index 0000000..063c475 --- /dev/null +++ b/src/soc/intel/common/block/dtt/Kconfig @@ -0,0 +1,7 @@ +config SOC_INTEL_COMMON_BLOCK_DTT + bool + default n + help + Minimal PCI Driver for enabling SSDT generation of Intel + Dynamic Tuning Technology (DTT) policies and controls, also + known as Intel DPTF (Dynamic Platform and Thermal Framework) diff --git a/src/soc/intel/common/block/dtt/Makefile.inc b/src/soc/intel/common/block/dtt/Makefile.inc new file mode 100644 index 0000000..fccccf2 --- /dev/null +++ b/src/soc/intel/common/block/dtt/Makefile.inc @@ -0,0 +1,3 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DTT) += dtt.c + + diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c new file mode 100644 index 0000000..025bbe5 --- /dev/null +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_TGL_DTT, +}; + +static struct device_operations dptf_dev_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_generic_bus, + .ops_pci = &pci_dev_ops_pci, +}; + +static const struct pci_driver pch_dptf __pci_driver = { + .ops = &dptf_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e0d29fb..ab82ea7 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -44,6 +44,7 @@ select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/41893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e Gerrit-Change-Number: 41893 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service
by John Zhao (Code Review) 07 Jul '20

07 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40968 ) Change subject: soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service ...................................................................... soc/intel/tigerlake: Clear TBT PCIe root ports BME at exit boot service Vt-d based security platform requires the system firmware to clear bus master enable(BME) bit for all Thunderbolt PCIe root ports, bridges and devices at exit boot service. In this state with BME bit cleared, the PCI root ports would be considered as trusted to not forward any DMA transaction to download endpoint devices. BUG=141609884 TEST=built image and booted to kernel successfully. Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/tigerlake/chip.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/40968/1 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 073c8d2..a0007f3 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -3,6 +3,7 @@ #include <device/device.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/acpi.h> @@ -15,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <soc/systemagent.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -114,6 +116,48 @@ gpio_pm_configure(value, TOTAL_GPIO_COMM); } +static void clear_tbt_pcie_rp_bme(struct device *dev, uint16_t device_id) +{ + uint16_t reg16; + + if (dev) { + if ((pci_read_config16(dev, PCI_DEVICE_ID) == device_id)) { + reg16 = pci_read_config16(dev, PCI_COMMAND); + + /* Check if BME bit is enabled before */ + if ((reg16 & PCI_COMMAND_MASTER) == PCI_COMMAND_MASTER) { + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); + } + } + } +} + +void platform_fsp_notify_status(enum fsp_notify_phase phase) +{ + if (phase == END_OF_FIRMWARE) { + struct device *dev; + + /* Check if VT-d is enabled */ + dev = pcidev_path_on_root(SA_DEVFN_ROOT); + if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE)) + return; + + /* Clear Thunderbolt PCIe root ports Bus Master Enable(BME) bit */ + dev = pcidev_path_on_root(SA_DEVFN_TBT0); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP0); + + dev = pcidev_path_on_root(SA_DEVFN_TBT1); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP1); + + dev = pcidev_path_on_root(SA_DEVFN_TBT2); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP2); + + dev = pcidev_path_on_root(SA_DEVFN_TBT3); + clear_tbt_pcie_rp_bme(dev, PCI_DEVICE_ID_INTEL_TGL_TBT_RP3); + } +} + void soc_init_pre_device(void *chip_info) { /* Snapshot the current GPIO IRQ polarities. FSP is setting a -- To view, visit https://review.coreboot.org/c/coreboot/+/40968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b Gerrit-Change-Number: 40968 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

15 68

Change in coreboot[4.11_branch]: mb/facebook/watson: select VPD_SMBIOS_VERSION
by Jonathan Zhang (Code Review) 07 Jul '20

07 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42942 ) Change subject: mb/facebook/watson: select VPD_SMBIOS_VERSION ...................................................................... mb/facebook/watson: select VPD_SMBIOS_VERSION Select VPD, GENERATE_SMBIOS_TABLES, VPD_SMBIOS_VERSION so that "firmware_version" key value in RO_VPD is reported in smbios type 0 as BIOS version. TEST=Build coreboot image for WatsonV2, run "vpd -s firmware_version=FB_OSF_1.2 -i RO_VPD -f build/coreboot.rom" command to add firmware_version key value pair in RO_VPD, flash the image to WatsonV2 and reboot it, run dmidecode to verify: [root@localhost ~]# dmidecode -t 0 ... BIOS Information Vendor: coreboot Version: FB_OSF_1.2 ... Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Id559904bfc0afec0668cfaa28303242da4fccf5c temp Change-Id: I31fb2cef01161175a0c01094c5445f7fa340f2d0 --- M src/mainboard/facebook/watson/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/42942/1 diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index f8f93df..2ebc020 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -12,6 +12,7 @@ def_bool y select SOC_INTEL_FSP_BROADWELL_DE select BOARD_ROMSIZE_KB_16384 + select GENERATE_SMBIOS_TABLES select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEGRATED_UART @@ -24,6 +25,8 @@ select VBOOT if BOARD_FACEBOOK_WATSON_V2 select VBOOT_MEASURED_BOOT if BOARD_FACEBOOK_WATSON_V2 select VBOOT_STARTS_IN_ROMSTAGE if BOARD_FACEBOOK_WATSON_V2 + select VPD + select VPD_SMBIOS_VERSION config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/42942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I31fb2cef01161175a0c01094c5445f7fa340f2d0 Gerrit-Change-Number: 42942 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: dptf: Add support for IDSP
by Tim Wawrzynczak (Code Review) 07 Jul '20

07 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42081 ) Change subject: dptf: Add support for IDSP ...................................................................... dptf: Add support for IDSP \_SB.DPTF.IDSP adverties to the DPTF daemon which policies the implementation supports. Added a new acpigen function to figure out which policies are used, and fills out IDSP appropriately. Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 3 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/42081/1 diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index c9131bf..1250539 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -10,6 +10,11 @@ /* Defaults */ #define DEFAULT_RAW_UNIT "ma" +/* DPTF-specific UUIDs */ +#define DPTF_PASSIVE_POLICY_1_0_UUID "42A441D6-AE6A-462B-A84B-4A8CE79027D3" +#define DPTF_CRITICAL_POLICY_UUID "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" +#define DPTF_ACTIVE_POLICY_UUID "3A95C389-E4B8-4629-A526-C52C88626BAE" + enum { ART_REVISION = 0, DEFAULT_PRIORITY = 100, @@ -445,3 +450,40 @@ acpigen_write_name_integer("GTSH", hysteresis); } + +void dptf_write_enabled_policies(const struct dptf_active_policy *active_policies, + int active_count, + const struct dptf_passive_policy *passive_policies, + int passive_count, + const struct dptf_critical_policy *critical_policies, + int critical_count) +{ + bool is_active_used; + bool is_passive_used; + bool is_critical_used; + int pkg_count; + + is_active_used = (active_count && active_policies[0].target != DPTF_NONE); + is_passive_used = (passive_count && passive_policies[0].target != DPTF_NONE); + is_critical_used = (critical_count && critical_policies[0].source != DPTF_NONE); + pkg_count = is_active_used + is_passive_used + is_critical_used; + + if (!pkg_count) + return; + + acpigen_write_scope(TOPLEVEL_DPTF_SCOPE); + acpigen_write_name("IDSP"); + acpigen_write_package(pkg_count); + + if (is_active_used) + acpigen_write_uuid(DPTF_ACTIVE_POLICY_UUID); + + if (is_passive_used) + acpigen_write_uuid(DPTF_PASSIVE_POLICY_1_0_UUID); + + if (is_critical_used) + acpigen_write_uuid(DPTF_CRITICAL_POLICY_UUID); + + acpigen_pop_len(); /* Package */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 52f2221..cdee340 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -64,6 +64,11 @@ for (p = DPTF_TSR0, i = 0; p <= DPTF_TSR3; ++p, ++i) tsr_en[i] = is_participant_used(config, p); + /* Policies */ + dptf_write_enabled_policies(config->policies.active, DPTF_MAX_ACTIVE_POLICIES, + config->policies.passive, DPTF_MAX_PASSIVE_POLICIES, + config->policies.critical, DPTF_MAX_CRITICAL_POLICIES); + dptf_write_active_policies(config->policies.active, DPTF_MAX_ACTIVE_POLICIES); diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 13c904d..d9f66f6 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -127,6 +127,17 @@ }; /* + * This function writes out \_SB.DPTF.IDSP, which describes the different DPTF policies that + * this implementation is using. + */ +void dptf_write_enabled_policies(const struct dptf_active_policy *active_policies, + int active_count, + const struct dptf_passive_policy *passive_policies, + int passive_count, + const struct dptf_critical_policy *critical_policies, + int critical_count); + +/* * This function provides tables of temperature and corresponding fan or percent. When the * temperature thresholds are met (_AC0 - _AC9), the fan is driven to corresponding percentage * of full speed. -- To view, visit https://review.coreboot.org/c/coreboot/+/42081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b Gerrit-Change-Number: 42081 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: dptf: Add support for Fan and TSR options
by Tim Wawrzynczak (Code Review) 07 Jul '20

07 Jul '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41891 ) Change subject: dptf: Add support for Fan and TSR options ...................................................................... dptf: Add support for Fan and TSR options DPTF has several options on how to control the fan (fine-grained speed control, minimum speed change in percentage points, and whether or not the DPTF device should notify the Fan if it detects low speed). Individual TSRs can also set GTSH, which is the amount of hysteresis inherent in the measurement, either from circuitry (if analog), or in firmware (if digital). BUG=b:143539650 TEST=compiles Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen_dptf.h 4 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41891/1 diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index 18b5a6c..745e233 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -460,3 +460,31 @@ acpigen_pop_len(); /* Method */ acpigen_pop_len(); /* Scope */ } + +void dptf_write_STR(enum dptf_participant participant, const char *str) +{ + if (!str) + return; + + acpigen_write_name_string("_STR", str); +} + +void dptf_write_fan_options(bool fine_grained, int step_size, bool low_speed_notify) +{ + acpigen_write_name("_FIF"); + acpigen_write_package(4); + + acpigen_write_integer(0); /* Revision */ + acpigen_write_integer(fine_grained); + acpigen_write_integer(step_size); + acpigen_write_integer(low_speed_notify); + acpigen_pop_len(); /* Package */ +} + +void dptf_write_tsr_hysteresis(uint8_t hysteresis) +{ + if (!hysteresis) + return; + + acpigen_write_name_integer("GTSH", hysteresis); +} diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 5ea32d9..3932968 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -19,6 +19,25 @@ struct dptf_fan_perf fan_perf[DPTF_MAX_FAN_PERF_STATES]; struct dptf_power_limits power_limits; } controls; + + struct { + struct { + /* True means _FSL is percentages, False means _FSL is Control values */ + bool fine_grained_control; + /* Recommended minimum step size in percentage points to adjust fan + * speed when utilizing fine-grained control (1-9) */ + uint8_t step_size; + /* True means the platform will issue a Notify (0x80) to the fan device + * if a a low fan speed is detected */ + bool low_speed_notify; + } fan; + struct { + /* The amount of hysteresis implemented in circuitry or in the platform + * EC's firmware implementation. */ + uint8_t hysteresis; /* GTSH */ + const char *desc; + } tsr[DPTF_MAX_TSR]; + } options; }; #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */ diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 70af050..8c1d8d8 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -57,6 +57,12 @@ static void dptf_fill_ssdt(const struct device *dev) { struct drivers_intel_dptf_config *config = dev->chip_info; + enum dptf_participant p; + bool tsr_en[DPTF_MAX_TSR] = {false}; + int i; + + for (p = DPTF_TSR0, i = 0; p <= DPTF_TSR3; ++p, ++i) + tsr_en[i] = is_participant_used(config, p); /* Policies */ dptf_write_enabled_policies(&config->policies.enabled); @@ -78,6 +84,22 @@ dptf_write_fan_perf(config->controls.fan_perf, DPTF_MAX_FAN_PERF_STATES); dptf_write_power_limits(&config->controls.power_limits); + /* Fan options */ + dptf_write_fan_options(config->options.fan.fine_grained_control, + config->options.fan.step_size, + config->options.fan.low_speed_notify); + + /* TSR options */ + for (p = DPTF_TSR0, i = 0; p <= DPTF_TSR3; ++p, ++i) { + if (tsr_en[i]) { + /* Open scope to the TSR; write GTSH and _STR */ + dptf_write_scope(p); + dptf_write_tsr_hysteresis(config->options.tsr[i].hysteresis); + dptf_write_STR(p, config->options.tsr[i].desc); + acpigen_pop_len(); /* Scope */ + } + } + printk(BIOS_INFO, "\\_SB.DPTF: %s at %s\n", dev->chip_ops->name, dev_path(dev)); } diff --git a/src/include/acpi/acpigen_dptf.h b/src/include/acpi/acpigen_dptf.h index 33a9961..aa355df 100644 --- a/src/include/acpi/acpigen_dptf.h +++ b/src/include/acpi/acpigen_dptf.h @@ -36,6 +36,9 @@ /* From ACPI spec 6.3 */ DPTF_FIELD_UNUSED = 0xFFFFFFFFull, + + /* Max supported by DPTF */ + DPTF_MAX_TSR = 4, }; /* Which policies are enabled? */ @@ -182,6 +185,18 @@ */ void dptf_write_power_limits(const struct dptf_power_limits *limits); +/* Set the _STR Name for the given participant */ +void dptf_write_STR(enum dptf_participant participant, const char *str); + +/* Set options in the _FIF table */ +void dptf_write_fan_options(bool fine_grained, int step_size, bool low_speed_notify); + +/* + * Sets the amount of inherent hysteresis in temperature sensor readings (either from hardware + * circuitry or possibly from the EC's firmware implementation. + */ +void dptf_write_tsr_hysteresis(uint8_t hysteresis); + /* Helper method to open the scope for a given participant. */ void dptf_write_scope(enum dptf_participant participant); -- To view, visit https://review.coreboot.org/c/coreboot/+/41891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb Gerrit-Change-Number: 41891 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020