coreboot-gerrit June 2020

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Change in coreboot[master]: acpi: add STA function to return external variable
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42245 ) Change subject: acpi: add STA function to return external variable ...................................................................... acpi: add STA function to return external variable This change adds support function to add STA function which returns an external variable. Change-Id: I31755a76ee985ee6059289ae194537d531270761 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42245/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 7a507d6..1fd4662 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -742,6 +742,17 @@ acpigen_pop_len(); } +void acpigen_write_STA_ext(const char *ext_val) +{ + /* + * Method (_STA, 0, NotSerialized) { Return (ext_val) } + */ + acpigen_write_method("_STA", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring(ext_val); + acpigen_pop_len(); +} + /* * Generates a func with max supported P-states. */ diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 565abcf..4c26464 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -319,6 +319,7 @@ void acpigen_write_empty_PTC(void); void acpigen_write_PRW(u32 wake, u32 level); void acpigen_write_STA(uint8_t status); +void acpigen_write_STA_ext(const char *ext_val); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); -- To view, visit https://review.coreboot.org/c/coreboot/+/42245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31755a76ee985ee6059289ae194537d531270761 Gerrit-Change-Number: 42245 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/mipi_camera: SSDT changes to handle CIO2 device
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42470 to review the following change. Change subject: drivers/intel/mipi_camera: SSDT changes to handle CIO2 device ...................................................................... drivers/intel/mipi_camera: SSDT changes to handle CIO2 device This change updates mipi_camera driver to handle CIO2 device type. Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/42470/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index ddafccf..bcce7a6 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -10,9 +10,83 @@ #include <device/pci_def.h> #include "chip.h" +#define CIO2_PCI_DEV 0x14 +#define CIO2_PCI_FN 0x3 #define SENSOR_NAME_UUID "822ace8f-2814-4174-a56b-5f029fe079ee" #define SENSOR_TYPE_UUID "26257549-9271-4ca4-bb43-c4899d5a4881" +/* + * This implementation assumes there is only 1 endpoint at each end of every data port. It also + * assumes there are no clock lanes. It also assumes that any VCM or NVM for a CAM is on the + * same I2C bus as the CAM. + */ + +/* + * Adds settings for a CIO2 device (typically at "\_SB.PCI0.CIO2"). A _DSD is added that + * specifies a child table for each port (e.g., PRT0 for "port0" and PRT1 for "port1"). Each + * PRTx table specifies a table for each endpoint (though only 1 endpoint is supported by this + * implementation so the table only has an "endpoint0" that points to a EPx0 table). The EPx0 + * table primarily describes the # of lanes in "data-lines" and specifies the name of the other + * side in "remote-endpoint" (the name is usually of the form "\_SB.PCI0.I2Cx.CAM0" for the + * first port/cam and "\_SB.PCI0.I2Cx.CAM1" if there's a second port/cam). + */ +static void camera_fill_cio2(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + char *ep_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_name[MAX_PORT_ENTRIES] = {NULL}; + unsigned int i, j; + char name[BUS_PATH_MAX]; + struct acpi_dp *ep_table = NULL; + struct acpi_dp *port_table = NULL; + struct acpi_dp *remote = NULL; + struct acpi_dp *lanes = NULL; + + for (i = 0; i < config->cio2_num_ports && i < MAX_PORT_ENTRIES; ++i) { + snprintf(name, sizeof(name), "EP%u0", i); + ep_table_name[i] = strdup(name); + ep_table = acpi_dp_new_table(ep_table_name[i]); + acpi_dp_add_integer(ep_table, "endpoint", 0); + acpi_dp_add_integer(ep_table, "clock-lanes", 0); + + if (config->cio2_lanes_used[i] > 0) { + lanes = acpi_dp_new_table("data-lanes"); + + for (j = 1; j <= config->cio2_lanes_used[i]; ++j) + acpi_dp_add_integer(lanes, NULL, j); + acpi_dp_add_array(ep_table, lanes); + } + + if (config->cio2_lane_endpoint[i]) { + remote = acpi_dp_new_table("remote-endpoint"); + acpi_dp_add_reference(remote, NULL, config->cio2_lane_endpoint[i]); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_array(ep_table, remote); + } + + snprintf(name, sizeof(name), "PRT%u", i); + port_table_name[i] = strdup(name); + port_table = acpi_dp_new_table(port_table_name[i]); + acpi_dp_add_integer(port_table, "port", config->cio2_prt[i]); + acpi_dp_add_child(port_table, "endpoint0", ep_table); + + snprintf(name, sizeof(name), "port%u", i); + port_name[i] = strdup(name); + acpi_dp_add_child(dsd, port_name[i], port_table); + } + + acpi_dp_write(dsd); + + for (i = 0; i < config->cio2_num_ports; ++i) { + free(ep_table_name[i]); + free(port_table_name[i]); + free(port_name[i]); + } +} + static void apply_pld_defaults(struct drivers_intel_mipi_camera_config *config) { if (!config->pld.ignore_color) @@ -142,6 +216,11 @@ static void camera_fill_sensor_defaults(struct drivers_intel_mipi_camera_config *config) { + struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, CIO2_PCI_FN); + struct drivers_intel_mipi_camera_config *cio2_config; + if (!config->ssdb.bdf_value) + config->ssdb.bdf_value = PCI_DEVFN(CIO2_PCI_DEV, CIO2_PCI_FN); + if (!config->ssdb.platform) config->ssdb.platform = PLATFORM_SKC; @@ -156,6 +235,31 @@ if (!config->ssdb.mclk_speed) config->ssdb.mclk_speed = CLK_FREQ_19_2MHZ; + + if (!config->ssdb.lanes_used) { + cio2_config = cio2 ? cio2->chip_info : NULL; + + if (!cio2_config) { + printk(BIOS_ERR, "Failed to get CIO2 config\n"); + } else if (cio2_config->device_type != INTEL_ACPI_CAMERA_CIO2) { + printk(BIOS_ERR, "Device type isn't CIO2: %u\n", + (u32)cio2_config->device_type); + } else if (config->ssdb.link_used >= cio2_config->cio2_num_ports) { + printk(BIOS_ERR, "%u exceeds CIO2's %u links\n", + (u32)config->ssdb.link_used, + (u32)cio2_config->cio2_num_ports); + } else { + config->ssdb.lanes_used = + cio2_config->cio2_lanes_used[config->ssdb.link_used]; + } + } + + if (!config->remote_name) { + if (cio2) + config->remote_name = acpi_device_path(cio2); + else + config->remote_name = "\\_SB.PCI0.CIO2"; + } } /* @@ -409,6 +513,9 @@ } switch (config->device_type) { + case INTEL_ACPI_CAMERA_CIO2: + camera_fill_cio2(dev); + break; case INTEL_ACPI_CAMERA_SENSOR: camera_fill_sensor(dev); break; diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 95a3ebb..82223c1 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -127,6 +127,12 @@ const char *chip_name; unsigned int acpi_uid; + /* Settings specific to CIO2 device */ + uint32_t cio2_num_ports; + uint32_t cio2_lanes_used[MAX_PORT_ENTRIES]; + const char *cio2_lane_endpoint[MAX_PORT_ENTRIES]; + uint32_t cio2_prt[MAX_PORT_ENTRIES]; + /* Settings specific to camera sensor */ bool disable_ssdb_defaults; -- To view, visit https://review.coreboot.org/c/coreboot/+/42470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I521740524bc1c4da3d8593f011a033542e4a872c Gerrit-Change-Number: 42470 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 28

Change in coreboot[master]: drivers/intel/mipi_camera: SSDT changes to add PLD
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42469 to review the following change. Change subject: drivers/intel/mipi_camera: SSDT changes to add PLD ...................................................................... drivers/intel/mipi_camera: SSDT changes to add PLD This change updates mipi_camera driver to add PLD section to SSDT. Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/42469/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index a3a9323..ddafccf 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -13,6 +13,53 @@ #define SENSOR_NAME_UUID "822ace8f-2814-4174-a56b-5f029fe079ee" #define SENSOR_TYPE_UUID "26257549-9271-4ca4-bb43-c4899d5a4881" +static void apply_pld_defaults(struct drivers_intel_mipi_camera_config *config) +{ + if (!config->pld.ignore_color) + config->pld.ignore_color = 1; + + if (!config->pld.visible) + config->pld.visible = 1; + + if (!config->pld.vertical_offset) + config->pld.vertical_offset = 0xffff; + + if (!config->pld.horizontal_offset) + config->pld.horizontal_offset = 0xffff; + + /* + * PLD_PANEL_TOP has a value of zero, so the following will change any instance of + * PLD_PANEL_TOP to PLD_PANEL_FRONT unless disable_pld_defaults is set. + */ + if (!config->pld.panel) + config->pld.panel = PLD_PANEL_FRONT; + + /* + * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so the following will change any + * instance of that value to PLD_HORIZONTAL_POSITION_CENTER unless disable_pld_defaults + * is set. + */ + if (!config->pld.horizontal_position) + config->pld.horizontal_position = PLD_HORIZONTAL_POSITION_CENTER; + + /* + * The desired default for |vertical_position| is PLD_VERTICAL_POSITION_UPPER, which + * has a value of zero so no work is needed to set a default. The same applies for + * setting |shape| to PLD_SHAPE_ROUND. + */ +} + +static void camera_generate_pld(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + + if (config->use_pld && !config->disable_pld_defaults) + apply_pld_defaults(config); + + if (config->use_pld) + acpigen_write_pld(&config->pld); +} + static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; @@ -140,6 +187,8 @@ const char *vcm_name = NULL; struct acpi_dp *lens_focus = NULL; + camera_generate_pld(dev); + if (!config->disable_ssdb_defaults) camera_fill_sensor_defaults(config); diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index f55ee1d..95a3ebb 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -4,6 +4,7 @@ #define __INTEL_MIPI_CAMERA_CHIP_H__ #include <stdint.h> +#include <acpi/acpi_pld.h> #define MAX_PWDB_ENTRIES 12 #define MAX_PORT_ENTRIES 4 @@ -134,6 +135,9 @@ const char *sensor_name; /* default "UNKNOWN" */ const char *remote_name; /* default "\_SB.PCI0.CIO2" */ const char *vcm_name; /* defaults to |vcm_address| device */ + bool use_pld; + bool disable_pld_defaults; + struct acpi_pld pld; uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */ /* Settings specific to nvram. Many values, if left as zero, will be assigned a default. -- To view, visit https://review.coreboot.org/c/coreboot/+/42469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If65b9cbabca95e9645d8e5023ce7fd78b0625d1e Gerrit-Change-Number: 42469 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: drivers/intel/mipi_camera: SSDT changes to add DSM
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42468 to review the following change. Change subject: drivers/intel/mipi_camera: SSDT changes to add DSM ...................................................................... drivers/intel/mipi_camera: SSDT changes to add DSM This change updates mipi_camera driver to add DSM section to SSDT. Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c 1 file changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/42468/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 81cd968..a3a9323 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -13,6 +13,86 @@ #define SENSOR_NAME_UUID "822ace8f-2814-4174-a56b-5f029fe079ee" #define SENSOR_TYPE_UUID "26257549-9271-4ca4-bb43-c4899d5a4881" +static uint32_t address_for_dev_type(const struct device *dev, uint8_t dev_type) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF; + uint16_t i2c_addr = dev->path.i2c.device; + + switch (dev_type) { + case DEV_TYPE_SENSOR: + return (((uint32_t)i2c_bus) << 24 | ((uint32_t)i2c_addr) << 8 | + dev_type); + case DEV_TYPE_VCM: + return (((uint32_t)i2c_bus) << 24 | ((uint32_t)config->vcm_address) << 8 | + dev_type); + case DEV_TYPE_ROM: + return (((uint32_t)i2c_bus) << 24 | ((uint32_t)config->rom_address) << 8 | + dev_type); + } + + return 0; +} + +static void camera_generate_dsm(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + int local1_ret = (config->ssdb.vcm_type ? 1 : 0) + (config->ssdb.rom_type ? 1 : 0) + 1; + int next_local1 = 1; + /* Method (_DSM, 4, NotSerialized) */ + acpigen_write_method("_DSM", 4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(SENSOR_NAME_UUID); + acpigen_write_return_string(config->sensor_name ? config->sensor_name : "UNKNOWN"); + acpigen_pop_len(); /* If */ + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(SENSOR_TYPE_UUID); + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + + /* If (LEqual (Local1, 1)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++); + acpigen_write_return_integer(local1_ret); + acpigen_pop_len(); /* If Arg2=1 */ + + /* If (LEqual (Local1, 2)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++); + acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_SENSOR)); + acpigen_pop_len(); /* If Arg2=2 */ + + if (config->ssdb.vcm_type) { + /* If (LEqual (Local1, 3)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1++); + acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_VCM)); + acpigen_pop_len(); /* If Arg2=3 */ + } + + if (config->ssdb.rom_type) { + /* If (LEqual (Local1, 3 or 4)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, next_local1); + acpigen_write_return_integer(address_for_dev_type(dev, DEV_TYPE_ROM)); + acpigen_pop_len(); /* If Arg2=3 or 4 */ + } + + acpigen_pop_len(); /* If uuid */ + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Method _DSM */ +} + static void camera_fill_sensor_defaults(struct drivers_intel_mipi_camera_config *config) { if (!config->ssdb.platform) @@ -63,6 +143,9 @@ if (!config->disable_ssdb_defaults) camera_fill_sensor_defaults(config); + /* _DSM */ + camera_generate_dsm(dev); + ep00 = acpi_dp_new_table("EP00"); acpi_dp_add_integer(ep00, "endpoint", 0); acpi_dp_add_integer(ep00, "clock-lanes", 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/42468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic60e972b6aebad171a7b77fe0d99781693adfb20 Gerrit-Change-Number: 42468 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: drivers/intel/mipi_camera: SSDT changes to handle camera sensor
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42467 to review the following change. Change subject: drivers/intel/mipi_camera: SSDT changes to handle camera sensor ...................................................................... drivers/intel/mipi_camera: SSDT changes to handle camera sensor This change updates mipi_camera driver to handle camera sensor. Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 179 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42467/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 955c430..81cd968 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -10,6 +10,141 @@ #include <device/pci_def.h> #include "chip.h" +#define SENSOR_NAME_UUID "822ace8f-2814-4174-a56b-5f029fe079ee" +#define SENSOR_TYPE_UUID "26257549-9271-4ca4-bb43-c4899d5a4881" + +static void camera_fill_sensor_defaults(struct drivers_intel_mipi_camera_config *config) +{ + if (!config->ssdb.platform) + config->ssdb.platform = PLATFORM_SKC; + + if (!config->ssdb.flash_support) + config->ssdb.flash_support = FLASH_DISABLE; + + if (!config->ssdb.privacy_led) + config->ssdb.privacy_led = PRIVACY_LED_A_16mA; + + if (!config->ssdb.mipi_define) + config->ssdb.mipi_define = MIPI_INFO_ACPI_DEFINED; + + if (!config->ssdb.mclk_speed) + config->ssdb.mclk_speed = CLK_FREQ_19_2MHZ; +} + +/* + * Adds settings for a camera sensor device (typically at "\_SB.PCI0.I2Cx.CAMy"). The drivers + * for Linux tends to expect the camera sensor device and any related nvram / vcm devices to be + * separate ACPI devices, while the drivers for Windows want all of these to be grouped + * together in the camera sensor ACPI device. This implementation tries to satisfy both, + * though the unfortunate tradeoff is that the same I2C address for nvram and vcm is advertised + * by multiple devices in ACPI (via "_CRS"). The Windows driver can use the "_DSM" method to + * disambiguate the I2C resources in the camera sensor ACPI device. Drivers for Windows + * typically query "SSDB" for configuration information (represented as a binary blob dump of + * struct), while Linux drivers typically consult individual parameters in "_DSD". + * + * The tree of tables in "_DSD" is analogous to what's used for the "CIO2" device. The _DSD + * specifies a child table for the sensor's port (e.g., PRT0 for "port0"--this implementation + * assumes a camera only has 1 port). The PRT0 table specifies a table for each endpoint + * (though only 1 endpoint is supported by this implementation so the table only has an + * "endpoint0" that points to a EP00 table). The EP00 table primarily describes the # of lanes + * in "data-lines", a list of frequencies in "list-frequencies", and specifies the name of the + * other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2"). + */ +static void camera_fill_sensor(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *ep00 = NULL; + struct acpi_dp *prt0 = NULL; + struct acpi_dp *dsd = NULL; + struct acpi_dp *remote = NULL; + const char *vcm_name = NULL; + struct acpi_dp *lens_focus = NULL; + + if (!config->disable_ssdb_defaults) + camera_fill_sensor_defaults(config); + + ep00 = acpi_dp_new_table("EP00"); + acpi_dp_add_integer(ep00, "endpoint", 0); + acpi_dp_add_integer(ep00, "clock-lanes", 0); + + if (config->ssdb.lanes_used > 0) { + struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); + uint32_t i; + for (i = 1; i <= config->ssdb.lanes_used; ++i) + acpi_dp_add_integer(lanes, NULL, i); + acpi_dp_add_array(ep00, lanes); + } + + if (config->num_freq_entries) { + struct acpi_dp *freq = acpi_dp_new_table("link-frequencies"); + uint32_t i; + for (i = 0; i < config->num_freq_entries && i < MAX_LINK_FREQ_ENTRIES; ++i) + acpi_dp_add_integer(freq, NULL, config->link_freq[i]); + acpi_dp_add_array(ep00, freq); + } + + remote = acpi_dp_new_table("remote-endpoint"); + + acpi_dp_add_reference(remote, NULL, config->remote_name); + acpi_dp_add_integer(remote, NULL, config->ssdb.link_used); + acpi_dp_add_integer(remote, NULL, 0); /* endpoint */ + acpi_dp_add_array(ep00, remote); + + prt0 = acpi_dp_new_table("PRT0"); + + acpi_dp_add_integer(prt0, "port", 0); + acpi_dp_add_child(prt0, "endpoint0", ep00); + dsd = acpi_dp_new_table("_DSD"); + + acpi_dp_add_integer(dsd, "clock-frequency", config->ssdb.mclk_speed); + + if (config->ssdb.degree) + acpi_dp_add_integer(dsd, "rotation", 180); + + if (config->ssdb.vcm_type) { + if (config->vcm_name) { + vcm_name = config->vcm_name; + } else { + const struct device_path path = { + .type = DEVICE_PATH_I2C, + .i2c.device = config->vcm_address, + }; + struct device *vcm_dev = find_dev_path(dev->bus, &path); + struct drivers_intel_mipi_camera_config *vcm_config; + vcm_config = vcm_dev ? vcm_dev->chip_info : NULL; + + if (!vcm_config) + printk(BIOS_ERR, "Failed to get VCM\n"); + else if (vcm_config->device_type != INTEL_ACPI_CAMERA_VCM) + printk(BIOS_ERR, "Device isn't VCM\n"); + else + vcm_name = acpi_device_path(vcm_dev); + } + } + + if (vcm_name) { + lens_focus = acpi_dp_new_table("lens-focus"); + acpi_dp_add_reference(lens_focus, NULL, vcm_name); + acpi_dp_add_array(dsd, lens_focus); + } + + acpi_dp_add_child(dsd, "port0", prt0); + acpi_dp_write(dsd); + + acpigen_write_method_serialized("SSDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, sizeof(config->ssdb)); + acpigen_pop_len(); /* Method */ + + /* Fill Power Sequencing Data */ + if (config->num_pwdb_entries > 0) { + acpigen_write_method_serialized("PWDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, + sizeof(struct intel_pwdb) * + config->num_pwdb_entries); + acpigen_pop_len(); /* Method */ + } +} + static void camera_fill_nvm(const struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; @@ -142,6 +277,9 @@ } switch (config->device_type) { + case INTEL_ACPI_CAMERA_SENSOR: + camera_fill_sensor(dev); + break; case INTEL_ACPI_CAMERA_VCM: camera_fill_vcm(dev); break; diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 5aa2183..f55ee1d 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -6,6 +6,39 @@ #include <stdint.h> #define MAX_PWDB_ENTRIES 12 +#define MAX_PORT_ENTRIES 4 +#define MAX_LINK_FREQ_ENTRIES 4 + +enum camera_device_type { + DEV_TYPE_SENSOR = 0, + DEV_TYPE_VCM, + DEV_TYPE_ROM +}; + +enum intel_camera_platform_type { + PLATFORM_SKC = 9, + PLATFORM_CNL = 10 +}; + +enum intel_camera_flash_type { + FLASH_DEFAULT = 0, + FLASH_DISABLE = 2, + FLASH_ENABLE = 3 +}; + +enum intel_camera_led_type { + PRIVACY_LED_DEFAULT = 0, + PRIVACY_LED_A_16mA +}; + +enum intel_camera_mipi_info { + MIPI_INFO_SENSOR_DRIVER = 0, + MIPI_INFO_ACPI_DEFINED +}; + +#define CLK_FREQ_19_2MHZ 19200000 +#define CLK_FREQ_24MHZ 24000000 +#define CLK_FREQ_20MHZ 20000000 enum intel_camera_device_type { INTEL_ACPI_CAMERA_CIO2, @@ -65,6 +98,7 @@ uint8_t degree; /* Camera Orientation */ uint8_t mipi_define; /* MIPI info defined in ACPI or sensor driver */ + uint32_t mclk_speed; /* Clock info for sensor */ uint32_t mclk; /* Clock info for sensor */ uint8_t control_logic_id; /* PMIC device node used for the camera sensor */ @@ -91,6 +125,13 @@ const char *acpi_name; const char *chip_name; unsigned int acpi_uid; + + /* Settings specific to camera sensor */ + bool disable_ssdb_defaults; + + uint8_t num_freq_entries; /* # of elements in link_freq */ + uint32_t link_freq[MAX_LINK_FREQ_ENTRIES]; + const char *sensor_name; /* default "UNKNOWN" */ const char *remote_name; /* default "\_SB.PCI0.CIO2" */ const char *vcm_name; /* defaults to |vcm_address| device */ uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I581c9bf9b87eac69e88ec11724c3b26ee5fa9431 Gerrit-Change-Number: 42467 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 21

Change in coreboot[master]: drivers/intel/mipi_camera: Handle NVM and VCM device type
by Sugnan Prabhu S (Code Review) 07 Jul '20

07 Jul '20

Hello Matt Delco, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42466 to review the following change. Change subject: drivers/intel/mipi_camera: Handle NVM and VCM device type ...................................................................... drivers/intel/mipi_camera: Handle NVM and VCM device type This change adds support in mipi_camera driver to handle NVM and VCM device types. Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/42466/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 2f4b953..955c430 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -10,6 +10,46 @@ #include <device/pci_def.h> #include "chip.h" +static void camera_fill_nvm(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + + /* It might be possible to default size or width based on type. */ + if (!config->disable_nvm_defaults && !config->nvm_pagesize) + config->nvm_pagesize = 1; + + if (!config->disable_nvm_defaults && !config->nvm_readonly) + config->nvm_readonly = 1; + + if (config->nvm_size) + acpi_dp_add_integer(dsd, "size", config->nvm_size); + + if (config->nvm_pagesize) + acpi_dp_add_integer(dsd, "pagesize", config->nvm_pagesize); + + if (config->nvm_readonly) + acpi_dp_add_integer(dsd, "read-only", config->nvm_readonly); + + if (config->nvm_width) + acpi_dp_add_integer(dsd, "address-width", config->nvm_width); + + acpi_dp_write(dsd); +} + +static void camera_fill_vcm(const struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd; + + if (!config->vcm_compat) + return; + + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "compatible", config->vcm_compat); + acpi_dp_write(dsd); +} + static void write_pci_camera_device(const struct device *dev, const char *scope) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; @@ -100,6 +140,19 @@ config->device_type == INTEL_ACPI_CAMERA_VCM) { acpigen_write_name_integer("CAMD", config->device_type); } + + switch (config->device_type) { + case INTEL_ACPI_CAMERA_VCM: + camera_fill_vcm(dev); + break; + case INTEL_ACPI_CAMERA_NVM: + camera_fill_nvm(dev); + break; + case INTEL_ACPI_CAMERA_IMGU: + case INTEL_ACPI_CAMERA_PMIC: + default: + break; + } } static void camera_fill_ssdt(const struct device *dev) diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index c029570..5aa2183 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -95,6 +95,18 @@ const char *vcm_name; /* defaults to |vcm_address| device */ uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */ + /* Settings specific to nvram. Many values, if left as zero, will be assigned a default. + Set disable_nvm_defaults to non-zero if you want to disable the defaulting behavior + so you can use zero for a value. */ + + bool disable_nvm_defaults; + uint32_t nvm_size; + uint32_t nvm_pagesize; + uint32_t nvm_readonly; + uint32_t nvm_width; + + /* Settings specific to vcm */ + const char *vcm_compat; }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24cb7f010d89bc8d14e0b4c8fe693ba6e9c68941 Gerrit-Change-Number: 42466 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb
by David Wu (Code Review) 07 Jul '20

07 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42302 ) Change subject: mb/google/volteer/var/terrador: update gpio setting and overridetree.cb ...................................................................... mb/google/volteer/var/terrador: update gpio setting and overridetree.cb Based on schematic and gpio table of terrador, generate gpio setting and overridetree.cb for terrador. BUG=b:b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 --- M src/mainboard/google/volteer/variants/terrador/gpio.c M src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h M src/mainboard/google/volteer/variants/terrador/overridetree.cb 3 files changed, 227 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42302/1 diff --git a/src/mainboard/google/volteer/variants/terrador/gpio.c b/src/mainboard/google/volteer/variants/terrador/gpio.c index a54aeca..198d7e1 100644 --- a/src/mainboard/google/volteer/variants/terrador/gpio.c +++ b/src/mainboard/google/volteer/variants/terrador/gpio.c @@ -1,15 +1,156 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> +#include <variant/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> /* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> ESPI_RST_L */ + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A23 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_A23, NONE), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B5 : ISH_I2C0_CVF_SDA ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : ISH_I2C0_CVF_SCL ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C11 : UART0_CTS# ==> NC */ + PAD_NC(GPP_C11, NONE), + + /* D4 : IMGCLKOUT0 ==> NC */ + PAD_NC(GPP_D4, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : SRCCLKREQ2# ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D17 : ISH_GP4 ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : ISH_GP5 ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E2 : SPI1_IO3 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E8 : SPI1_CS1# ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E10 : SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E13 : SPI1_MOSI_IO0 ==> NC */ + PAD_NC(GPP_E13, NONE), + /* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E16, 1, DEEP), + /* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E17, NONE, DEEP, EDGE_SINGLE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F8 : I2S_MCLK2_INOUT ==> NC */ + PAD_NC(GPP_F8, NONE), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F14 : GSXDIN ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + + /* H6 : I2C3_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C3_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H11, NONE), + /* H12 : M2_SKT2_CFG0 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : M2_SKT2_CFG3 # ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : IMGCLKOUT4 ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + /* R6 : I2S1_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD11: LANPHYC ==> NC */ + PAD_NC(GPD11, NONE), }; -const struct pad_config *variant_base_gpio_table(size_t *num) +const struct pad_config *variant_override_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -17,7 +158,38 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), }; const struct pad_config *variant_early_gpio_table(size_t *num) @@ -25,12 +197,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h index 0075826..fe512d8 100644 --- a/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/terrador/include/variant/gpio.h @@ -5,6 +5,8 @@ #include <baseboard/gpio.h> -/* Copied from baseboard and may need to change for the new variant. */ +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 #endif diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 75422d8..24842a1 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -1,4 +1,54 @@ chip soc/intel/tigerlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on end + end + end # I2C #0 0xA0E8 + device pci 1f.3 on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F18)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HD audio 0xA0C8-A0CF end end -- To view, visit https://review.coreboot.org/c/coreboot/+/42302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Gerrit-Change-Number: 42302 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

6 30

Change in coreboot[master]: mb/google/volteer/variants/terrador: Add two SPD files
by David Wu (Code Review) 07 Jul '20

07 Jul '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41995 ) Change subject: mb/google/volteer/variants/terrador: Add two SPD files ...................................................................... mb/google/volteer/variants/terrador: Add two SPD files Adds SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex, which will be used initially for the "MT53E512M64D4NW-046 WT:E" Micron part as DRAM ID #7. Adds SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex, which will be used initially for the "MT53E1G64D8NW-046 WT:E" Micron part as DRAM ID #8. BUG=b:152936481 b:151978872 TEST=build. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c --- M src/mainboard/google/volteer/variants/terrador/Makefile.inc A src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex A src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex 3 files changed, 67 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/41995/1 diff --git a/src/mainboard/google/volteer/variants/terrador/Makefile.inc b/src/mainboard/google/volteer/variants/terrador/Makefile.inc index c9a128d..da23cf7 100644 --- a/src/mainboard/google/volteer/variants/terrador/Makefile.inc +++ b/src/mainboard/google/volteer/variants/terrador/Makefile.inc @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = +## Memory Options # DRAM ID # Part Num +SPD_SOURCES = SPD_LPDDR4X_432b_1R_32Gb_QDP_4267 # b0111 # MT53E512M64D4NW-046 WT:E +SPD_SOURCES += SPD_LPDDR4X_432b_2R_64Gb_ODP_4267 # b0100 # MT53E1G64D8NW-046 WT:E bootblock-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex new file mode 100644 index 0000000..ef177a3 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_1R_32Gb_QDP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B9 08 00 40 00 00 02 01 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex new file mode 100644 index 0000000..2f32372 --- /dev/null +++ b/src/mainboard/google/volteer/variants/terrador/spd/SPD_LPDDR4X_432b_2R_64Gb_ODP_4267.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 F9 08 00 40 00 00 0A 01 00 00 +49 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/41995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c Gerrit-Change-Number: 41995 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: trogdor: Add board variant checks in Kconfig
by Ravi kumar (Code Review) 06 Jul '20

06 Jul '20

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42730 ) Change subject: trogdor: Add board variant checks in Kconfig ...................................................................... trogdor: Add board variant checks in Kconfig Diffentiate Lazor and trogdor build configuration Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc --- M src/mainboard/google/trogdor/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/42730/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index dfd98f0..9f0e037 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -5,7 +5,8 @@ if BOARD_GOOGLE_TROGDOR_COMMON config TROGDOR_REV0 - def_bool y + def_bool y if BOARD_GOOGLE_TROGDOR + def_bool n if BOARD_GOOGLE_LAZOR config BOARD_SPECIFIC_OPTIONS def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/42730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc Gerrit-Change-Number: 42730 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: tests: Add lib/b64_decode-test test case
by Anna Karas (Code Review) 06 Jul '20

06 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42313 ) Change subject: tests: Add lib/b64_decode-test test case ...................................................................... tests: Add lib/b64_decode-test test case Implement unit tests for lib/b64_decode module. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: Id5fe9272e30eaff3d086a95241b3819101089c2b --- M tests/lib/Makefile.inc A tests/lib/b64_decode-test.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/42313/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 61f99bf..abb279c 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,10 @@ # two examples - first should be simply string.c, second should use -wrap tests-y += string-test +tests-y += b64_decode-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c + +b64_decode-test-srcs += tests/lib/b64_decode-test.c +b64_decode-test-srcs += src/lib/b64_decode.c diff --git a/tests/lib/b64_decode-test.c b/tests/lib/b64_decode-test.c new file mode 100644 index 0000000..9426236 --- /dev/null +++ b/tests/lib/b64_decode-test.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stddef.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <b64_decode.h> +#include <tests/test.h> + +struct messages_t { + const char *enc; + const char *dec; +} messages[] = { + {"QQ==", "A"}, + {"QUI=", "AB"}, + {"QUJD", "ABC"}, + {"QUJDRA==", "ABCD"}, + {"SGVsbG8=", "Hello"}, + {"SGVsbG8h", "Hello!"} +}; + +const char *invalid[] = { + "QQ=-=", + "SGVsbG-8=" +}; + +/* Provide necessary definition in order to satisfy dependencies. */ +int do_printk(int msg_level, const char *fmt, ...) { + return 0; +} + +static void test_b64_decode(void **state) +{ + uint8_t *decoded; + size_t res; + + for (int i = 0; i < ARRAY_SIZE(messages); i++) { + decoded = malloc(strlen(messages[i].enc) * sizeof(char)); + + res = b64_decode((uint8_t *)messages[i].enc, strlen(messages[i].enc), decoded); + + assert_int_equal(res, (strlen(messages[i].dec))); + assert_string_equal(decoded, messages[i].dec); + + free(decoded); + } + + for (int i = 0; i < ARRAY_SIZE(invalid); i++) { + decoded = malloc(strlen(invalid[i]) * sizeof(char)); + + res = b64_decode((uint8_t *)invalid[i], strlen(invalid[i]), decoded); + + assert_int_equal(res, 0); + + free(decoded); + } +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_b64_decode), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5fe9272e30eaff3d086a95241b3819101089c2b Gerrit-Change-Number: 42313 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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