coreboot-gerrit June 2020

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Change in coreboot[master]: mb/supermicro/x9scl: Select IPMI_KCS
by Angel Pons (Code Review) 05 Jul '20

05 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41687 ) Change subject: mb/supermicro/x9scl: Select IPMI_KCS ...................................................................... mb/supermicro/x9scl: Select IPMI_KCS Needed for `chip drivers/ipmi` in the devicetree. Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/supermicro/x9scl/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/41687/1 diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig index df6308e..c2e3a37 100644 --- a/src/mainboard/supermicro/x9scl/Kconfig +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -13,6 +13,7 @@ select SUPERIO_NUVOTON_NCT6776_COM_A select SUPERIO_NUVOTON_WPCM450 select MAINBOARD_USES_IFD_GBE_REGION + select IPMI_KCS config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/41687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f Gerrit-Change-Number: 41687 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

7 27

Change in coreboot[master]: drivers/pc80/tpm: Remove support code if TPM is disabled
by Kyösti Mälkki (Code Review) 05 Jul '20

05 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41873 ) Change subject: drivers/pc80/tpm: Remove support code if TPM is disabled ...................................................................... drivers/pc80/tpm: Remove support code if TPM is disabled Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/41873/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..4cc6823 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -993,8 +993,9 @@ static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &lpc_tpm_ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + if (CONFIG(TPM1) || CONFIG(TPM2)) + pnp_enable_devices(dev, &lpc_tpm_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations drivers_pc80_tpm_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/41873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7015d4bf6f536c5cea8e1174db81f09f756ae0e5 Gerrit-Change-Number: 41873 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: [WIP] mb/google/poppy-nocturne: Add SX9310 driver unconditionally
by Kyösti Mälkki (Code Review) 05 Jul '20

05 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41726 ) Change subject: [WIP] mb/google/poppy-nocturne: Add SX9310 driver unconditionally ...................................................................... [WIP] mb/google/poppy-nocturne: Add SX9310 driver unconditionally Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/41726/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 8553821..74b4da6 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -174,7 +174,7 @@ config VARIANT_SPECIFIC_OPTIONS_NOCTURNE def_bool n select CHROMEOS_WIFI_SAR if CHROMEOS - select DRIVERS_I2C_SX9310 if CHROMEOS_WIFI_SAR + select DRIVERS_I2C_SX9310 select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/41726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a Gerrit-Change-Number: 41726 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: util/inteltool: Refactoring #2
by Felix Singer (Code Review) 05 Jul '20

05 Jul '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31634 Change subject: util/inteltool: Refactoring #2 ...................................................................... util/inteltool: Refactoring #2 Change-Id: Ie92a5af141a907251fc847d53c767984949d9312 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/Makefile M util/inteltool/gpio.h A util/inteltool/gpio_test.c A util/inteltool/gpio_test.h 4 files changed, 447 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31634/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d88063b..0097831 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o gpio_test.o \ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h index c89f393..161e9bb 100644 --- a/util/inteltool/gpio.h +++ b/util/inteltool/gpio.h @@ -17,6 +17,36 @@ #ifndef GPIO_H #define GPIO_H + +// Describes a native function +struct native_mode { + uint8_t mode; + char *name; +}; + +/* + * Describes a GPIO pad, which optionally can + * have one or more native functions and a default + * mode. If no default mode is set, + * default_mode to -1, else set it to the + * function number. + */ +struct gpio_pad { + const char *name; + uint8_t default_mode; + const struct native_mode *modes; + uint64_t default_config; + uint64_t config; +}; + +/* +struct gpio_pad { + const char *name; + size_t defaultMode; + const char **functions; +}; +*/ + struct gpio_group { const char *display; size_t pad_count; diff --git a/util/inteltool/gpio_test.c b/util/inteltool/gpio_test.c new file mode 100644 index 0000000..9052623 --- /dev/null +++ b/util/inteltool/gpio_test.c @@ -0,0 +1,66 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> +#include <assert.h> +#include <inttypes.h> +#include "inteltool.h" +#include "pcr.h" +#include "gpio.h" +#include "gpio_test.h" + +#define SBBAR_SIZE (16 * MiB) +#define PCR_PORT_SIZE (64 * KiB) + +void select_gpio_community(struct pci_dev *const sb) +{ + size_t community_count; + const struct gpio_community *const *communities; + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_CM236: +// community_count = ARRAY_SIZE(sunrise_communities); +// communities = sunrise_communities; +// pcr_init(sb); + break; + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: +// community_count = ARRAY_SIZE(sunrise_lp_communities); +// communities = sunrise_lp_communities; +// pcr_init(sb); + break; + case PCI_DEVICE_ID_INTEL_DNV_LPC: +// community_count = ARRAY_SIZE(denverton_communities); +// communities = denverton_communities; +// pcr_init(sb); + break; + default: + return; + } + + printf("\n============= GPIOS =============\n\n"); + +// for (; community_count; --community_count) +// print_gpio_community(*communities++); +} diff --git a/util/inteltool/gpio_test.h b/util/inteltool/gpio_test.h new file mode 100644 index 0000000..9edc4fe --- /dev/null +++ b/util/inteltool/gpio_test.h @@ -0,0 +1,350 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * Copyright (C) 2019 by 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "gpio.h" + +#ifndef GPIO_TEST_H +#define GPIO_TEST_H + +/* +const struct gpio_pad test[] = { + { "gpio1", 2, (const char *[]) { "function1", "function2", NULL, } }, +}; +*/ + +const struct gpio_pad test[] = { + { "GPP_A0", -1, (const struct native_mode[]) { {1, "RCIN#" }, }, }, + { "GPP_A1", -1, (const struct native_mode[]) { {1, "LAD0" }, {3, "ESPI_IO0" }, }, }, + { "GPP_A2", -1, (const struct native_mode[]) { {1, "LAD1" }, {3, "ESPI_IO1" }, }, }, + { "GPP_A3", -1, (const struct native_mode[]) { {1, "LAD2" }, {3, "ESPI_IO2" }, }, }, + { "GPP_A4", -1, (const struct native_mode[]) { {1, "LAD3" }, {3, "ESPI_IO3" }, }, }, + { "GPP_A5", -1, (const struct native_mode[]) { {1, "LFRAME#" }, {3, "ESPI_CS#" }, }, }, + { "GPP_A6", -1, (const struct native_mode[]) { {1, "SERIRQ#" }, }, }, + { "GPP_A7", -1, (const struct native_mode[]) { {1, "PIRQA#" }, }, }, + { "GPP_A8", -1, (const struct native_mode[]) { {1, "CLKRUN#" }, }, }, + { "GPP_A9", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC0" }, {3, "ESPI_CLK" }, }, }, + { "GPP_A10", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC1" }, }, }, + { "GPP_A11", -1, (const struct native_mode[]) { {1, "PME#" }, }, }, + { "GPP_A12", -1, (const struct native_mode[]) { {1, "BM_BUSY#" }, {2, "ISH_GP6" }, {3, "SX_EXIT_HOLDOFF#" }, }, }, + { "GPP_A13", -1, (const struct native_mode[]) { {1, "SUSWARN#/SUSPWRDNACK" }, }, }, + { "GPP_A14", -1, (const struct native_mode[]) { {1, "SUS_STAT#" }, {3, "ESPI_RESET#" }, }, }, + { "GPP_A15", -1, (const struct native_mode[]) { {1, "SUS_ACK#" }, }, }, + { "GPP_A16", -1, (const struct native_mode[]) { {1, "SD_1P8_SEL" }, }, }, + { "GPP_A17", -1, (const struct native_mode[]) { {1, "SD_PWR_EN#" }, {2, "ISH_GP7" }, }, }, + { "GPP_A18", -1, (const struct native_mode[]) { {1, "ISH_GP0" }, }, }, + { "GPP_A19", -1, (const struct native_mode[]) { {1, "ISH_GP1" }, }, }, + { "GPP_A20", -1, (const struct native_mode[]) { {1, "ISH_GP2" }, }, }, + { "GPP_A21", -1, (const struct native_mode[]) { {1, "ISH_GP3" }, }, }, + { "GPP_A22", -1, (const struct native_mode[]) { {1, "ISH_GP4" }, }, }, + { "GPP_A23", -1, (const struct native_mode[]) { {1, "ISH_GP5" }, }, }, +}; + +/* +const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; +*/ +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92a5af141a907251fc847d53c767984949d9312 Gerrit-Change-Number: 31634 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review) 05 Jul '20

05 Jul '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504 Change subject: util/inteltool: Refactor code of GPIO groups ...................................................................... util/inteltool: Refactor code of GPIO groups Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A util/inteltool/gpio.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_sunrise.h 4 files changed, 865 insertions(+), 816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1 diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h new file mode 100644 index 0000000..64f62f8 --- /dev/null +++ b/util/inteltool/gpio.h @@ -0,0 +1,29 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +struct gpio_group { + const char *display; + size_t pad_count; + size_t func_count; + const char *const *pad_names; /* indexed by 'pad * func_count + func' */ +}; + +struct gpio_community { + const char *name; + uint8_t pcr_port_id; + size_t group_count; + const struct gpio_group *const *groups; +}; diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h new file mode 100644 index 0000000..e745b44 --- /dev/null +++ b/util/inteltool/gpio_denverton.h @@ -0,0 +1,237 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const denverton_group_north_all_names[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +static const struct gpio_group denverton_group_north_all = { + .display = "------- GPIO Group North All -------", + .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, + .func_count = 1, + .pad_names = denverton_group_north_all_names, +}; + +static const struct gpio_group *const denverton_community_north_groups[] = { + &denverton_group_north_all, +}; + +static const struct gpio_community denverton_community_north = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xc2, + .group_count = ARRAY_SIZE(denverton_community_north_groups), + .groups = denverton_community_north_groups, +}; + +static const char *const denverton_group_south_dfx_names[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", +}; + +static const struct gpio_group denverton_group_south_dfx = { + .display = "------- GPIO Group South DFX -------", + .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_dfx_names, +}; + +static const char *const denverton_group_south_group0_names[] = { + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", +}; + +static const struct gpio_group denverton_group_south_group0 = { + .display = "------- GPIO Group South Group0 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group0_names, +}; + +static const char *const denverton_group_south_group1_names[] = { + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + +static const struct gpio_group denverton_group_south_group1 = { + .display = "------- GPIO Group South Group1 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group1_names, +}; + +static const struct gpio_group *const denverton_community_south_groups[] = { + &denverton_group_south_dfx, + &denverton_group_south_group0, + &denverton_group_south_group1, +}; + +static const struct gpio_community denverton_community_south = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(denverton_community_south_groups), + .groups = denverton_community_south_groups, +}; + +static const struct gpio_community *const denverton_communities[] = { + &denverton_community_north, &denverton_community_south, +}; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 53a8eb9..c7ab186 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,826 +22,13 @@ #include <inttypes.h> #include "inteltool.h" #include "pcr.h" +#include "gpio.h" +#include "gpio_denverton.h" +#include "gpio_sunrise.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -struct gpio_group { - const char *display; - size_t pad_count; - size_t func_count; - const char *const *pad_names; /* indexed by 'pad * func_count + func' */ -}; - -struct gpio_community { - const char *name; - uint8_t pcr_port_id; - size_t group_count; - const struct gpio_group *const *groups; -}; - -static const char *const sunrise_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "ISH_GP7", "n/a", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_a_names, -}; - -static const char *const sunrise_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "n/a", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "n/a", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_a = { - .display = "------- GPIO group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_a_names, -}; - -static const char *const sunrise_group_b_names[] = { - "GPP_B0", "n/a", "n/a", "n/a", - "GPP_B1", "n/a", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPIO_CS#", "n/a", "n/a", - "GPP_B16", "GSPIO_CLK", "n/a", "n/a", - "GPP_B17", "GSPIO_MISO", "n/a", "n/a", - "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_b_names, -}; - -static const char *const sunrise_lp_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPI0_CS#", "n/a", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_b_names, -}; - -static const struct gpio_group *const sunrise_community_ab_groups[] = { - &sunrise_group_a, &sunrise_group_b, -}; - -static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { - &sunrise_lp_group_a, &sunrise_lp_group_b, -}; - -static const struct gpio_community sunrise_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_community_ab_groups), - .groups = sunrise_community_ab_groups, -}; - -static const struct gpio_community sunrise_lp_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), - .groups = sunrise_lp_community_ab_groups, -}; - -static const char *const sunrise_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "n/a", "n/a", - "GPP_C4", "SML0DATA", "n/a", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", "n/a", - "GPP_C6", "SML1CLK", "n/a", "n/a", - "GPP_C7", "SML1DATA", "n/a", "n/a", - "GPP_C8", "UART0_RXD", "n/a", "n/a", - "GPP_C9", "UART0_TXD", "n/a", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", - "GPP_C16", "I2C0_SDA", "n/a", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", "n/a", - "GPP_C20", "UART2_RXD", "n/a", "n/a", - "GPP_C21", "UART2_TXD", "n/a", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_c_names, -}; - -static const char *const sunrise_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "n/a", - "GPP_D1", "n/a", "n/a", "n/a", - "GPP_D2", "n/a", "n/a", "n/a", - "GPP_D3", "n/a", "n/a", "n/a", - "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", - "GPP_D5", "I2S_SFRM", "n/a", "n/a", - "GPP_D6", "I2S_TXD", "n/a", "n/a", - "GPP_D7", "I2S_RXD", "n/a", "n/a", - "GPP_D8", "I2S_SCLK", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "n/a", - "GPP_D22", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", -}; - -static const struct gpio_group sunrise_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_d_names, -}; - -static const char *const sunrise_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "n/a", - "GPP_D1", "SPI1_CLK", "n/a", "n/a", - "GPP_D2", "SPI1_MISO", "n/a", "n/a", - "GPP_D3", "SPI1_MOSI", "n/a", "n/a", - "GPP_D4", "FLASHTRIG", "n/a", "n/a", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_d_names, -}; - -static const char *const sunrise_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATA_LED#", "n/a", "n/a", - "GPP_E9", "USB_OC0#", "n/a", "n/a", - "GPP_E10", "USB_OC1#", "n/a", "n/a", - "GPP_E11", "USB_OC2#", "n/a", "n/a", - "GPP_E12", "USB_OC3#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const sunrise_lp_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATALED#", "n/a", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", "n/a", - "GPP_E13", "DDPB_HPD0", "n/a", "n/a", - "GPP_E14", "DDPC_HPD1", "n/a", "n/a", - "GPP_E15", "DDPD_HPD2", "n/a", "n/a", - "GPP_E16", "DDPE_HPD3", "n/a", "n/a", - "GPP_E17", "EDP_HPD", "n/a", "n/a", - "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_E22", "n/a", "n/a", "n/a", - "GPP_E23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_e_names, -}; - -static const char *const sunrise_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", - "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", - "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", - "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", - "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "n/a", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_f_names, -}; - -static const char *const sunrise_lp_group_f_names[] = { - "GPP_F0", "I2S2_SCLK", "n/a", "n/a", - "GPP_F1", "I2S2_SFRM", "n/a", "n/a", - "GPP_F2", "I2S2_TXD", "n/a", "n/a", - "GPP_F3", "I2S2_RXD", "n/a", "n/a", - "GPP_F4", "I2C2_SDA", "n/a", "n/a", - "GPP_F5", "I2C2_SCL", "n/a", "n/a", - "GPP_F6", "I2C3_SDA", "n/a", "n/a", - "GPP_F7", "I2C3_SCL", "n/a", "n/a", - "GPP_F8", "I2C4_SDA", "n/a", "n/a", - "GPP_F9", "I2C4_SCL", "n/a", "n/a", - "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", - "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", - "GPP_F12", "EMMC_CMD", "n/a", "n/a", - "GPP_F13", "EMMC_DATA0", "n/a", "n/a", - "GPP_F14", "EMMC_DATA1", "n/a", "n/a", - "GPP_F15", "EMMC_DATA2", "n/a", "n/a", - "GPP_F16", "EMMC_DATA3", "n/a", "n/a", - "GPP_F17", "EMMC_DATA4", "n/a", "n/a", - "GPP_F18", "EMMC_DATA5", "n/a", "n/a", - "GPP_F19", "EMMC_DATA6", "n/a", "n/a", - "GPP_F20", "EMMC_DATA7", "n/a", "n/a", - "GPP_F21", "EMMC_RCLK", "n/a", "n/a", - "GPP_F22", "EMMC_CLK", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_f_names, -}; - -static const char *const sunrise_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "n/a", "n/a", - "GPP_G1", "FAN_TACH_1", "n/a", "n/a", - "GPP_G2", "FAN_TACH_2", "n/a", "n/a", - "GPP_G3", "FAN_TACH_3", "n/a", "n/a", - "GPP_G4", "FAN_TACH_4", "n/a", "n/a", - "GPP_G5", "FAN_TACH_5", "n/a", "n/a", - "GPP_G6", "FAN_TACH_6", "n/a", "n/a", - "GPP_G7", "FAN_TACH_7", "n/a", "n/a", - "GPP_G8", "FAN_PWM_0", "n/a", "n/a", - "GPP_G9", "FAN_PWM_1", "n/a", "n/a", - "GPP_G10", "FAN_PWM_2", "n/a", "n/a", - "GPP_G11", "FAN_PWM_3", "n/a", "n/a", - "GPP_G12", "GSXDOUT", "n/a", "n/a", - "GPP_G13", "GSXSLOAD", "n/a", "n/a", - "GPP_G14", "GSXDIN", "n/a", "n/a", - "GPP_G15", "GSXRESET#", "n/a", "n/a", - "GPP_G16", "GSXCLK", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "n/a", "n/a", - "GPP_G21", "n/a", "n/a", "n/a", - "GPP_G22", "n/a", "n/a", "n/a", - "GPP_G23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_g_names, -}; - -static const char *const sunrise_lp_group_g_names[] = { - "GPP_G0", "SD_CMD", "n/a", "n/a", - "GPP_G1", "SD_DATA0", "n/a", "n/a", - "GPP_G2", "SD_DATA1", "n/a", "n/a", - "GPP_G3", "SD_DATA2", "n/a", "n/a", - "GPP_G4", "SD_DATA3", "n/a", "n/a", - "GPP_G5", "SD_CD#", "n/a", "n/a", - "GPP_G6", "SD_CLK", "n/a", "n/a", - "GPP_G7", "SD_WP", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_g_names, -}; - -static const char *const sunrise_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "n/a", "n/a", - "GPP_H11", "SML2DATA", "n/a", "n/a", - "GPP_H12", "SML2ALERT#", "n/a", "n/a", - "GPP_H13", "SML3CLK", "n/a", "n/a", - "GPP_H14", "SML3DATA", "n/a", "n/a", - "GPP_H15", "SML3ALERT#", "n/a", "n/a", - "GPP_H16", "SML4CLK", "n/a", "n/a", - "GPP_H17", "SML4DATA", "n/a", "n/a", - "GPP_H18", "SML4ALERT#", "n/a", "n/a", - "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_H23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_h_names, -}; - -static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { - &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, - &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, -}; - -static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { - &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, -}; - -static const struct gpio_community sunrise_community_cdefgh = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), - .groups = sunrise_community_cdefgh_groups, -}; - -static const struct gpio_community sunrise_lp_community_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), - .groups = sunrise_lp_community_cde_groups, -}; - -static const char *const sunrise_group_gpd_names[] = { - "GPD0", "BATLOW#", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "LAN_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "SLP_WLAN#", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "LANPHYPC", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_gpd_names, -}; - -static const struct gpio_group *const sunrise_community_gpd_groups[] = { - &sunrise_group_gpd, -}; - -static const struct gpio_community sunrise_community_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), - .groups = sunrise_community_gpd_groups, -}; - -static const char *const sunrise_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "n/a", "n/a", - "GPP_I1", "DDPC_HPD1", "n/a", "n/a", - "GPP_I2", "DDPD_HPD2", "n/a", "n/a", - "GPP_I3", "DDPE_HPD3", "n/a", "n/a", - "GPP_I4", "EDP_HPD", "n/a", "n/a", - "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_i_names, -}; - -static const struct gpio_group *const sunrise_community_i_groups[] = { - &sunrise_group_i, -}; - -static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { - &sunrise_lp_group_f, &sunrise_lp_group_g, -}; - -static const struct gpio_community sunrise_community_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_community_i_groups), - .groups = sunrise_community_i_groups, -}; - -static const struct gpio_community sunrise_lp_community_fg = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), - .groups = sunrise_lp_community_fg_groups, -}; - -static const struct gpio_community *const sunrise_communities[] = { - &sunrise_community_ab, &sunrise_community_cdefgh, - &sunrise_community_gpd, &sunrise_community_i, -}; - -static const struct gpio_community *const sunrise_lp_communities[] = { - &sunrise_lp_community_ab, &sunrise_lp_community_cde, - &sunrise_community_gpd, &sunrise_lp_community_fg, -}; - -static const char *const denverton_group_north_all_names[] = { - "NORTH_ALL_GBE0_SDP0", - "NORTH_ALL_GBE1_SDP0", - "NORTH_ALL_GBE0_SDP1", - "NORTH_ALL_GBE1_SDP1", - "NORTH_ALL_GBE0_SDP2", - "NORTH_ALL_GBE1_SDP2", - "NORTH_ALL_GBE0_SDP3", - "NORTH_ALL_GBE1_SDP3", - "NORTH_ALL_GBE2_LED0", - "NORTH_ALL_GBE2_LED1", - "NORTH_ALL_GBE0_I2C_CLK", - "NORTH_ALL_GBE0_I2C_DATA", - "NORTH_ALL_GBE1_I2C_CLK", - "NORTH_ALL_GBE1_I2C_DATA", - "NORTH_ALL_NCSI_RXD0", - "NORTH_ALL_NCSI_CLK_IN", - "NORTH_ALL_NCSI_RXD1", - "NORTH_ALL_NCSI_CRS_DV", - "NORTH_ALL_NCSI_ARB_IN", - "NORTH_ALL_NCSI_TX_EN", - "NORTH_ALL_NCSI_TXD0", - "NORTH_ALL_NCSI_TXD1", - "NORTH_ALL_NCSI_ARB_OUT", - "NORTH_ALL_GBE0_LED0", - "NORTH_ALL_GBE0_LED1", - "NORTH_ALL_GBE1_LED0", - "NORTH_ALL_GBE1_LED1", - "NORTH_ALL_GPIO_0", - "NORTH_ALL_PCIE_CLKREQ0_N", - "NORTH_ALL_PCIE_CLKREQ1_N", - "NORTH_ALL_PCIE_CLKREQ2_N", - "NORTH_ALL_PCIE_CLKREQ3_N", - "NORTH_ALL_PCIE_CLKREQ4_N", - "NORTH_ALL_GPIO_1", - "NORTH_ALL_GPIO_2", - "NORTH_ALL_SVID_ALERT_N", - "NORTH_ALL_SVID_DATA", - "NORTH_ALL_SVID_CLK", - "NORTH_ALL_THERMTRIP_N", - "NORTH_ALL_PROCHOT_N", - "NORTH_ALL_MEMHOT_N", -}; - -static const struct gpio_group denverton_group_north_all = { - .display = "------- GPIO Group North All -------", - .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, - .func_count = 1, - .pad_names = denverton_group_north_all_names, -}; - -static const struct gpio_group *const denverton_community_north_groups[] = { - &denverton_group_north_all, -}; - -static const struct gpio_community denverton_community_north = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xc2, - .group_count = ARRAY_SIZE(denverton_community_north_groups), - .groups = denverton_community_north_groups, -}; - -static const char *const denverton_group_south_dfx_names[] = { - "SOUTH_DFX_DFX_PORT_CLK0", - "SOUTH_DFX_DFX_PORT_CLK1", - "SOUTH_DFX_DFX_PORT0", - "SOUTH_DFX_DFX_PORT1", - "SOUTH_DFX_DFX_PORT2", - "SOUTH_DFX_DFX_PORT3", - "SOUTH_DFX_DFX_PORT4", - "SOUTH_DFX_DFX_PORT5", - "SOUTH_DFX_DFX_PORT6", - "SOUTH_DFX_DFX_PORT7", - "SOUTH_DFX_DFX_PORT8", - "SOUTH_DFX_DFX_PORT9", - "SOUTH_DFX_DFX_PORT10", - "SOUTH_DFX_DFX_PORT11", - "SOUTH_DFX_DFX_PORT12", - "SOUTH_DFX_DFX_PORT13", - "SOUTH_DFX_DFX_PORT14", - "SOUTH_DFX_DFX_PORT15", -}; - -static const struct gpio_group denverton_group_south_dfx = { - .display = "------- GPIO Group South DFX -------", - .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_dfx_names, -}; - -static const char *const denverton_group_south_group0_names[] = { - "SOUTH_GROUP0_GPIO_12", - "SOUTH_GROUP0_SMB5_GBE_ALRT_N", - "SOUTH_GROUP0_PCIE_CLKREQ5_N", - "SOUTH_GROUP0_PCIE_CLKREQ6_N", - "SOUTH_GROUP0_PCIE_CLKREQ7_N", - "SOUTH_GROUP0_UART0_RXD", - "SOUTH_GROUP0_UART0_TXD", - "SOUTH_GROUP0_SMB5_GBE_CLK", - "SOUTH_GROUP0_SMB5_GBE_DATA", - "SOUTH_GROUP0_ERROR2_N", - "SOUTH_GROUP0_ERROR1_N", - "SOUTH_GROUP0_ERROR0_N", - "SOUTH_GROUP0_IERR_N", - "SOUTH_GROUP0_MCERR_N", - "SOUTH_GROUP0_SMB0_LEG_CLK", - "SOUTH_GROUP0_SMB0_LEG_DATA", - "SOUTH_GROUP0_SMB0_LEG_ALRT_N", - "SOUTH_GROUP0_SMB1_HOST_DATA", - "SOUTH_GROUP0_SMB1_HOST_CLK", - "SOUTH_GROUP0_SMB2_PECI_DATA", - "SOUTH_GROUP0_SMB2_PECI_CLK", - "SOUTH_GROUP0_SMB4_CSME0_DATA", - "SOUTH_GROUP0_SMB4_CSME0_CLK", - "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", - "SOUTH_GROUP0_USB_OC0_N", - "SOUTH_GROUP0_FLEX_CLK_SE0", - "SOUTH_GROUP0_FLEX_CLK_SE1", - "SOUTH_GROUP0_GPIO_4", - "SOUTH_GROUP0_GPIO_5", - "SOUTH_GROUP0_GPIO_6", - "SOUTH_GROUP0_GPIO_7", - "SOUTH_GROUP0_SATA0_LED_N", - "SOUTH_GROUP0_SATA1_LED_N", - "SOUTH_GROUP0_SATA_PDETECT0", - "SOUTH_GROUP0_SATA_PDETECT1", - "SOUTH_GROUP0_SATA0_SDOUT", - "SOUTH_GROUP0_SATA1_SDOUT", - "SOUTH_GROUP0_UART1_RXD", - "SOUTH_GROUP0_UART1_TXD", - "SOUTH_GROUP0_GPIO_8", - "SOUTH_GROUP0_GPIO_9", - "SOUTH_GROUP0_TCK", - "SOUTH_GROUP0_TRST_N", - "SOUTH_GROUP0_TMS", - "SOUTH_GROUP0_TDI", - "SOUTH_GROUP0_TDO", - "SOUTH_GROUP0_CX_PRDY_N", - "SOUTH_GROUP0_CX_PREQ_N", - "SOUTH_GROUP0_CTBTRIGINOUT", - "SOUTH_GROUP0_CTBTRIGOUT", - "SOUTH_GROUP0_DFX_SPARE2", - "SOUTH_GROUP0_DFX_SPARE3", - "SOUTH_GROUP0_DFX_SPARE4", -}; - -static const struct gpio_group denverton_group_south_group0 = { - .display = "------- GPIO Group South Group0 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group0_names, -}; - -static const char *const denverton_group_south_group1_names[] = { - "SOUTH_GROUP1_SUSPWRDNACK", - "SOUTH_GROUP1_PMU_SUSCLK", - "SOUTH_GROUP1_ADR_TRIGGER", - "SOUTH_GROUP1_PMU_SLP_S45_N", - "SOUTH_GROUP1_PMU_SLP_S3_N", - "SOUTH_GROUP1_PMU_WAKE_N", - "SOUTH_GROUP1_PMU_PWRBTN_N", - "SOUTH_GROUP1_PMU_RESETBUTTON_N", - "SOUTH_GROUP1_PMU_PLTRST_N", - "SOUTH_GROUP1_SUS_STAT_N", - "SOUTH_GROUP1_SLP_S0IX_N", - "SOUTH_GROUP1_SPI_CS0_N", - "SOUTH_GROUP1_SPI_CS1_N", - "SOUTH_GROUP1_SPI_MOSI_IO0", - "SOUTH_GROUP1_SPI_MISO_IO1", - "SOUTH_GROUP1_SPI_IO2", - "SOUTH_GROUP1_SPI_IO3", - "SOUTH_GROUP1_SPI_CLK", - "SOUTH_GROUP1_SPI_CLK_LOOPBK", - "SOUTH_GROUP1_ESPI_IO0", - "SOUTH_GROUP1_ESPI_IO1", - "SOUTH_GROUP1_ESPI_IO2", - "SOUTH_GROUP1_ESPI_IO3", - "SOUTH_GROUP1_ESPI_CS0_N", - "SOUTH_GROUP1_ESPI_CLK", - "SOUTH_GROUP1_ESPI_RST_N", - "SOUTH_GROUP1_ESPI_ALRT0_N", - "SOUTH_GROUP1_GPIO_10", - "SOUTH_GROUP1_GPIO_11", - "SOUTH_GROUP1_ESPI_CLK_LOOPBK", - "SOUTH_GROUP1_EMMC_CMD", - "SOUTH_GROUP1_EMMC_STROBE", - "SOUTH_GROUP1_EMMC_CLK", - "SOUTH_GROUP1_EMMC_D0", - "SOUTH_GROUP1_EMMC_D1", - "SOUTH_GROUP1_EMMC_D2", - "SOUTH_GROUP1_EMMC_D3", - "SOUTH_GROUP1_EMMC_D4", - "SOUTH_GROUP1_EMMC_D5", - "SOUTH_GROUP1_EMMC_D6", - "SOUTH_GROUP1_EMMC_D7", - "SOUTH_GROUP1_GPIO_3", -}; - -static const struct gpio_group denverton_group_south_group1 = { - .display = "------- GPIO Group South Group1 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group1_names, -}; - -static const struct gpio_group *const denverton_community_south_groups[] = { - &denverton_group_south_dfx, - &denverton_group_south_group0, - &denverton_group_south_group1, -}; - -static const struct gpio_community denverton_community_south = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(denverton_community_south_groups), - .groups = denverton_community_south_groups, -}; - -static const struct gpio_community *const denverton_communities[] = { - &denverton_community_north, &denverton_community_south, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h new file mode 100644 index 0000000..5553b7d --- /dev/null +++ b/util/inteltool/gpio_sunrise.h @@ -0,0 +1,595 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const sunrise_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_a_names, +}; + +static const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +static const char *const sunrise_group_b_names[] = { + "GPP_B0", "n/a", "n/a", "n/a", + "GPP_B1", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPIO_CS#", "n/a", "n/a", + "GPP_B16", "GSPIO_CLK", "n/a", "n/a", + "GPP_B17", "GSPIO_MISO", "n/a", "n/a", + "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_b_names, +}; + +static const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +static const struct gpio_group *const sunrise_community_ab_groups[] = { + &sunrise_group_a, &sunrise_group_b, +}; + +static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +static const struct gpio_community sunrise_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_community_ab_groups), + .groups = sunrise_community_ab_groups, +}; + +static const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +static const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +static const char *const sunrise_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "n/a", + "GPP_D1", "n/a", "n/a", "n/a", + "GPP_D2", "n/a", "n/a", "n/a", + "GPP_D3", "n/a", "n/a", "n/a", + "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", + "GPP_D5", "I2S_SFRM", "n/a", "n/a", + "GPP_D6", "I2S_TXD", "n/a", "n/a", + "GPP_D7", "I2S_RXD", "n/a", "n/a", + "GPP_D8", "I2S_SCLK", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "n/a", + "GPP_D22", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", +}; + +static const struct gpio_group sunrise_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_d_names, +}; + +static const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +static const char *const sunrise_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +static const char *const sunrise_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "n/a", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_f_names, +}; + +static const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +static const char *const sunrise_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", + "GPP_G8", "FAN_PWM_0", "n/a", "n/a", + "GPP_G9", "FAN_PWM_1", "n/a", "n/a", + "GPP_G10", "FAN_PWM_2", "n/a", "n/a", + "GPP_G11", "FAN_PWM_3", "n/a", "n/a", + "GPP_G12", "GSXDOUT", "n/a", "n/a", + "GPP_G13", "GSXSLOAD", "n/a", "n/a", + "GPP_G14", "GSXDIN", "n/a", "n/a", + "GPP_G15", "GSXRESET#", "n/a", "n/a", + "GPP_G16", "GSXCLK", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "n/a", "n/a", + "GPP_G21", "n/a", "n/a", "n/a", + "GPP_G22", "n/a", "n/a", "n/a", + "GPP_G23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_g_names, +}; + +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +static const char *const sunrise_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_h_names, +}; + +static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, + &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, +}; + +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +static const struct gpio_community sunrise_community_cdefgh = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), + .groups = sunrise_community_cdefgh_groups, +}; + +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +static const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +static const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +static const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +static const char *const sunrise_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "n/a", "n/a", + "GPP_I1", "DDPC_HPD1", "n/a", "n/a", + "GPP_I2", "DDPD_HPD2", "n/a", "n/a", + "GPP_I3", "DDPE_HPD3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_i_names, +}; + +static const struct gpio_group *const sunrise_community_i_groups[] = { + &sunrise_group_i, +}; + +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +static const struct gpio_community sunrise_community_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_community_i_groups), + .groups = sunrise_community_i_groups, +}; + +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +static const struct gpio_community *const sunrise_communities[] = { + &sunrise_community_ab, &sunrise_community_cdefgh, + &sunrise_community_gpd, &sunrise_community_i, +}; + +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Gerrit-Change-Number: 31504 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: update HOB display code
by Jonathan Zhang (Code Review) 04 Jul '20

04 Jul '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42841 ) Change subject: soc/intel/xeon_sp/cpx: update HOB display code ...................................................................... soc/intel/xeon_sp/cpx: update HOB display code Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB. Build hob display into romstage, in addition to ramstage. Memory map HOB data is a big structure. Update the soc_display_memmap_hob() to assist trouble shooting of FSP interface. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26 --- M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/cpx/hob_display.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42841/1 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index a7ac5d7..969fe25 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -10,9 +10,10 @@ romstage-y += romstage.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += chip.c acpi.c cpu.c soc_util.c -ramstage-$(CONFIG_DISPLAY_HOB) += hob_display.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index d10a0f6..4f13759 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <console/console.h> #include <fsp/util.h> -#include <assert.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <lib.h> #include <soc/soc_util.h> static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; @@ -61,20 +62,24 @@ assert(hob != NULL); printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n"); - printk(BIOS_DEBUG, "hob: %p\n", hob); + printk(BIOS_DEBUG, "hob: %p, size: 0x%lx, structure size: 0x%lx\n", + hob, hob_size, sizeof(*hob)); printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, " "highMemSize: 0x%x\n", hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize); printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n", hob->memSize, hob->memFreq); - printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries); + printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d, entry size: %ld\n", + hob->numberEntries, sizeof(SYSTEM_MEMORY_MAP_ELEMENT)); for (int e = 0; e < hob->numberEntries; ++e) { const struct SystemMemoryMapElement *mem_element = &hob->Element[e]; printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n", e, mem_element->BaseAddress, mem_element->ElementSize, mem_element->Type); } + + hexdump(hob, sizeof(*hob)); } void soc_display_iio_universal_data_hob(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/42841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26 Gerrit-Change-Number: 42841 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Add VPD flash regions and select VPD_SMBIOS_VERSION
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42428 ) Change subject: mb/ocp/deltalake: Add VPD flash regions and select VPD_SMBIOS_VERSION ...................................................................... mb/ocp/deltalake: Add VPD flash regions and select VPD_SMBIOS_VERSION Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/board.fmd 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/42428/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 739cdea..b4e88b5 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -11,6 +11,8 @@ select IPMI_KCS select IPMI_KCS_ROMSTAGE select OCP_DMI + select VPD + select VPD_SMBIOS_VERSION config IPMI_KCS_REGISTER_SPACING int diff --git a/src/mainboard/ocp/deltalake/board.fmd b/src/mainboard/ocp/deltalake/board.fmd index a0c8dc5..9ac1331 100644 --- a/src/mainboard/ocp/deltalake/board.fmd +++ b/src/mainboard/ocp/deltalake/board.fmd @@ -7,6 +7,8 @@ SI_BIOS@0x3000000 0x1000000 { FMAP@0x0 0x800 RW_MRC_CACHE@0x1000 0x10000 - COREBOOT(CBFS)@0x11000 + RO_VPD@0x11000 0x4000 + RW_VPD@0x15000 0x4000 + COREBOOT(CBFS)@0x19000 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/42428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Gerrit-Change-Number: 42428 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42277 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC ...................................................................... mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMC There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/ipmi.c M src/mainboard/ocp/deltalake/ipmi.h M src/mainboard/ocp/deltalake/ramstage.c 3 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42277/1 diff --git a/src/mainboard/ocp/deltalake/ipmi.c b/src/mainboard/ocp/deltalake/ipmi.c index fe620fa..dd81bfd 100644 --- a/src/mainboard/ocp/deltalake/ipmi.c +++ b/src/mainboard/ocp/deltalake/ipmi.c @@ -45,3 +45,28 @@ return CB_SUCCESS; } + +enum cb_err ipmi_get_slot_id(uint8_t *slot_id) +{ + int ret; + struct ipmi_config_rsp { + struct ipmi_rsp resp; + uint8_t board_sku_id; + uint8_t board_rev_id; + uint8_t slot_id; + uint8_t slot_config_id; + } __packed; + struct ipmi_config_rsp rsp; + + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, IPMI_OEM_GET_BOARD_ID, + NULL, 0, (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + *slot_id = rsp.slot_id; + + return CB_SUCCESS; +} diff --git a/src/mainboard/ocp/deltalake/ipmi.h b/src/mainboard/ocp/deltalake/ipmi.h index 310ff27..b167473 100644 --- a/src/mainboard/ocp/deltalake/ipmi.h +++ b/src/mainboard/ocp/deltalake/ipmi.h @@ -8,6 +8,7 @@ #define IPMI_NETFN_OEM 0x30 #define IPMI_OEM_SET_PPIN 0x77 #define IPMI_OEM_GET_PCIE_CONFIG 0xf4 +#define IPMI_OEM_GET_BOARD_ID 0x37 #define PCIE_CONFIG_UNKNOWN 0x0 #define PCIE_CONFIG_A 0x1 @@ -24,4 +25,5 @@ enum cb_err ipmi_set_ppin(struct ppin_req *req); enum cb_err ipmi_get_pcie_config(uint8_t *config); +enum cb_err ipmi_get_slot_id(uint8_t *slot_id); #endif diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index ae11296..f08eb9b 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -4,10 +4,31 @@ #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> #include <soc/ramstage.h> +#include <stdio.h> #include "ipmi.h" +#define SLOT_ID_LEN 2 + extern struct fru_info_str fru_strings; +static char slot_id_str[SLOT_ID_LEN]; + +/* Override SMBIOS 2 Location In Chassis from BMC */ +const char *smbios_mainboard_location_in_chassis(void) +{ + uint8_t slot_id = 0; + + if (ipmi_get_slot_id(&slot_id) != CB_SUCCESS) + return ""; + + /* Sanity check, slot_id can only be 1~4 since there are 4 slots in YV3 */ + if (!slot_id || slot_id > 4) { + printk(BIOS_ERR, "slot_id %d is not between 1~4\n", slot_id); + return ""; + } + snprintf(slot_id_str, SLOT_ID_LEN, "%d", slot_id); + return slot_id_str; +} static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Gerrit-Change-Number: 42277 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/smbios: Add SMBIOS type8 data
by Bryant Ou (Code Review) 04 Jul '20

04 Jul '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40545 ) Change subject: arch/x86/smbios: Add SMBIOS type8 data ...................................................................... arch/x86/smbios: Add SMBIOS type8 data Refer to section 7.9 Port Connector Information of DSP0134_3.3.0 to add type 8 data, the table of data should be ported according to platform design and MB silkscreen. Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Signed-off-by: BryantOu <Bryant.Ou.Q(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 149 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/40545/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c047d75..eb383b2 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -890,6 +890,41 @@ return len; } + +const struct port_information *__weak smbios_get_port_info(size_t *num_port) +{ + *num_port = 0; + return NULL; +} + +static int smbios_write_type8(unsigned long *current, int *handle) +{ + int len = sizeof(struct smbios_type8); + int totallen = 0, i; + const struct port_information *port; + size_t num_port; + + port = smbios_get_port_info(&num_port); + for (i = 0; i < num_port; i++, port++) { + struct smbios_type8 *t = (struct smbios_type8 *)*current; + memset(t, 0, sizeof(struct smbios_type8)); + t->type = SMBIOS_PORT_CONNECTOR_INFORMATION; + t->handle = *handle; + t->length = len - 2; + t->internal_reference_designator = + smbios_add_string(t->eos, port->internal_reference_designator); + t->internal_connector_type = port->internal_connector_type; + t->external_reference_designator = + smbios_add_string(t->eos, port->external_reference_designator); + t->external_connector_type = port->external_connector_type; + t->port_type = port->port_type; + *handle += 1; + *current += t->length + smbios_string_table_len(t->eos); + totallen += t->length + smbios_string_table_len(t->eos); + } + return totallen; +} + int smbios_write_type9(unsigned long *current, int *handle, const char *name, const enum misc_slot_type type, const enum slot_data_bus_bandwidth bandwidth, @@ -1187,6 +1222,8 @@ handle++)); len += smbios_write_type7_cache_parameters(&current, &handle, &max_struct_size, type4); + update_max(len, max_struct_size, smbios_write_type8(&current, + &handle)); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) diff --git a/src/include/smbios.h b/src/include/smbios.h index 184b2c8..60d9364 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,8 @@ u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); +const struct port_information *smbios_get_port_info(size_t *num_port); + #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) #define BIOS_CHARACTERISTICS_PNP (1 << 9) @@ -209,6 +211,7 @@ SMBIOS_SYSTEM_ENCLOSURE = 3, SMBIOS_PROCESSOR_INFORMATION = 4, SMBIOS_CACHE_INFORMATION = 7, + SMBIOS_PORT_CONNECTOR_INFORMATION = 8, SMBIOS_SYSTEM_SLOTS = 9, SMBIOS_OEM_STRINGS = 11, SMBIOS_EVENT_LOG = 15, @@ -483,6 +486,115 @@ u8 eos[2]; } __packed; +/* enum for connector types */ +enum type8_connector_types { + CONN_NONE = 0x00, + CONN_CENTRONICS = 0x01, + CONN_MINI_CENTRONICS = 0x02, + CONN_PROPRIETARY = 0x03, + CONN_DB_25_PIN_MALE = 0x04, + CONN_DB_25_PIN_FEMALE = 0x05, + CONN_DB_15_PIN_MALE = 0x06, + CONN_DB_15_PIN_FEMALE = 0x07, + CONN_DB_9_PIN_MALE = 0x08, + CONN_DB_9_PIN_FEMALE = 0x09, + CONN_RJ_11 = 0x0A, + CONN_RJ_45 = 0x0B, + CONN_50_PIN_MINI_SCSI = 0x0C, + CONN_MINI_DIN = 0x0D, + CONN_MICRO_DIN = 0x0E, + CONN_PS_2 = 0x0F, + CONN_INFRARED = 0x10, + CONN_HP_HIL = 0x11, + CONN_ACCESS_BUS_USB = 0x12, + CONN_SSA_SCSI = 0x13, + CONN_CIRCULAR_DIN_8_MALE = 0x14, + CONN_CIRCULAR_DIN_8_FEMALE = 0x15, + CONN_ON_BOARD_IDE = 0x16, + CONN_ON_BOARD_FLOPPY = 0x17, + CONN_9_PIN_DUAL_INLINE = 0x18, + CONN_25_PIN_DUAL_INLINE = 0x19, + CONN_50_PIN_DUAL_INLINE = 0x1A, + CONN_68_PIN_DUAL_INLINE = 0x1B, + CONN_ON_BOARD_SOUND_INPUT_FROM_CD_ROM = 0x1C, + CONN_MINI_CENTRONICS_TYPE14 = 0x1D, + CONN_MINI_CENTRONICS_TYPE26 = 0x1E, + CONN_MINI_JACK_HEADPHONES = 0x1F, + CONN_BNC = 0x20, + CONN_1394 = 0x21, + CONN_SAS_SATA = 0x22, + CONN_USB_TYPE_C = 0x23, + CONN_PC_98 = 0xA0, + CONN_PC_98_HIRESO = 0xA1, + CONN_PC_H98 = 0xA2, + CONN_PC98_NOTE = 0xA3, + CONN_PC_98_FULL = 0xA4, + CONN_OTHER = 0xFF, +}; + +/* enum for port types */ +enum type8_port_types { + TYPE_NONE = 0x00, + TYPE_PARALLEL_PORT_XT_AT_COMPATIBLE = 0x01, + TYPE_PARALLEL_PORT_PS_2 = 0x02, + TYPE_PARALLEL_PORT_ECP = 0x03, + TYPE_PARALLEL_PORT_EPP = 0x04, + TYPE_PARALLEL_PORT_ECP_EPP = 0x05, + TYPE_SERIAL_PORT_XT_AT_COMPATIBLE = 0x06, + TYPE_SERIAL_PORT_16450_COMPATIBLE = 0x07, + TYPE_SERIAL_PORT_16550_COMPATIBLE = 0x08, + TYPE_SERIAL_PORT_16550A_COMPATIBLE = 0x09, + TYPE_SCSI_PORT = 0x0A, + TYPE_MIDI_PORT = 0x0B, + TYPE_JOY_STICK_PORT = 0x0C, + TYPE_KEYBOARD_PORT = 0x0D, + TYPE_MOUSE_PORT = 0x0E, + TYPE_SSA_SCSI = 0x0F, + TYPE_USB = 0x10, + TYPE_FIREWIRE_IEEE_P1394 = 0x11, + TYPE_PCMCIA_TYPE_I = 0x12, + TYPE_PCMCIA_TYPE_II = 0x13, + TYPE_PCMCIA_TYPE_III = 0x14, + TYPE_CARDBUS = 0x15, + TYPE_ACCESS_BUS_PORT = 0x16, + TYPE_SCSI_II = 0x17, + TYPE_SCSI_WIDE = 0x18, + TYPE_PC_98 = 0x19, + TYPE_PC_98_HIRESO = 0x1A, + TYPE_PC_H98 = 0x1B, + TYPE_VIDEO_PORT = 0x1C, + TYPE_AUDIO_PORT = 0x1D, + TYPE_MODEM_PORT = 0x1E, + TYPE_NETWORK_PORT = 0x1F, + TYPE_SATA = 0x20, + TYPE_SAS = 0x21, + TYPE_MFDP = 0x22, + TYPE_THUNDERBOLT = 0x23, + TYPE_8251_COMPATIBLE = 0xA0, + TYPE_8251_FIFO_COMPATIBLE = 0xA1, + TYPE_OTHER = 0xFF, +}; + +struct port_information { + const char *internal_reference_designator; + uint8_t internal_connector_type; + const char *external_reference_designator; + uint8_t external_connector_type; + uint8_t port_type; +}; + +struct smbios_type8 { + uint8_t type; + uint8_t length; + uint16_t handle; + uint8_t internal_reference_designator; + uint8_t internal_connector_type; + uint8_t external_reference_designator; + uint8_t external_connector_type; + uint8_t port_type; + uint8_t eos[2]; +} __packed; + /* System Slots - Slot Type */ enum misc_slot_type { SlotTypeOther = 0x01, -- To view, visit https://review.coreboot.org/c/coreboot/+/40545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81e25d27c9c6717750edf1d547e5f4cfb8f1da14 Gerrit-Change-Number: 40545 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/coreboot_table: Add Intel FSP version for cbmem to display
by Johnny Lin (Code Review) 04 Jul '20

04 Jul '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41809 ) Change subject: lib/coreboot_table: Add Intel FSP version for cbmem to display ...................................................................... lib/coreboot_table: Add Intel FSP version for cbmem to display Add Intel FSP version to coreboot table LB_TAG_EXTRA_VERSION when FSP_ADD_VERSION_TO_CBMEM is selected. Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/lib/coreboot_table.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/41809/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 075bd04..51c1cc3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -31,6 +31,9 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) +#include <fsp/util.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) { @@ -408,6 +411,23 @@ } +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) +/* Add FSP version to coreboot table LB_TAG_EXTRA_VERSION */ +static void lb_strings_fsp_version(struct lb_header *header) +{ + struct lb_string *rec; + size_t len; + char fsp_version[FSP_VER_LEN] = {0}; + + fsp_get_version(fsp_version); + rec = (struct lb_string *)lb_new_record(header); + rec->tag = LB_TAG_EXTRA_VERSION; + len = strlen(fsp_version); + rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); + memcpy(rec->string, fsp_version, len+1); +} +#endif + static void lb_record_version_timestamp(struct lb_header *header) { struct lb_timestamp *rec; @@ -516,6 +536,9 @@ /* Record our various random string information */ lb_strings(head); +#if CONFIG(FSP_ADD_VERSION_TO_CBMEM) + lb_strings_fsp_version(head); +#endif lb_record_version_timestamp(head); /* Record our framebuffer */ lb_framebuffer(head); -- To view, visit https://review.coreboot.org/c/coreboot/+/41809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Gerrit-Change-Number: 41809 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

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