Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504
Change subject: util/inteltool: Refactor code of GPIO groups ......................................................................
util/inteltool: Refactor code of GPIO groups
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- A util/inteltool/gpio.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_sunrise.h 4 files changed, 865 insertions(+), 816 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1
diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h new file mode 100644 index 0000000..64f62f8 --- /dev/null +++ b/util/inteltool/gpio.h @@ -0,0 +1,29 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer migy@darmstadt.ccc.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +struct gpio_group { + const char *display; + size_t pad_count; + size_t func_count; + const char *const *pad_names; /* indexed by 'pad * func_count + func' */ +}; + +struct gpio_community { + const char *name; + uint8_t pcr_port_id; + size_t group_count; + const struct gpio_group *const *groups; +}; diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h new file mode 100644 index 0000000..e745b44 --- /dev/null +++ b/util/inteltool/gpio_denverton.h @@ -0,0 +1,237 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer migy@darmstadt.ccc.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const denverton_group_north_all_names[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +static const struct gpio_group denverton_group_north_all = { + .display = "------- GPIO Group North All -------", + .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, + .func_count = 1, + .pad_names = denverton_group_north_all_names, +}; + +static const struct gpio_group *const denverton_community_north_groups[] = { + &denverton_group_north_all, +}; + +static const struct gpio_community denverton_community_north = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xc2, + .group_count = ARRAY_SIZE(denverton_community_north_groups), + .groups = denverton_community_north_groups, +}; + +static const char *const denverton_group_south_dfx_names[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", +}; + +static const struct gpio_group denverton_group_south_dfx = { + .display = "------- GPIO Group South DFX -------", + .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_dfx_names, +}; + +static const char *const denverton_group_south_group0_names[] = { + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", +}; + +static const struct gpio_group denverton_group_south_group0 = { + .display = "------- GPIO Group South Group0 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group0_names, +}; + +static const char *const denverton_group_south_group1_names[] = { + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + +static const struct gpio_group denverton_group_south_group1 = { + .display = "------- GPIO Group South Group1 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group1_names, +}; + +static const struct gpio_group *const denverton_community_south_groups[] = { + &denverton_group_south_dfx, + &denverton_group_south_group0, + &denverton_group_south_group1, +}; + +static const struct gpio_community denverton_community_south = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(denverton_community_south_groups), + .groups = denverton_community_south_groups, +}; + +static const struct gpio_community *const denverton_communities[] = { + &denverton_community_north, &denverton_community_south, +}; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 53a8eb9..c7ab186 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer migy@darmstadt.ccc.de * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,826 +22,13 @@ #include <inttypes.h> #include "inteltool.h" #include "pcr.h" +#include "gpio.h" +#include "gpio_denverton.h" +#include "gpio_sunrise.h"
#define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB)
-struct gpio_group { - const char *display; - size_t pad_count; - size_t func_count; - const char *const *pad_names; /* indexed by 'pad * func_count + func' */ -}; - -struct gpio_community { - const char *name; - uint8_t pcr_port_id; - size_t group_count; - const struct gpio_group *const *groups; -}; - -static const char *const sunrise_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "ISH_GP7", "n/a", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_a_names, -}; - -static const char *const sunrise_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "n/a", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "n/a", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_a = { - .display = "------- GPIO group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_a_names, -}; - -static const char *const sunrise_group_b_names[] = { - "GPP_B0", "n/a", "n/a", "n/a", - "GPP_B1", "n/a", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPIO_CS#", "n/a", "n/a", - "GPP_B16", "GSPIO_CLK", "n/a", "n/a", - "GPP_B17", "GSPIO_MISO", "n/a", "n/a", - "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_b_names, -}; - -static const char *const sunrise_lp_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPI0_CS#", "n/a", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_b_names, -}; - -static const struct gpio_group *const sunrise_community_ab_groups[] = { - &sunrise_group_a, &sunrise_group_b, -}; - -static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { - &sunrise_lp_group_a, &sunrise_lp_group_b, -}; - -static const struct gpio_community sunrise_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_community_ab_groups), - .groups = sunrise_community_ab_groups, -}; - -static const struct gpio_community sunrise_lp_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), - .groups = sunrise_lp_community_ab_groups, -}; - -static const char *const sunrise_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "n/a", "n/a", - "GPP_C4", "SML0DATA", "n/a", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", "n/a", - "GPP_C6", "SML1CLK", "n/a", "n/a", - "GPP_C7", "SML1DATA", "n/a", "n/a", - "GPP_C8", "UART0_RXD", "n/a", "n/a", - "GPP_C9", "UART0_TXD", "n/a", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", - "GPP_C16", "I2C0_SDA", "n/a", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", "n/a", - "GPP_C20", "UART2_RXD", "n/a", "n/a", - "GPP_C21", "UART2_TXD", "n/a", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_c_names, -}; - -static const char *const sunrise_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "n/a", - "GPP_D1", "n/a", "n/a", "n/a", - "GPP_D2", "n/a", "n/a", "n/a", - "GPP_D3", "n/a", "n/a", "n/a", - "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", - "GPP_D5", "I2S_SFRM", "n/a", "n/a", - "GPP_D6", "I2S_TXD", "n/a", "n/a", - "GPP_D7", "I2S_RXD", "n/a", "n/a", - "GPP_D8", "I2S_SCLK", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "n/a", - "GPP_D22", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", -}; - -static const struct gpio_group sunrise_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_d_names, -}; - -static const char *const sunrise_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "n/a", - "GPP_D1", "SPI1_CLK", "n/a", "n/a", - "GPP_D2", "SPI1_MISO", "n/a", "n/a", - "GPP_D3", "SPI1_MOSI", "n/a", "n/a", - "GPP_D4", "FLASHTRIG", "n/a", "n/a", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_d_names, -}; - -static const char *const sunrise_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATA_LED#", "n/a", "n/a", - "GPP_E9", "USB_OC0#", "n/a", "n/a", - "GPP_E10", "USB_OC1#", "n/a", "n/a", - "GPP_E11", "USB_OC2#", "n/a", "n/a", - "GPP_E12", "USB_OC3#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const sunrise_lp_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATALED#", "n/a", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", "n/a", - "GPP_E13", "DDPB_HPD0", "n/a", "n/a", - "GPP_E14", "DDPC_HPD1", "n/a", "n/a", - "GPP_E15", "DDPD_HPD2", "n/a", "n/a", - "GPP_E16", "DDPE_HPD3", "n/a", "n/a", - "GPP_E17", "EDP_HPD", "n/a", "n/a", - "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_E22", "n/a", "n/a", "n/a", - "GPP_E23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_e_names, -}; - -static const char *const sunrise_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", - "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", - "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", - "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", - "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "n/a", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_f_names, -}; - -static const char *const sunrise_lp_group_f_names[] = { - "GPP_F0", "I2S2_SCLK", "n/a", "n/a", - "GPP_F1", "I2S2_SFRM", "n/a", "n/a", - "GPP_F2", "I2S2_TXD", "n/a", "n/a", - "GPP_F3", "I2S2_RXD", "n/a", "n/a", - "GPP_F4", "I2C2_SDA", "n/a", "n/a", - "GPP_F5", "I2C2_SCL", "n/a", "n/a", - "GPP_F6", "I2C3_SDA", "n/a", "n/a", - "GPP_F7", "I2C3_SCL", "n/a", "n/a", - "GPP_F8", "I2C4_SDA", "n/a", "n/a", - "GPP_F9", "I2C4_SCL", "n/a", "n/a", - "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", - "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", - "GPP_F12", "EMMC_CMD", "n/a", "n/a", - "GPP_F13", "EMMC_DATA0", "n/a", "n/a", - "GPP_F14", "EMMC_DATA1", "n/a", "n/a", - "GPP_F15", "EMMC_DATA2", "n/a", "n/a", - "GPP_F16", "EMMC_DATA3", "n/a", "n/a", - "GPP_F17", "EMMC_DATA4", "n/a", "n/a", - "GPP_F18", "EMMC_DATA5", "n/a", "n/a", - "GPP_F19", "EMMC_DATA6", "n/a", "n/a", - "GPP_F20", "EMMC_DATA7", "n/a", "n/a", - "GPP_F21", "EMMC_RCLK", "n/a", "n/a", - "GPP_F22", "EMMC_CLK", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_f_names, -}; - -static const char *const sunrise_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "n/a", "n/a", - "GPP_G1", "FAN_TACH_1", "n/a", "n/a", - "GPP_G2", "FAN_TACH_2", "n/a", "n/a", - "GPP_G3", "FAN_TACH_3", "n/a", "n/a", - "GPP_G4", "FAN_TACH_4", "n/a", "n/a", - "GPP_G5", "FAN_TACH_5", "n/a", "n/a", - "GPP_G6", "FAN_TACH_6", "n/a", "n/a", - "GPP_G7", "FAN_TACH_7", "n/a", "n/a", - "GPP_G8", "FAN_PWM_0", "n/a", "n/a", - "GPP_G9", "FAN_PWM_1", "n/a", "n/a", - "GPP_G10", "FAN_PWM_2", "n/a", "n/a", - "GPP_G11", "FAN_PWM_3", "n/a", "n/a", - "GPP_G12", "GSXDOUT", "n/a", "n/a", - "GPP_G13", "GSXSLOAD", "n/a", "n/a", - "GPP_G14", "GSXDIN", "n/a", "n/a", - "GPP_G15", "GSXRESET#", "n/a", "n/a", - "GPP_G16", "GSXCLK", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "n/a", "n/a", - "GPP_G21", "n/a", "n/a", "n/a", - "GPP_G22", "n/a", "n/a", "n/a", - "GPP_G23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_g_names, -}; - -static const char *const sunrise_lp_group_g_names[] = { - "GPP_G0", "SD_CMD", "n/a", "n/a", - "GPP_G1", "SD_DATA0", "n/a", "n/a", - "GPP_G2", "SD_DATA1", "n/a", "n/a", - "GPP_G3", "SD_DATA2", "n/a", "n/a", - "GPP_G4", "SD_DATA3", "n/a", "n/a", - "GPP_G5", "SD_CD#", "n/a", "n/a", - "GPP_G6", "SD_CLK", "n/a", "n/a", - "GPP_G7", "SD_WP", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_g_names, -}; - -static const char *const sunrise_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "n/a", "n/a", - "GPP_H11", "SML2DATA", "n/a", "n/a", - "GPP_H12", "SML2ALERT#", "n/a", "n/a", - "GPP_H13", "SML3CLK", "n/a", "n/a", - "GPP_H14", "SML3DATA", "n/a", "n/a", - "GPP_H15", "SML3ALERT#", "n/a", "n/a", - "GPP_H16", "SML4CLK", "n/a", "n/a", - "GPP_H17", "SML4DATA", "n/a", "n/a", - "GPP_H18", "SML4ALERT#", "n/a", "n/a", - "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_H23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_h_names, -}; - -static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { - &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, - &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, -}; - -static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { - &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, -}; - -static const struct gpio_community sunrise_community_cdefgh = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), - .groups = sunrise_community_cdefgh_groups, -}; - -static const struct gpio_community sunrise_lp_community_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), - .groups = sunrise_lp_community_cde_groups, -}; - -static const char *const sunrise_group_gpd_names[] = { - "GPD0", "BATLOW#", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "LAN_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "SLP_WLAN#", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "LANPHYPC", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_gpd_names, -}; - -static const struct gpio_group *const sunrise_community_gpd_groups[] = { - &sunrise_group_gpd, -}; - -static const struct gpio_community sunrise_community_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), - .groups = sunrise_community_gpd_groups, -}; - -static const char *const sunrise_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "n/a", "n/a", - "GPP_I1", "DDPC_HPD1", "n/a", "n/a", - "GPP_I2", "DDPD_HPD2", "n/a", "n/a", - "GPP_I3", "DDPE_HPD3", "n/a", "n/a", - "GPP_I4", "EDP_HPD", "n/a", "n/a", - "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_i_names, -}; - -static const struct gpio_group *const sunrise_community_i_groups[] = { - &sunrise_group_i, -}; - -static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { - &sunrise_lp_group_f, &sunrise_lp_group_g, -}; - -static const struct gpio_community sunrise_community_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_community_i_groups), - .groups = sunrise_community_i_groups, -}; - -static const struct gpio_community sunrise_lp_community_fg = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), - .groups = sunrise_lp_community_fg_groups, -}; - -static const struct gpio_community *const sunrise_communities[] = { - &sunrise_community_ab, &sunrise_community_cdefgh, - &sunrise_community_gpd, &sunrise_community_i, -}; - -static const struct gpio_community *const sunrise_lp_communities[] = { - &sunrise_lp_community_ab, &sunrise_lp_community_cde, - &sunrise_community_gpd, &sunrise_lp_community_fg, -}; - -static const char *const denverton_group_north_all_names[] = { - "NORTH_ALL_GBE0_SDP0", - "NORTH_ALL_GBE1_SDP0", - "NORTH_ALL_GBE0_SDP1", - "NORTH_ALL_GBE1_SDP1", - "NORTH_ALL_GBE0_SDP2", - "NORTH_ALL_GBE1_SDP2", - "NORTH_ALL_GBE0_SDP3", - "NORTH_ALL_GBE1_SDP3", - "NORTH_ALL_GBE2_LED0", - "NORTH_ALL_GBE2_LED1", - "NORTH_ALL_GBE0_I2C_CLK", - "NORTH_ALL_GBE0_I2C_DATA", - "NORTH_ALL_GBE1_I2C_CLK", - "NORTH_ALL_GBE1_I2C_DATA", - "NORTH_ALL_NCSI_RXD0", - "NORTH_ALL_NCSI_CLK_IN", - "NORTH_ALL_NCSI_RXD1", - "NORTH_ALL_NCSI_CRS_DV", - "NORTH_ALL_NCSI_ARB_IN", - "NORTH_ALL_NCSI_TX_EN", - "NORTH_ALL_NCSI_TXD0", - "NORTH_ALL_NCSI_TXD1", - "NORTH_ALL_NCSI_ARB_OUT", - "NORTH_ALL_GBE0_LED0", - "NORTH_ALL_GBE0_LED1", - "NORTH_ALL_GBE1_LED0", - "NORTH_ALL_GBE1_LED1", - "NORTH_ALL_GPIO_0", - "NORTH_ALL_PCIE_CLKREQ0_N", - "NORTH_ALL_PCIE_CLKREQ1_N", - "NORTH_ALL_PCIE_CLKREQ2_N", - "NORTH_ALL_PCIE_CLKREQ3_N", - "NORTH_ALL_PCIE_CLKREQ4_N", - "NORTH_ALL_GPIO_1", - "NORTH_ALL_GPIO_2", - "NORTH_ALL_SVID_ALERT_N", - "NORTH_ALL_SVID_DATA", - "NORTH_ALL_SVID_CLK", - "NORTH_ALL_THERMTRIP_N", - "NORTH_ALL_PROCHOT_N", - "NORTH_ALL_MEMHOT_N", -}; - -static const struct gpio_group denverton_group_north_all = { - .display = "------- GPIO Group North All -------", - .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, - .func_count = 1, - .pad_names = denverton_group_north_all_names, -}; - -static const struct gpio_group *const denverton_community_north_groups[] = { - &denverton_group_north_all, -}; - -static const struct gpio_community denverton_community_north = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xc2, - .group_count = ARRAY_SIZE(denverton_community_north_groups), - .groups = denverton_community_north_groups, -}; - -static const char *const denverton_group_south_dfx_names[] = { - "SOUTH_DFX_DFX_PORT_CLK0", - "SOUTH_DFX_DFX_PORT_CLK1", - "SOUTH_DFX_DFX_PORT0", - "SOUTH_DFX_DFX_PORT1", - "SOUTH_DFX_DFX_PORT2", - "SOUTH_DFX_DFX_PORT3", - "SOUTH_DFX_DFX_PORT4", - "SOUTH_DFX_DFX_PORT5", - "SOUTH_DFX_DFX_PORT6", - "SOUTH_DFX_DFX_PORT7", - "SOUTH_DFX_DFX_PORT8", - "SOUTH_DFX_DFX_PORT9", - "SOUTH_DFX_DFX_PORT10", - "SOUTH_DFX_DFX_PORT11", - "SOUTH_DFX_DFX_PORT12", - "SOUTH_DFX_DFX_PORT13", - "SOUTH_DFX_DFX_PORT14", - "SOUTH_DFX_DFX_PORT15", -}; - -static const struct gpio_group denverton_group_south_dfx = { - .display = "------- GPIO Group South DFX -------", - .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_dfx_names, -}; - -static const char *const denverton_group_south_group0_names[] = { - "SOUTH_GROUP0_GPIO_12", - "SOUTH_GROUP0_SMB5_GBE_ALRT_N", - "SOUTH_GROUP0_PCIE_CLKREQ5_N", - "SOUTH_GROUP0_PCIE_CLKREQ6_N", - "SOUTH_GROUP0_PCIE_CLKREQ7_N", - "SOUTH_GROUP0_UART0_RXD", - "SOUTH_GROUP0_UART0_TXD", - "SOUTH_GROUP0_SMB5_GBE_CLK", - "SOUTH_GROUP0_SMB5_GBE_DATA", - "SOUTH_GROUP0_ERROR2_N", - "SOUTH_GROUP0_ERROR1_N", - "SOUTH_GROUP0_ERROR0_N", - "SOUTH_GROUP0_IERR_N", - "SOUTH_GROUP0_MCERR_N", - "SOUTH_GROUP0_SMB0_LEG_CLK", - "SOUTH_GROUP0_SMB0_LEG_DATA", - "SOUTH_GROUP0_SMB0_LEG_ALRT_N", - "SOUTH_GROUP0_SMB1_HOST_DATA", - "SOUTH_GROUP0_SMB1_HOST_CLK", - "SOUTH_GROUP0_SMB2_PECI_DATA", - "SOUTH_GROUP0_SMB2_PECI_CLK", - "SOUTH_GROUP0_SMB4_CSME0_DATA", - "SOUTH_GROUP0_SMB4_CSME0_CLK", - "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", - "SOUTH_GROUP0_USB_OC0_N", - "SOUTH_GROUP0_FLEX_CLK_SE0", - "SOUTH_GROUP0_FLEX_CLK_SE1", - "SOUTH_GROUP0_GPIO_4", - "SOUTH_GROUP0_GPIO_5", - "SOUTH_GROUP0_GPIO_6", - "SOUTH_GROUP0_GPIO_7", - "SOUTH_GROUP0_SATA0_LED_N", - "SOUTH_GROUP0_SATA1_LED_N", - "SOUTH_GROUP0_SATA_PDETECT0", - "SOUTH_GROUP0_SATA_PDETECT1", - "SOUTH_GROUP0_SATA0_SDOUT", - "SOUTH_GROUP0_SATA1_SDOUT", - "SOUTH_GROUP0_UART1_RXD", - "SOUTH_GROUP0_UART1_TXD", - "SOUTH_GROUP0_GPIO_8", - "SOUTH_GROUP0_GPIO_9", - "SOUTH_GROUP0_TCK", - "SOUTH_GROUP0_TRST_N", - "SOUTH_GROUP0_TMS", - "SOUTH_GROUP0_TDI", - "SOUTH_GROUP0_TDO", - "SOUTH_GROUP0_CX_PRDY_N", - "SOUTH_GROUP0_CX_PREQ_N", - "SOUTH_GROUP0_CTBTRIGINOUT", - "SOUTH_GROUP0_CTBTRIGOUT", - "SOUTH_GROUP0_DFX_SPARE2", - "SOUTH_GROUP0_DFX_SPARE3", - "SOUTH_GROUP0_DFX_SPARE4", -}; - -static const struct gpio_group denverton_group_south_group0 = { - .display = "------- GPIO Group South Group0 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group0_names, -}; - -static const char *const denverton_group_south_group1_names[] = { - "SOUTH_GROUP1_SUSPWRDNACK", - "SOUTH_GROUP1_PMU_SUSCLK", - "SOUTH_GROUP1_ADR_TRIGGER", - "SOUTH_GROUP1_PMU_SLP_S45_N", - "SOUTH_GROUP1_PMU_SLP_S3_N", - "SOUTH_GROUP1_PMU_WAKE_N", - "SOUTH_GROUP1_PMU_PWRBTN_N", - "SOUTH_GROUP1_PMU_RESETBUTTON_N", - "SOUTH_GROUP1_PMU_PLTRST_N", - "SOUTH_GROUP1_SUS_STAT_N", - "SOUTH_GROUP1_SLP_S0IX_N", - "SOUTH_GROUP1_SPI_CS0_N", - "SOUTH_GROUP1_SPI_CS1_N", - "SOUTH_GROUP1_SPI_MOSI_IO0", - "SOUTH_GROUP1_SPI_MISO_IO1", - "SOUTH_GROUP1_SPI_IO2", - "SOUTH_GROUP1_SPI_IO3", - "SOUTH_GROUP1_SPI_CLK", - "SOUTH_GROUP1_SPI_CLK_LOOPBK", - "SOUTH_GROUP1_ESPI_IO0", - "SOUTH_GROUP1_ESPI_IO1", - "SOUTH_GROUP1_ESPI_IO2", - "SOUTH_GROUP1_ESPI_IO3", - "SOUTH_GROUP1_ESPI_CS0_N", - "SOUTH_GROUP1_ESPI_CLK", - "SOUTH_GROUP1_ESPI_RST_N", - "SOUTH_GROUP1_ESPI_ALRT0_N", - "SOUTH_GROUP1_GPIO_10", - "SOUTH_GROUP1_GPIO_11", - "SOUTH_GROUP1_ESPI_CLK_LOOPBK", - "SOUTH_GROUP1_EMMC_CMD", - "SOUTH_GROUP1_EMMC_STROBE", - "SOUTH_GROUP1_EMMC_CLK", - "SOUTH_GROUP1_EMMC_D0", - "SOUTH_GROUP1_EMMC_D1", - "SOUTH_GROUP1_EMMC_D2", - "SOUTH_GROUP1_EMMC_D3", - "SOUTH_GROUP1_EMMC_D4", - "SOUTH_GROUP1_EMMC_D5", - "SOUTH_GROUP1_EMMC_D6", - "SOUTH_GROUP1_EMMC_D7", - "SOUTH_GROUP1_GPIO_3", -}; - -static const struct gpio_group denverton_group_south_group1 = { - .display = "------- GPIO Group South Group1 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group1_names, -}; - -static const struct gpio_group *const denverton_community_south_groups[] = { - &denverton_group_south_dfx, - &denverton_group_south_group0, - &denverton_group_south_group1, -}; - -static const struct gpio_community denverton_community_south = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(denverton_community_south_groups), - .groups = denverton_community_south_groups, -}; - -static const struct gpio_community *const denverton_communities[] = { - &denverton_community_north, &denverton_community_south, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h new file mode 100644 index 0000000..5553b7d --- /dev/null +++ b/util/inteltool/gpio_sunrise.h @@ -0,0 +1,595 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer migy@darmstadt.ccc.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const sunrise_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_a_names, +}; + +static const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +static const char *const sunrise_group_b_names[] = { + "GPP_B0", "n/a", "n/a", "n/a", + "GPP_B1", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPIO_CS#", "n/a", "n/a", + "GPP_B16", "GSPIO_CLK", "n/a", "n/a", + "GPP_B17", "GSPIO_MISO", "n/a", "n/a", + "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_b_names, +}; + +static const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +static const struct gpio_group *const sunrise_community_ab_groups[] = { + &sunrise_group_a, &sunrise_group_b, +}; + +static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +static const struct gpio_community sunrise_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_community_ab_groups), + .groups = sunrise_community_ab_groups, +}; + +static const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +static const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +static const char *const sunrise_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "n/a", + "GPP_D1", "n/a", "n/a", "n/a", + "GPP_D2", "n/a", "n/a", "n/a", + "GPP_D3", "n/a", "n/a", "n/a", + "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", + "GPP_D5", "I2S_SFRM", "n/a", "n/a", + "GPP_D6", "I2S_TXD", "n/a", "n/a", + "GPP_D7", "I2S_RXD", "n/a", "n/a", + "GPP_D8", "I2S_SCLK", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "n/a", + "GPP_D22", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", +}; + +static const struct gpio_group sunrise_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_d_names, +}; + +static const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +static const char *const sunrise_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +static const char *const sunrise_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "n/a", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_f_names, +}; + +static const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +static const char *const sunrise_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", + "GPP_G8", "FAN_PWM_0", "n/a", "n/a", + "GPP_G9", "FAN_PWM_1", "n/a", "n/a", + "GPP_G10", "FAN_PWM_2", "n/a", "n/a", + "GPP_G11", "FAN_PWM_3", "n/a", "n/a", + "GPP_G12", "GSXDOUT", "n/a", "n/a", + "GPP_G13", "GSXSLOAD", "n/a", "n/a", + "GPP_G14", "GSXDIN", "n/a", "n/a", + "GPP_G15", "GSXRESET#", "n/a", "n/a", + "GPP_G16", "GSXCLK", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "n/a", "n/a", + "GPP_G21", "n/a", "n/a", "n/a", + "GPP_G22", "n/a", "n/a", "n/a", + "GPP_G23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_g_names, +}; + +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +static const char *const sunrise_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_h_names, +}; + +static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, + &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, +}; + +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +static const struct gpio_community sunrise_community_cdefgh = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), + .groups = sunrise_community_cdefgh_groups, +}; + +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +static const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +static const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +static const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +static const char *const sunrise_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "n/a", "n/a", + "GPP_I1", "DDPC_HPD1", "n/a", "n/a", + "GPP_I2", "DDPD_HPD2", "n/a", "n/a", + "GPP_I3", "DDPE_HPD3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_i_names, +}; + +static const struct gpio_group *const sunrise_community_i_groups[] = { + &sunrise_group_i, +}; + +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +static const struct gpio_community sunrise_community_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_community_i_groups), + .groups = sunrise_community_i_groups, +}; + +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +static const struct gpio_community *const sunrise_communities[] = { + &sunrise_community_ab, &sunrise_community_cdefgh, + &sunrise_community_gpd, &sunrise_community_i, +}; + +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +};
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: util/inteltool: Refactor code of GPIO groups ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31504/1/util/inteltool/gpio_sunrise.h File util/inteltool/gpio_sunrise.h:
https://review.coreboot.org/#/c/31504/1/util/inteltool/gpio_sunrise.h@30 PS1, Line 30: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
https://review.coreboot.org/#/c/31504/1/util/inteltool/gpio_sunrise.h@64 PS1, Line 64: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: util/inteltool: Refactor code of GPIOs ......................................................................
Patch Set 8:
Patch Set 8:
In gpio_*.h add '#include "gpio.h"'
As these are all includes and not classes this would cause a redefinition and wouldn't be able to compile.
and include guards for for better reading
What do you mean with "guards"?
Hello Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#9).
Change subject: util/inteltool: Refactor code of GPIOs ......................................................................
util/inteltool: Refactor code of GPIOs
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/gpio.c A util/inteltool/gpio.h A util/inteltool/gpio_baytrail.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_ich.h A util/inteltool/gpio_pch.h A util/inteltool/gpio_sunrise.h 8 files changed, 1,582 insertions(+), 1,448 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: util/inteltool: Refactor code of GPIOs ......................................................................
Patch Set 9:
(149 comments)
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h File util/inteltool/gpio_baytrail.h:
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@103 PS9, Line 103: "GPIO_S0_SC[000]", "SATA_GP[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@104 PS9, Line 104: "GPIO_S0_SC[001]", "SATA_GP[1]", "SATA_DEVSLP[0]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@105 PS9, Line 105: "GPIO_S0_SC[002]", "SATA_LED#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@106 PS9, Line 106: "GPIO_S0_SC[003]", "PCIE_CLKREQ[0]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@107 PS9, Line 107: "GPIO_S0_SC[004]", "PCIE_CLKREQ[1]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@108 PS9, Line 108: "GPIO_S0_SC[005]", "PCIE_CLKREQ[2]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@109 PS9, Line 109: "GPIO_S0_SC[006]", "PCIE_CLKREQ[3]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@110 PS9, Line 110: "GPIO_S0_SC[007]", "RESERVED", "SD3_WP", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@111 PS9, Line 111: "GPIO_S0_SC[008]", "I2S0_CLK", "HDA_RST#", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@112 PS9, Line 112: "GPIO_S0_SC[009]", "I2S0_FRM", "HDA_SYNC", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@113 PS9, Line 113: "GPIO_S0_SC[010]", "I2S0_DATAOUT", "HDA_CLK", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@114 PS9, Line 114: "GPIO_S0_SC[011]", "I2S0_DATAIN", "HDA_SDO", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@115 PS9, Line 115: "GPIO_S0_SC[012]", "I2S1_CLK", "HDA_SDI[0]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@116 PS9, Line 116: "GPIO_S0_SC[013]", "I2S1_FRM", "HDA_SDI[1]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@117 PS9, Line 117: "GPIO_S0_SC[014]", "I2S1_DATAOUT", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@118 PS9, Line 118: "GPIO_S0_SC[015]", "I2S1_DATAIN", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@119 PS9, Line 119: "GPIO_S0_SC[016]", "MMC1_CLK", "-", "MMC1_45_CLK", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@120 PS9, Line 120: "GPIO_S0_SC[017]", "MMC1_D[0]", "-", "MMC1_45_D[0]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@121 PS9, Line 121: "GPIO_S0_SC[018]", "MMC1_D[1]", "-", "MMC1_45_D[1]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@122 PS9, Line 122: "GPIO_S0_SC[019]", "MMC1_D[2]", "-", "MMC1_45_D[2]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@123 PS9, Line 123: "GPIO_S0_SC[020]", "MMC1_D[3]", "-", "MMC1_45_D[3]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@124 PS9, Line 124: "GPIO_S0_SC[021]", "MMC1_D[4]", "-", "MMC1_45_D[4]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@125 PS9, Line 125: "GPIO_S0_SC[022]", "MMC1_D[5]", "-", "MMC1_45_D[5]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@126 PS9, Line 126: "GPIO_S0_SC[023]", "MMC1_D[6]", "-", "MMC1_45_D[6]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@127 PS9, Line 127: "GPIO_S0_SC[024]", "MMC1_D[7]", "-", "MMC1_45_D[7]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@128 PS9, Line 128: "GPIO_S0_SC[025]", "MMC1_CMD", "-", "MMC1_45_CMD", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@129 PS9, Line 129: "GPIO_S0_SC[026]", "MMC1_RST#", "SATA_DEVSLP[0]", "MMC1_45_RST#", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@130 PS9, Line 130: "GPIO_S0_SC[027]", "SD2_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@131 PS9, Line 131: "GPIO_S0_SC[028]", "SD2_D[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@132 PS9, Line 132: "GPIO_S0_SC[029]", "SD2_D[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@133 PS9, Line 133: "GPIO_S0_SC[030]", "SD2_D[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@134 PS9, Line 134: "GPIO_S0_SC[031]", "SD2_D[3]_CD#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@135 PS9, Line 135: "GPIO_S0_SC[032]", "SD2_CMD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@136 PS9, Line 136: "GPIO_S0_SC[033]", "SD3_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@137 PS9, Line 137: "GPIO_S0_SC[034]", "SD3_D[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@138 PS9, Line 138: "GPIO_S0_SC[035]", "SD3_D[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@139 PS9, Line 139: "GPIO_S0_SC[036]", "SD3_D[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@140 PS9, Line 140: "GPIO_S0_SC[037]", "SD3_D[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@141 PS9, Line 141: "GPIO_S0_SC[038]", "SD3_CD#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@142 PS9, Line 142: "GPIO_S0_SC[039]", "SD3_CMD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@143 PS9, Line 143: "GPIO_S0_SC[040]", "SD3_1P8EN", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@144 PS9, Line 144: "GPIO_S0_SC[041]", "SD3_PWREN#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@145 PS9, Line 145: "GPIO_S0_SC[042]", "ILB_LPC_AD[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@146 PS9, Line 146: "GPIO_S0_SC[043]", "ILB_LPC_AD[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@147 PS9, Line 147: "GPIO_S0_SC[044]", "ILB_LPC_AD[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@148 PS9, Line 148: "GPIO_S0_SC[045]", "ILB_LPC_AD[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@149 PS9, Line 149: "GPIO_S0_SC[046]", "ILB_LPC_FRAME#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@150 PS9, Line 150: "GPIO_S0_SC[047]", "ILB_LPC_CLK[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@151 PS9, Line 151: "GPIO_S0_SC[048]", "ILB_LPC_CLK[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@152 PS9, Line 152: "GPIO_S0_SC[049]", "ILB_LPC_CLKRUN#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@153 PS9, Line 153: "GPIO_S0_SC[050]", "ILB_LPC_SERIRQ", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@154 PS9, Line 154: "GPIO_S0_SC[051]", "PCU_SMB_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@155 PS9, Line 155: "GPIO_S0_SC[052]", "PCU_SMB_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@156 PS9, Line 156: "GPIO_S0_SC[053]", "PCU_SMB_ALERT#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@157 PS9, Line 157: "GPIO_S0_SC[054]", "ILB_8254_SPKR", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@158 PS9, Line 158: "GPIO_S0_SC[055]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@159 PS9, Line 159: "GPIO_S0_SC[056]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@160 PS9, Line 160: "GPIO_S0_SC[057]", "PCU_UART_TXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@161 PS9, Line 161: "GPIO_S0_SC[058]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@162 PS9, Line 162: "GPIO_S0_SC[059]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@163 PS9, Line 163: "GPIO_S0_SC[060]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@164 PS9, Line 164: "GPIO_S0_SC[061]", "PCU_UART_RXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@165 PS9, Line 165: "GPIO_S0_SC[062]", "LPE_I2S2_CLK", "SATA_DEVSLP[1]", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@166 PS9, Line 166: "GPIO_S0_SC[063]", "LPE_I2S2_FRM", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@167 PS9, Line 167: "GPIO_S0_SC[064]", "LPE_I2S2_DATAIN", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@168 PS9, Line 168: "GPIO_S0_SC[065]", "LPE_I2S2_DATAOUT", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@169 PS9, Line 169: "GPIO_S0_SC[066]", "SIO_SPI_CS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@170 PS9, Line 170: "GPIO_S0_SC[067]", "SIO_SPI_MISO", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@171 PS9, Line 171: "GPIO_S0_SC[068]", "SIO_SPI_MOSI", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@172 PS9, Line 172: "GPIO_S0_SC[069]", "SIO_SPI_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@173 PS9, Line 173: "GPIO_S0_SC[070]", "SIO_UART1_RXD", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@174 PS9, Line 174: "GPIO_S0_SC[071]", "SIO_UART1_TXD", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@175 PS9, Line 175: "GPIO_S0_SC[072]", "SIO_UART1_RTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@176 PS9, Line 176: "GPIO_S0_SC[073]", "SIO_UART1_CTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@177 PS9, Line 177: "GPIO_S0_SC[074]", "SIO_UART2_RXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@178 PS9, Line 178: "GPIO_S0_SC[075]", "SIO_UART2_TXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@179 PS9, Line 179: "GPIO_S0_SC[076]", "SIO_UART2_RTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@180 PS9, Line 180: "GPIO_S0_SC[077]", "SIO_UART2_CTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@181 PS9, Line 181: "GPIO_S0_SC[078]", "SIO_I2C0_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@182 PS9, Line 182: "GPIO_S0_SC[079]", "SIO_I2C0_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@183 PS9, Line 183: "GPIO_S0_SC[080]", "SIO_I2C1_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@184 PS9, Line 184: "GPIO_S0_SC[081]", "SIO_I2C1_CLK", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@185 PS9, Line 185: "GPIO_S0_SC[082]", "SIO_I2C2_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@186 PS9, Line 186: "GPIO_S0_SC[083]", "SIO_I2C2_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@187 PS9, Line 187: "GPIO_S0_SC[084]", "SIO_I2C3_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@188 PS9, Line 188: "GPIO_S0_SC[085]", "SIO_I2C3_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@189 PS9, Line 189: "GPIO_S0_SC[086]", "SIO_I2C4_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@190 PS9, Line 190: "GPIO_S0_SC[087]", "SIO_I2C4_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@191 PS9, Line 191: "GPIO_S0_SC[088]", "SIO_I2C5_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@192 PS9, Line 192: "GPIO_S0_SC[089]", "SIO_I2C5_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@193 PS9, Line 193: "GPIO_S0_SC[090]", "SIO_I2C6_DATA", "ILB_NMI", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@194 PS9, Line 194: "GPIO_S0_SC[091]", "SIO_I2C6_CLK", "SD3_WP", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@195 PS9, Line 195: "RESERVED", "GPIO_S0_SC[092]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@196 PS9, Line 196: "RESERVED", "GPIO_S0_SC[093]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@197 PS9, Line 197: "GPIO_S0_SC[094]", "SIO_PWM[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@198 PS9, Line 198: "GPIO_S0_SC[095]", "SIO_PWM[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@199 PS9, Line 199: "GPIO_S0_SC[096]", "PMC_PLT_CLK[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@200 PS9, Line 200: "GPIO_S0_SC[097]", "PMC_PLT_CLK[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@201 PS9, Line 201: "GPIO_S0_SC[098]", "PMC_PLT_CLK[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@202 PS9, Line 202: "GPIO_S0_SC[099]", "PMC_PLT_CLK[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@203 PS9, Line 203: "GPIO_S0_SC[100]", "PMC_PLT_CLK[4]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@204 PS9, Line 204: "GPIO_S0_SC[101]", "PMC_PLT_CLK[5]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@208 PS9, Line 208: "GPIO_S5[00]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@209 PS9, Line 209: "GPIO_S5[01]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[1]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@210 PS9, Line 210: "GPIO_S5[02]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[2]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@211 PS9, Line 211: "GPIO_S5[03]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[3]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@212 PS9, Line 212: "GPIO_S5[04]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@213 PS9, Line 213: "GPIO_S5[05]", "PMC_SUSCLK[1]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@214 PS9, Line 214: "GPIO_S5[06]", "PMC_SUSCLK[2]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@215 PS9, Line 215: "GPIO_S5[07]", "PMC_SUSCLK[3]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@216 PS9, Line 216: "GPIO_S5[08]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@217 PS9, Line 217: "GPIO_S5[09]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@218 PS9, Line 218: "GPIO_S5[10]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@219 PS9, Line 219: "PMC_SUSPWRDNACK", "GPIO_S5[11]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@220 PS9, Line 220: "PMC_SUSCLK[0]", "GPIO_S5[12]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@221 PS9, Line 221: "RESERVED", "GPIO_S5[13]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@222 PS9, Line 222: "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@222 PS9, Line 222: "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-", space required after that ',' (ctx:VxV)
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@223 PS9, Line 223: "PMC_WAKE_PCIE[0]#", "GPIO_S5[15]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@224 PS9, Line 224: "PMC_PWRBTN#", "GPIO_S5[16]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@225 PS9, Line 225: "RESERVED", "GPIO_S5[17]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@226 PS9, Line 226: "PMC_SUS_STAT#", "GPIO_S5[18]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@227 PS9, Line 227: "USB_OC[0]#", "GPIO_S5[19]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@228 PS9, Line 228: "USB_OC[1]#", "GPIO_S5[20]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@229 PS9, Line 229: "PCU_SPI_CS[1]#", "GPIO_S5[21]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@230 PS9, Line 230: "GPIO_S5[22]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@231 PS9, Line 231: "GPIO_S5[23]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@232 PS9, Line 232: "GPIO_S5[24]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@233 PS9, Line 233: "GPIO_S5[25]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@234 PS9, Line 234: "GPIO_S5[26]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@235 PS9, Line 235: "GPIO_S5[27]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@236 PS9, Line 236: "GPIO_S5[28]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@237 PS9, Line 237: "GPIO_S5[29]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@238 PS9, Line 238: "GPIO_S5[30]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@239 PS9, Line 239: "GPIO_S5[31]", "USB_ULPI_CLK", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@240 PS9, Line 240: "GPIO_S5[32]", "USB_ULPI_DATA[0]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@241 PS9, Line 241: "GPIO_S5[33]", "USB_ULPI_DATA[1]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@242 PS9, Line 242: "GPIO_S5[34]", "USB_ULPI_DATA[2]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@243 PS9, Line 243: "GPIO_S5[35]", "USB_ULPI_DATA[3]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@244 PS9, Line 244: "GPIO_S5[36]", "USB_ULPI_DATA[4]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@245 PS9, Line 245: "GPIO_S5[37]", "USB_ULPI_DATA[5]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@246 PS9, Line 246: "GPIO_S5[38]", "USB_ULPI_DATA[6]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@247 PS9, Line 247: "GPIO_S5[39]", "USB_ULPI_DATA[7]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@248 PS9, Line 248: "GPIO_S5[40]", "USB_ULPI_DIR", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@249 PS9, Line 249: "GPIO_S5[41]", "USB_ULPI_NXT", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@250 PS9, Line 250: "GPIO_S5[42]", "USB_ULPI_STP", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_baytrail.h@251 PS9, Line 251: "GPIO_S5[43]", "USB_ULPI_REFCLK", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_sunrise.h File util/inteltool/gpio_sunrise.h:
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_sunrise.h@33 PS9, Line 33: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
https://review.coreboot.org/#/c/31504/9/util/inteltool/gpio_sunrise.h@67 PS9, Line 67: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
Hello Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#10).
Change subject: util/inteltool: Refactor code of GPIOs ......................................................................
util/inteltool: Refactor code of GPIOs
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/gpio.c A util/inteltool/gpio.h A util/inteltool/gpio_baytrail.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_ich.h A util/inteltool/gpio_pch.h A util/inteltool/gpio_sunrise.h 8 files changed, 1,592 insertions(+), 1,448 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/10
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: util/inteltool: Refactor code of GPIOs ......................................................................
Patch Set 10:
(149 comments)
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h File util/inteltool/gpio_baytrail.h:
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@105 PS10, Line 105: "GPIO_S0_SC[000]", "SATA_GP[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@106 PS10, Line 106: "GPIO_S0_SC[001]", "SATA_GP[1]", "SATA_DEVSLP[0]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@107 PS10, Line 107: "GPIO_S0_SC[002]", "SATA_LED#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@108 PS10, Line 108: "GPIO_S0_SC[003]", "PCIE_CLKREQ[0]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@109 PS10, Line 109: "GPIO_S0_SC[004]", "PCIE_CLKREQ[1]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@110 PS10, Line 110: "GPIO_S0_SC[005]", "PCIE_CLKREQ[2]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@111 PS10, Line 111: "GPIO_S0_SC[006]", "PCIE_CLKREQ[3]#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@112 PS10, Line 112: "GPIO_S0_SC[007]", "RESERVED", "SD3_WP", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@113 PS10, Line 113: "GPIO_S0_SC[008]", "I2S0_CLK", "HDA_RST#", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@114 PS10, Line 114: "GPIO_S0_SC[009]", "I2S0_FRM", "HDA_SYNC", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@115 PS10, Line 115: "GPIO_S0_SC[010]", "I2S0_DATAOUT", "HDA_CLK", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@116 PS10, Line 116: "GPIO_S0_SC[011]", "I2S0_DATAIN", "HDA_SDO", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@117 PS10, Line 117: "GPIO_S0_SC[012]", "I2S1_CLK", "HDA_SDI[0]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@118 PS10, Line 118: "GPIO_S0_SC[013]", "I2S1_FRM", "HDA_SDI[1]", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@119 PS10, Line 119: "GPIO_S0_SC[014]", "I2S1_DATAOUT", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@120 PS10, Line 120: "GPIO_S0_SC[015]", "I2S1_DATAIN", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@121 PS10, Line 121: "GPIO_S0_SC[016]", "MMC1_CLK", "-", "MMC1_45_CLK", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@122 PS10, Line 122: "GPIO_S0_SC[017]", "MMC1_D[0]", "-", "MMC1_45_D[0]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@123 PS10, Line 123: "GPIO_S0_SC[018]", "MMC1_D[1]", "-", "MMC1_45_D[1]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@124 PS10, Line 124: "GPIO_S0_SC[019]", "MMC1_D[2]", "-", "MMC1_45_D[2]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@125 PS10, Line 125: "GPIO_S0_SC[020]", "MMC1_D[3]", "-", "MMC1_45_D[3]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@126 PS10, Line 126: "GPIO_S0_SC[021]", "MMC1_D[4]", "-", "MMC1_45_D[4]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@127 PS10, Line 127: "GPIO_S0_SC[022]", "MMC1_D[5]", "-", "MMC1_45_D[5]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@128 PS10, Line 128: "GPIO_S0_SC[023]", "MMC1_D[6]", "-", "MMC1_45_D[6]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@129 PS10, Line 129: "GPIO_S0_SC[024]", "MMC1_D[7]", "-", "MMC1_45_D[7]", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@130 PS10, Line 130: "GPIO_S0_SC[025]", "MMC1_CMD", "-", "MMC1_45_CMD", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@131 PS10, Line 131: "GPIO_S0_SC[026]", "MMC1_RST#", "SATA_DEVSLP[0]", "MMC1_45_RST#", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@132 PS10, Line 132: "GPIO_S0_SC[027]", "SD2_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@133 PS10, Line 133: "GPIO_S0_SC[028]", "SD2_D[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@134 PS10, Line 134: "GPIO_S0_SC[029]", "SD2_D[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@135 PS10, Line 135: "GPIO_S0_SC[030]", "SD2_D[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@136 PS10, Line 136: "GPIO_S0_SC[031]", "SD2_D[3]_CD#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@137 PS10, Line 137: "GPIO_S0_SC[032]", "SD2_CMD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@138 PS10, Line 138: "GPIO_S0_SC[033]", "SD3_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@139 PS10, Line 139: "GPIO_S0_SC[034]", "SD3_D[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@140 PS10, Line 140: "GPIO_S0_SC[035]", "SD3_D[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@141 PS10, Line 141: "GPIO_S0_SC[036]", "SD3_D[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@142 PS10, Line 142: "GPIO_S0_SC[037]", "SD3_D[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@143 PS10, Line 143: "GPIO_S0_SC[038]", "SD3_CD#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@144 PS10, Line 144: "GPIO_S0_SC[039]", "SD3_CMD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@145 PS10, Line 145: "GPIO_S0_SC[040]", "SD3_1P8EN", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@146 PS10, Line 146: "GPIO_S0_SC[041]", "SD3_PWREN#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@147 PS10, Line 147: "GPIO_S0_SC[042]", "ILB_LPC_AD[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@148 PS10, Line 148: "GPIO_S0_SC[043]", "ILB_LPC_AD[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@149 PS10, Line 149: "GPIO_S0_SC[044]", "ILB_LPC_AD[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@150 PS10, Line 150: "GPIO_S0_SC[045]", "ILB_LPC_AD[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@151 PS10, Line 151: "GPIO_S0_SC[046]", "ILB_LPC_FRAME#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@152 PS10, Line 152: "GPIO_S0_SC[047]", "ILB_LPC_CLK[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@153 PS10, Line 153: "GPIO_S0_SC[048]", "ILB_LPC_CLK[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@154 PS10, Line 154: "GPIO_S0_SC[049]", "ILB_LPC_CLKRUN#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@155 PS10, Line 155: "GPIO_S0_SC[050]", "ILB_LPC_SERIRQ", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@156 PS10, Line 156: "GPIO_S0_SC[051]", "PCU_SMB_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@157 PS10, Line 157: "GPIO_S0_SC[052]", "PCU_SMB_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@158 PS10, Line 158: "GPIO_S0_SC[053]", "PCU_SMB_ALERT#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@159 PS10, Line 159: "GPIO_S0_SC[054]", "ILB_8254_SPKR", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@160 PS10, Line 160: "GPIO_S0_SC[055]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@161 PS10, Line 161: "GPIO_S0_SC[056]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@162 PS10, Line 162: "GPIO_S0_SC[057]", "PCU_UART_TXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@163 PS10, Line 163: "GPIO_S0_SC[058]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@164 PS10, Line 164: "GPIO_S0_SC[059]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@165 PS10, Line 165: "GPIO_S0_SC[060]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@166 PS10, Line 166: "GPIO_S0_SC[061]", "PCU_UART_RXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@167 PS10, Line 167: "GPIO_S0_SC[062]", "LPE_I2S2_CLK", "SATA_DEVSLP[1]", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@168 PS10, Line 168: "GPIO_S0_SC[063]", "LPE_I2S2_FRM", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@169 PS10, Line 169: "GPIO_S0_SC[064]", "LPE_I2S2_DATAIN", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@170 PS10, Line 170: "GPIO_S0_SC[065]", "LPE_I2S2_DATAOUT", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@171 PS10, Line 171: "GPIO_S0_SC[066]", "SIO_SPI_CS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@172 PS10, Line 172: "GPIO_S0_SC[067]", "SIO_SPI_MISO", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@173 PS10, Line 173: "GPIO_S0_SC[068]", "SIO_SPI_MOSI", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@174 PS10, Line 174: "GPIO_S0_SC[069]", "SIO_SPI_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@175 PS10, Line 175: "GPIO_S0_SC[070]", "SIO_UART1_RXD", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@176 PS10, Line 176: "GPIO_S0_SC[071]", "SIO_UART1_TXD", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@177 PS10, Line 177: "GPIO_S0_SC[072]", "SIO_UART1_RTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@178 PS10, Line 178: "GPIO_S0_SC[073]", "SIO_UART1_CTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@179 PS10, Line 179: "GPIO_S0_SC[074]", "SIO_UART2_RXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@180 PS10, Line 180: "GPIO_S0_SC[075]", "SIO_UART2_TXD", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@181 PS10, Line 181: "GPIO_S0_SC[076]", "SIO_UART2_RTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@182 PS10, Line 182: "GPIO_S0_SC[077]", "SIO_UART2_CTS#", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@183 PS10, Line 183: "GPIO_S0_SC[078]", "SIO_I2C0_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@184 PS10, Line 184: "GPIO_S0_SC[079]", "SIO_I2C0_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@185 PS10, Line 185: "GPIO_S0_SC[080]", "SIO_I2C1_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@186 PS10, Line 186: "GPIO_S0_SC[081]", "SIO_I2C1_CLK", "RESERVED", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@187 PS10, Line 187: "GPIO_S0_SC[082]", "SIO_I2C2_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@188 PS10, Line 188: "GPIO_S0_SC[083]", "SIO_I2C2_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@189 PS10, Line 189: "GPIO_S0_SC[084]", "SIO_I2C3_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@190 PS10, Line 190: "GPIO_S0_SC[085]", "SIO_I2C3_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@191 PS10, Line 191: "GPIO_S0_SC[086]", "SIO_I2C4_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@192 PS10, Line 192: "GPIO_S0_SC[087]", "SIO_I2C4_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@193 PS10, Line 193: "GPIO_S0_SC[088]", "SIO_I2C5_DATA", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@194 PS10, Line 194: "GPIO_S0_SC[089]", "SIO_I2C5_CLK", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@195 PS10, Line 195: "GPIO_S0_SC[090]", "SIO_I2C6_DATA", "ILB_NMI", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@196 PS10, Line 196: "GPIO_S0_SC[091]", "SIO_I2C6_CLK", "SD3_WP", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@197 PS10, Line 197: "RESERVED", "GPIO_S0_SC[092]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@198 PS10, Line 198: "RESERVED", "GPIO_S0_SC[093]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@199 PS10, Line 199: "GPIO_S0_SC[094]", "SIO_PWM[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@200 PS10, Line 200: "GPIO_S0_SC[095]", "SIO_PWM[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@201 PS10, Line 201: "GPIO_S0_SC[096]", "PMC_PLT_CLK[0]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@202 PS10, Line 202: "GPIO_S0_SC[097]", "PMC_PLT_CLK[1]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@203 PS10, Line 203: "GPIO_S0_SC[098]", "PMC_PLT_CLK[2]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@204 PS10, Line 204: "GPIO_S0_SC[099]", "PMC_PLT_CLK[3]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@205 PS10, Line 205: "GPIO_S0_SC[100]", "PMC_PLT_CLK[4]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@206 PS10, Line 206: "GPIO_S0_SC[101]", "PMC_PLT_CLK[5]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@210 PS10, Line 210: "GPIO_S5[00]", "RESERVED", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@211 PS10, Line 211: "GPIO_S5[01]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[1]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@212 PS10, Line 212: "GPIO_S5[02]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[2]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@213 PS10, Line 213: "GPIO_S5[03]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "PMC_WAKE_PCIE[3]#", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@214 PS10, Line 214: "GPIO_S5[04]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@215 PS10, Line 215: "GPIO_S5[05]", "PMC_SUSCLK[1]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@216 PS10, Line 216: "GPIO_S5[06]", "PMC_SUSCLK[2]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@217 PS10, Line 217: "GPIO_S5[07]", "PMC_SUSCLK[3]", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@218 PS10, Line 218: "GPIO_S5[08]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@219 PS10, Line 219: "GPIO_S5[09]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@220 PS10, Line 220: "GPIO_S5[10]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@221 PS10, Line 221: "PMC_SUSPWRDNACK", "GPIO_S5[11]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@222 PS10, Line 222: "PMC_SUSCLK[0]", "GPIO_S5[12]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@223 PS10, Line 223: "RESERVED", "GPIO_S5[13]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@224 PS10, Line 224: "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@224 PS10, Line 224: "RESERVED", "GPIO_S5[14]", "USB_ULPI_RST#","-", "-", "-", "-", "-", space required after that ',' (ctx:VxV)
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@225 PS10, Line 225: "PMC_WAKE_PCIE[0]#", "GPIO_S5[15]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@226 PS10, Line 226: "PMC_PWRBTN#", "GPIO_S5[16]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@227 PS10, Line 227: "RESERVED", "GPIO_S5[17]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@228 PS10, Line 228: "PMC_SUS_STAT#", "GPIO_S5[18]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@229 PS10, Line 229: "USB_OC[0]#", "GPIO_S5[19]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@230 PS10, Line 230: "USB_OC[1]#", "GPIO_S5[20]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@231 PS10, Line 231: "PCU_SPI_CS[1]#", "GPIO_S5[21]", "-", "-", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@232 PS10, Line 232: "GPIO_S5[22]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@233 PS10, Line 233: "GPIO_S5[23]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@234 PS10, Line 234: "GPIO_S5[24]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@235 PS10, Line 235: "GPIO_S5[25]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@236 PS10, Line 236: "GPIO_S5[26]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@237 PS10, Line 237: "GPIO_S5[27]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@238 PS10, Line 238: "GPIO_S5[28]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@239 PS10, Line 239: "GPIO_S5[29]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@240 PS10, Line 240: "GPIO_S5[30]", "RESERVED", "RESERVED", "RESERVED", "-", "-", "RESERVED", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@241 PS10, Line 241: "GPIO_S5[31]", "USB_ULPI_CLK", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@242 PS10, Line 242: "GPIO_S5[32]", "USB_ULPI_DATA[0]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@243 PS10, Line 243: "GPIO_S5[33]", "USB_ULPI_DATA[1]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@244 PS10, Line 244: "GPIO_S5[34]", "USB_ULPI_DATA[2]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@245 PS10, Line 245: "GPIO_S5[35]", "USB_ULPI_DATA[3]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@246 PS10, Line 246: "GPIO_S5[36]", "USB_ULPI_DATA[4]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@247 PS10, Line 247: "GPIO_S5[37]", "USB_ULPI_DATA[5]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@248 PS10, Line 248: "GPIO_S5[38]", "USB_ULPI_DATA[6]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@249 PS10, Line 249: "GPIO_S5[39]", "USB_ULPI_DATA[7]", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@250 PS10, Line 250: "GPIO_S5[40]", "USB_ULPI_DIR", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@251 PS10, Line 251: "GPIO_S5[41]", "USB_ULPI_NXT", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@252 PS10, Line 252: "GPIO_S5[42]", "USB_ULPI_STP", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_baytrail.h@253 PS10, Line 253: "GPIO_S5[43]", "USB_ULPI_REFCLK", "RESERVED", "RESERVED", "-", "-", "-", "-", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_sunrise.h File util/inteltool/gpio_sunrise.h:
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_sunrise.h@35 PS10, Line 35: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
https://review.coreboot.org/#/c/31504/10/util/inteltool/gpio_sunrise.h@69 PS10, Line 69: "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", line over 80 characters
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to header files per platform ......................................................................
Patch Set 16:
This change is ready for review.
Hello Patrick Rudolph, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#17).
Change subject: inteltool: Move GPIOs to header files per platform ......................................................................
inteltool: Move GPIOs to header files per platform
This patch moves the GPIO declarations to header files per platform, which gives a bit more overview over the GPIOs.
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/gpio.c A util/inteltool/gpio.h A util/inteltool/gpio_baytrail.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_i631x.h A util/inteltool/gpio_ich.h A util/inteltool/gpio_lynxpoint.h A util/inteltool/gpio_pch.h A util/inteltool/gpio_sunrise.h 10 files changed, 1,704 insertions(+), 1,516 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/17
Hello Patrick Rudolph, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#18).
Change subject: inteltool: Move GPIOs to header files per platform ......................................................................
inteltool: Move GPIOs to header files per platform
This patch moves the GPIO declarations to header files per platform, which gives a better overview over the GPIOs.
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/gpio.c A util/inteltool/gpio.h A util/inteltool/gpio_baytrail.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_i631x.h A util/inteltool/gpio_ich.h A util/inteltool/gpio_lynxpoint.h A util/inteltool/gpio_pch.h A util/inteltool/gpio_sunrise.h 10 files changed, 1,704 insertions(+), 1,516 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/18
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to header files per platform ......................................................................
Patch Set 18:
(1 comment)
https://review.coreboot.org/#/c/31504/18/util/inteltool/gpio.h File util/inteltool/gpio.h:
https://review.coreboot.org/#/c/31504/18/util/inteltool/gpio.h@5 PS18, Line 5: * Copyright (C) 2019 Felix Singer migy@darmstadt.ccc.de For which line exactly? ;)
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to header files per platform ......................................................................
Patch Set 24:
This change is ready for review.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 32:
This change is ready for review.
Hello Patrick Rudolph, Marius Genheimer, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#33).
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_ich.h A util/inteltool/gpio_pch.h A util/inteltool/platform_apollolake.c A util/inteltool/platform_apollolake.h A util/inteltool/platform_baytrail.h A util/inteltool/platform_cannonlake.c A util/inteltool/platform_cannonlake.h A util/inteltool/platform_denverton.c A util/inteltool/platform_denverton.h A util/inteltool/platform_i631x.c A util/inteltool/platform_i631x.h A util/inteltool/platform_lynxpoint.c A util/inteltool/platform_lynxpoint.h A util/inteltool/platform_sunrise.c A util/inteltool/platform_sunrise.h 19 files changed, 2,769 insertions(+), 2,384 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/33
Hello Patrick Rudolph, Marius Genheimer, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#34).
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer migy@darmstadt.ccc.de --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_ich.h A util/inteltool/gpio_pch.h A util/inteltool/platform_apollolake.c A util/inteltool/platform_apollolake.h A util/inteltool/platform_baytrail.h A util/inteltool/platform_cannonlake.c A util/inteltool/platform_cannonlake.h A util/inteltool/platform_denverton.c A util/inteltool/platform_denverton.h A util/inteltool/platform_i631x.c A util/inteltool/platform_i631x.h A util/inteltool/platform_lynxpoint.c A util/inteltool/platform_lynxpoint.h A util/inteltool/platform_sunrise.c A util/inteltool/platform_sunrise.h 19 files changed, 2,770 insertions(+), 2,384 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/34
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/#/c/31504/34/util/inteltool/gpio.h File util/inteltool/gpio.h:
PS34: Why mix these two different models in one file?
https://review.coreboot.org/#/c/31504/34/util/inteltool/platform_apollolake.... File util/inteltool/platform_apollolake.h:
PS34: You don't need one header file per platform. You could gather the declarations in a single file instead. If they are only used in one compilation unit, you could also move these declarations there.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/#/c/31504/34/util/inteltool/gpio.h File util/inteltool/gpio.h:
PS34:
Why mix these two different models in one file?
No specific reason. Both seperated seems a bit small to me, but not really a problem.
https://review.coreboot.org/#/c/31504/34/util/inteltool/platform_apollolake.... File util/inteltool/platform_apollolake.h:
PS34:
You don't need one header file per platform. You could gather the declarations […]
What is a compilation unit? I want to implement more registers in the future, so they will also be included in other c files.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 36:
This change is ready for review.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 37:
This change is ready for review.
Daniel Maslowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 37: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 37:
(2 comments)
https://review.coreboot.org/#/c/31504/34/util/inteltool/gpio.h File util/inteltool/gpio.h:
PS34:
No specific reason. Both seperated seems a bit small to me, but not really a problem.
Maybe move the `gpio_group` definitions into platform.h?
https://review.coreboot.org/#/c/31504/34/util/inteltool/platform_apollolake.... File util/inteltool/platform_apollolake.h:
PS34:
What is a compilation unit? I want to implement more registers in the future, so they will also be i […]
Compilation unit is what the compiler sees after preprocessing, i.e. a .c file with all its includes.
I think it makes sense to gather all the definitions in a single `platform.h`.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 38:
This change is ready for review.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 39:
(6 comments)
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio.h File util/inteltool/gpio.h:
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio.h@24 PS39, Line 24: const char *const *pad_names; /* indexed by 'pad * func_count + func' */ Please don't mix comment styles. I guess C style (this here) is preferred, though.
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio.h@40 PS39, Line 40: /* Description of GPIO 'bank' ex. {ncore, score. ssus} */ Mention that this is used for BayTrail? Also, maybe put it between `new` and `old`?
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio.c File util/inteltool/gpio.c:
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio.c@5 PS39, Line 5: * Copyright (C) 2019 by 9elements Agency GmbH For the added #includes?
https://review.coreboot.org/#/c/31504/39/util/inteltool/gpio_baytrail.h File util/inteltool/gpio_baytrail.h:
PS39: Why is this a .h?
https://review.coreboot.org/#/c/31504/39/util/inteltool/platform_i631x.c File util/inteltool/platform_i631x.c:
PS39: Maybe keep it alongside `gpio_ich`? Because of its similarity.
https://review.coreboot.org/#/c/31504/39/util/inteltool/platform_lynxpoint.c File util/inteltool/platform_lynxpoint.c:
PS39: This is for Lynx Point LP (low power) only. The file name should reflect that.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 44:
This change is ready for review.
Hello Patrick Rudolph, Felix Held, Marius Genheimer, Daniel Maslowski, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#45).
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer felixsinger@posteo.net --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/platform.h A util/inteltool/platform_apollolake.c A util/inteltool/platform_baytrail.c A util/inteltool/platform_cannonlake.c A util/inteltool/platform_denverton.c A util/inteltool/platform_ich.c A util/inteltool/platform_lynxpoint_lp.c A util/inteltool/platform_pch.c A util/inteltool/platform_sunrise.c 13 files changed, 2,722 insertions(+), 2,407 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/45
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 45: Code-Review+1
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 45: Code-Review+1
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 46:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/31504/39/util/inteltool/gpio_baytra... File util/inteltool/gpio_baytrail.h:
PS39:
Why is this a . […]
Done
https://review.coreboot.org/c/coreboot/+/31504/41/util/inteltool/platform_ca... File util/inteltool/platform_cannonlake.c:
PS41:
I think it's okay grouping similar platforms (like Cannonlake*) by one file, else the directory ge […]
Done
Hello Patrick Rudolph, Christoph Pomaska, Felix Held, Angel Pons, Marius Genheimer, Daniel Maslowski, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#47).
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer felixsinger@posteo.net --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/platform.h A util/inteltool/platform_apollolake.c A util/inteltool/platform_baytrail.c A util/inteltool/platform_cannonlake_pch_h.c A util/inteltool/platform_denverton.c A util/inteltool/platform_ich.c A util/inteltool/platform_lynxpoint_lp.c A util/inteltool/platform_pch.c A util/inteltool/platform_sunrisepoint.c A util/inteltool/platform_sunrisepoint_common.c A util/inteltool/platform_sunrisepoint_common.h A util/inteltool/platform_sunrisepoint_lp.c 16 files changed, 2,796 insertions(+), 2,409 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/47
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 47:
How about creating a platform directory and moving all platform* files in there?
Hello Patrick Rudolph, Christoph Pomaska, Felix Held, Angel Pons, Marius Genheimer, Daniel Maslowski, Paul Menzel, Stefan Reinauer, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31504
to look at the new patch set (#48).
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer felixsinger@posteo.net --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/platform.h A util/inteltool/platform_apollolake.c A util/inteltool/platform_baytrail.c A util/inteltool/platform_cannonlake_pch_h.c A util/inteltool/platform_denverton.c A util/inteltool/platform_ich.c A util/inteltool/platform_lynxpoint_lp.c A util/inteltool/platform_pch.c A util/inteltool/platform_sunrisepoint.c A util/inteltool/platform_sunrisepoint_common.c A util/inteltool/platform_sunrisepoint_common.h A util/inteltool/platform_sunrisepoint_lp.c 16 files changed, 2,796 insertions(+), 2,409 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/48
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 48:
(2 comments)
https://review.coreboot.org/c/coreboot/+/31504/48/util/inteltool/platform.h File util/inteltool/platform.h:
https://review.coreboot.org/c/coreboot/+/31504/48/util/inteltool/platform.h@... PS48, Line 23: size_t apl_communities_count; Why aren't these `extern const`, too?
https://review.coreboot.org/c/coreboot/+/31504/47/util/inteltool/platform_su... File util/inteltool/platform_sunrisepoint_common.h:
https://review.coreboot.org/c/coreboot/+/31504/47/util/inteltool/platform_su... PS47, Line 23: extern Why omit the `extern`? (I only just learned, that one can.)
Matt DeVillier has uploaded a new patch set (#49) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
inteltool: Move GPIOs to c files per platform
This patch moves the GPIO declarations to c files per platform, which gives a better overview over the GPIOs and future implementations of registers.
Tested on Clevo N130WU (Kabylake)
Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer felixsinger@posteo.net Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M util/inteltool/Makefile M util/inteltool/gpio.c A util/inteltool/gpio.h M util/inteltool/gpio_groups.c A util/inteltool/platform.h A util/inteltool/platforms/apollolake.c A util/inteltool/platforms/baytrail.c A util/inteltool/platforms/cannonlake_pch_h.c A util/inteltool/platforms/denverton.c A util/inteltool/platforms/icelake_lp.c A util/inteltool/platforms/ich.c A util/inteltool/platforms/lewisburg.c A util/inteltool/platforms/lynxpoint_lp.c A util/inteltool/platforms/pch.c A util/inteltool/platforms/sunrisepoint.c A util/inteltool/platforms/sunrisepoint_common.c A util/inteltool/platforms/sunrisepoint_common.h A util/inteltool/platforms/sunrisepoint_lp.c 18 files changed, 3,760 insertions(+), 3,338 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/49
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Patch Set 49:
rebased this since it had gotten a bit stale, and moved all the platform_ files into a new platforms folder to keep things tidy
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31504 )
Change subject: inteltool: Move GPIOs to c files per platform ......................................................................
Abandoned
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Christoph Pomaska (Code Review)
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Daniel Maslowski (Code Review)
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Felix Singer (Code Review)
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Matt DeVillier (Code Review)
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Nico Huber (Code Review)