coreboot-gerrit June 2020

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Change in coreboot[master]: Documenation: Add several fixes
by Patrick Rudolph (Code Review) 01 Jul '20

01 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41492 ) Change subject: Documenation: Add several fixes ...................................................................... Documenation: Add several fixes * Add support for Sphinx 3.0+ * Add backward support for Sphinx 1.8 and older * Make sphinxcontrib ditaa an option extension * Allow SPHINXOPTS to be set from command line * Add sphinx and sphinx-lint to top level Makefile Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/Makefile.sphinx M Documentation/conf.py M Makefile 3 files changed, 37 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/41492/1 diff --git a/Documentation/Makefile.sphinx b/Documentation/Makefile.sphinx index caa8190..6930130 100644 --- a/Documentation/Makefile.sphinx +++ b/Documentation/Makefile.sphinx @@ -2,7 +2,7 @@ # # You can set these variables from the command line. -SPHINXOPTS = +SPHINXOPTS ?= SPHINXBUILD = sphinx-build SPHINXAUTOBUILD = sphinx-autobuild PAPER = diff --git a/Documentation/conf.py b/Documentation/conf.py index 8848ee6..f82fa0e 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -1,6 +1,18 @@ # -*- coding: utf-8 -*- import subprocess from recommonmark.parser import CommonMarkParser +import sphinx + +# Get Sphinx version +major = 0 +minor = 0 +patchlevel = 0 +version = sphinx.__version__.split(".") +if len(version) > 1: + major = int(version[0]) + minor = int(version[1]) + if len(version) > 2: + patchlevel = int(version[2]) # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] @@ -25,7 +37,18 @@ # The short X.Y version. version = release.split("-")[0] -extensions = ['sphinxcontrib.ditaa'] +extensions = [] +# Load recommonmark, supported since 1.8+ +if major >= 2 or (major == 1 and minor >= 8): + extensions += ['recommonmark'] + +# Try to load DITAA +try: + import sphinxcontrib.ditaa +except ImportError: + print("Error: Please install sphinxcontrib.ditaa for ASCII art conversion\n") +else: + extensions += 'sphinxcontrib.ditaa' # The language for content autogenerated by Sphinx. Refer to documentation # for a list of supported languages. @@ -187,7 +210,9 @@ def setup(app): from recommonmark.transform import AutoStructify - app.add_source_parser('.md', MyCommonMarkParser) + # Load recommonmark on old Sphinx + if major == 1 and minor < 8: + app.add_source_parser('.md', MyCommonMarkParser) app.add_config_value('recommonmark_config', { 'enable_auto_toc_tree': True, diff --git a/Makefile b/Makefile index 55d3db1..ea21131 100644 --- a/Makefile +++ b/Makefile @@ -113,6 +113,8 @@ @echo ' distclean - Remove build artifacts and config files' @echo ' doxygen - Build doxygen documentation for coreboot' @echo ' doxyplatform - Build doxygen documentation for the current platform' + @echo ' sphinx - Build sphinx documentation for coreboot' + @echo ' sphinx-lint - Build sphinx documenttion for coreboot with warnings as errors' @echo ' filelist - Show files used in current build' @echo ' printall - print makefile info for debugging' @echo ' gitconfig - set up git to submit patches to coreboot' @@ -449,6 +451,12 @@ cscope: cscope -bR +sphinx: + $(MAKE) -C Documentation -f Makefile.sphinx html + +sphinx-lint: + $(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html + doxy: doxygen doxygen: $(DOXYGEN) Documentation/Doxyfile.coreboot @@ -495,5 +503,5 @@ rm -rf coreboot-builds coreboot-builds-chromeos rm -f abuild*.xml junit.xml* util/lint/junit.xml -.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy doxygen_simple +.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy doxygen_simple sphinx sphinx-lint .PHONY: ctags-project cscope-project clean-ctags -- To view, visit https://review.coreboot.org/c/coreboot/+/41492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51 Gerrit-Change-Number: 41492 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake/northbridge.c: Drop thunk functions
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42696 ) Change subject: nb/intel/ironlake/northbridge.c: Drop thunk functions ...................................................................... nb/intel/ironlake/northbridge.c: Drop thunk functions Just call the called function directly. Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/northbridge.c 1 file changed, 2 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42696/1 diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index f53b03e..267baf7 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -147,13 +147,7 @@ add_fixed_resources(dev, 10); } -static void mc_set_resources(struct device *dev) -{ - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - -static void northbridge_dmi_init(struct device *dev) +static void northbridge_init(struct device *dev) { u32 reg32; @@ -200,11 +194,6 @@ DMIBAR32(0x88) = reg32; } -static void northbridge_init(struct device *dev) -{ - northbridge_dmi_init(dev); -} - /* Disable unused PEG devices based on devicetree before PCI enumeration */ static void ironlake_init(void *const chip_info) { @@ -229,7 +218,7 @@ static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .acpi_fill_ssdt = generate_cpu_entries, -- To view, visit https://review.coreboot.org/c/coreboot/+/42696 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c997a63cbbd2b1029f94c23685847df910f8a0e Gerrit-Change-Number: 42696 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Move EC wake to happen in ramstage
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42952 ) Change subject: mb/google/zork: Move EC wake to happen in ramstage ...................................................................... mb/google/zork: Move EC wake to happen in ramstage Currently, EC wake signal (GPIO_24) is configured early on in romstage. However, there is no need for that since EC wake is not really required to be configured until ramstage. This change moves GPIO_24 configuration to happen in ramstage. BUG=b:159832123 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/42952/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 75a7096..ea85819 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -12,8 +12,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -45,8 +43,6 @@ PAD_GPO(GPIO_5, LOW), /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_6, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -109,6 +105,8 @@ PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_UP), /* */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 4fbc4f0..60f997d 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -12,8 +12,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EN_PWR_TOUCHPAD_PS2 - reset */ @@ -41,8 +39,6 @@ PAD_GPO(GPIO_5, LOW), /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_13, LOW), - /* EC_FCH_WAKE_L */ - PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EMMC_RESET - reset (default stuffing unused)*/ @@ -105,6 +101,8 @@ PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* EC_AP_INT_ODL (Sensor Framesync) */ PAD_GPI(GPIO_31, PULL_UP), /* EN_PWR_FP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6949dcd7c866df2fa028c7b2e7f347cec988e309 Gerrit-Change-Number: 42952 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Fix pad configurations for wake signals
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42951 ) Change subject: mb/google/zork: Fix pad configurations for wake signals ...................................................................... mb/google/zork: Fix pad configurations for wake signals This change updates the pad configurations for wake lines as follows: 1. Pen eject wake signal needs to be configured as PAD_WAKE i.e. wake using GPIO controller block. This is because pen eject signal is not dual routed and the trigger filtering is set by the kernel driver differently for S0 and S3 wake. Hence, it cannot use SCI GEVENT and instead has to fall back to using GPIO controller wake. 2. All other wake signals (EC, trackpad, fingerprint) need to be configured as SCI. This allows OS to enable/disable wake from these sources if required. Example: powerd disables wake from trackpad when in tablet mode. Hence, all other wake sources use SCI. BUG=b:159832123 TEST=Verified wake using pen eject and EC. Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/42951/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 711a94c..75a7096 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -13,7 +13,7 @@ /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -46,7 +46,7 @@ /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_6, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* PCIE_RST1_L - Variable timings (May remove) */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* NVME_AUX_RESET_L */ @@ -80,7 +80,7 @@ /* PCIE_WAKE_L */ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ - PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* EN_PWR_TOUCHPAD */ @@ -90,8 +90,7 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* EC_IN_RW_OD */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index f7e30ef..4fbc4f0 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -13,7 +13,7 @@ /* PEN_POWER_EN - reset */ PAD_GPO(GPIO_5, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EN_PWR_TOUCHPAD_PS2 - reset */ @@ -42,7 +42,7 @@ /* EN_PWR_TOUCHPAD_PS2 - reset */ PAD_GPO(GPIO_13, LOW), /* EC_FCH_WAKE_L */ - PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, HIGH), /* EMMC_RESET - reset (default stuffing unused)*/ @@ -76,14 +76,13 @@ /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ - PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5), + PAD_SCI(GPIO_6, PULL_NONE, EDGE_LOW), /* I2S_SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ - PAD_GPI(GPIO_9, PULL_UP), + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* FPMCU_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8cd5926f223db51a689ed8948040b8070cf1680 Gerrit-Change-Number: 42951 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt
by Felix Held (Code Review) 01 Jul '20

01 Jul '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42846 ) Change subject: soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt ...................................................................... soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdt Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/root_complex.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/42846/1 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4930a0e..af347e7 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -135,6 +135,11 @@ { msr_t msr; + if (!device) { + printk(BIOS_ERR, "Error: %s device is NULL.\n", __func__); + return; + } + acpigen_write_scope(acpi_device_scope(device)); msr = rdmsr(TOP_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/42846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Gerrit-Change-Number: 42846 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: set tcc_offset value to 10
by Sumeet R Pawnikar (Code Review) 01 Jul '20

01 Jul '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42906 ) Change subject: mb/google/dedede: set tcc_offset value to 10 ...................................................................... mb/google/dedede: set tcc_offset value to 10 Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/42906/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index f95d123..32f6690 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,6 +155,8 @@ # Enable processor thermal control register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90C + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: -- To view, visit https://review.coreboot.org/c/coreboot/+/42906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53d1bd413c64643cf8bdaef266bde25a2f3a97ee Gerrit-Change-Number: 42906 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Drop copy-pasted and unused macro
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42702 ) Change subject: nb/intel/ironlake: Drop copy-pasted and unused macro ...................................................................... nb/intel/ironlake: Drop copy-pasted and unused macro Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I78856707864563e392626a494f0e77eec9802002 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/finalize.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/42702/1 diff --git a/src/northbridge/intel/ironlake/finalize.c b/src/northbridge/intel/ironlake/finalize.c index 6e0844b..88bc98d 100644 --- a/src/northbridge/intel/ironlake/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -2,8 +2,6 @@ #include "ironlake.h" -#define PCI_DEV_SNB PCI_DEV(0, 0, 0) - void intel_ironlake_finalize_smm(void) { MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78856707864563e392626a494f0e77eec9802002 Gerrit-Change-Number: 42702 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Use `pci_update_config32()`
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42700 ) Change subject: nb/intel/ironlake: Use `pci_update_config32()` ...................................................................... nb/intel/ironlake: Use `pci_update_config32()` Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/42700/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index acc76da..4f221bf 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -63,8 +63,7 @@ /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, - (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); + pci_update_config32(PCI_DEV(0xff, 0x00, 0), 0x80, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; -- To view, visit https://review.coreboot.org/c/coreboot/+/42700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d36165e61e6399458479d47a33fe708eba7ea86 Gerrit-Change-Number: 42700 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake: Simplify BAR handling
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42699 ) Change subject: nb/intel/ironlake: Simplify BAR handling ...................................................................... nb/intel/ironlake: Simplify BAR handling Currently, northbridge BARs are 32-bit values. We don't have any use case for BARs above 4 GiB in early stages, so handling possibly 64-bit values seems unnecessary, which currently is a noisy way to write zero. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/early_init.c 1 file changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/42699/1 diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b6c5f0f..acc76da 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -38,15 +38,11 @@ printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, - (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, - (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); - + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, - (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); -- To view, visit https://review.coreboot.org/c/coreboot/+/42699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93d1740b961f6a5962757d9a1e960b3f1014a0c6 Gerrit-Change-Number: 42699 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/ironlake/ironlake.h: Clean up
by Angel Pons (Code Review) 01 Jul '20

01 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42698 ) Change subject: nb/intel/ironlake/ironlake.h: Clean up ...................................................................... nb/intel/ironlake/ironlake.h: Clean up Align values and drop copy-pasted, wrong and unused definitions. Tested with BUILD_TIMELESS=1, packardbell/ms2290 remains identical. Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/ironlake.h 1 file changed, 50 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42698/1 diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 53efced..92ee76c 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -14,64 +14,47 @@ /* * D0:F0 */ -#define D0F0_EPBAR_LO 0x40 -#define D0F0_EPBAR_HI 0x44 -#define D0F0_MCHBAR_LO 0x48 -#define D0F0_MCHBAR_HI 0x4c -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 -#define DEVEN_IGD (1 << 3) -#define DEVEN_PEG10 (1 << 1) -#define DEVEN_HOST (1 << 0) -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 -#define D0F0_DMIBAR_LO 0x68 -#define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 -#define QPD0F1_PAM(x) (0x40+(x)) /* 0-6*/ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 -#define D0F0_TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define DEVEN_IGD (1 << 3) +#define DEVEN_PEG10 (1 << 1) +#define DEVEN_HOST (1 << 0) +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_IGD_BASE 0xa4 +#define D0F0_GTT_BASE 0xa8 +#define D0F0_TOLUD 0xb0 +#define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define D0F0_CAPID0 0xe0 -#define TSEG 0xac /* TSEG base */ +#define TSEG 0xac /* TSEG base */ /* * D1:F0 PEG */ -#define PEG_CAP 0xa2 -#define SLOTCAP 0xb4 -#define PEGLC 0xec -#define D1F0_VCCAP 0x104 -#define D1F0_VC0RCTL 0x114 +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 /* Chipset types */ -#define IRONLAKE_MOBILE 0 +#define IRONLAKE_MOBILE 0 #define IRONLAKE_DESKTOP 1 -#define IRONLAKE_SERVER 2 - -/* Device ID for SandyBridge and IvyBridge */ -#define BASE_REV_SNB 0x00 -#define BASE_REV_IVB 0x50 -#define BASE_REV_MASK 0x50 - -/* SandyBridge CPU stepping */ -#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ -#define SNB_STEP_D1 (BASE_REV_SNB + 6) -#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ - -/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 (BASE_REV_IVB + 0) -#define IVB_STEP_B0 (BASE_REV_IVB + 2) -#define IVB_STEP_C0 (BASE_REV_IVB + 4) -#define IVB_STEP_K0 (BASE_REV_IVB + 5) -#define IVB_STEP_D0 (BASE_REV_IVB + 6) +#define IRONLAKE_SERVER 2 /* Northbridge BARs */ #ifndef __ACPI__ @@ -113,28 +96,25 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) \ - (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR16_AND_OR(x, and, or) \ - (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR32_AND_OR(x, and, or) \ - (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) -#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR8(x) (*((volatile u8 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) +#define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x)))) #define EPPVCCAP1 0x004 /* 32bit */ #define EPPVCCAP2 0x008 /* 32bit */ @@ -163,9 +143,9 @@ * DMIBAR */ -#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) -#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR8(x) (*((volatile u8 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) +#define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x)))) #define DMIVCECH 0x000 /* 32bit */ #define DMIPVCCAP1 0x004 /* 32bit */ @@ -199,9 +179,6 @@ #ifndef __ASSEMBLER__ -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 - void intel_ironlake_finalize_smm(void); int bridge_silicon_revision(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44f96982c8a38e1933cd78a976e18a8a11fb4096 Gerrit-Change-Number: 42698 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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