coreboot-gerrit June 2020

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Change in coreboot[master]: crossgcc: Upgrade IASL to version 20200214
by HAOUAS Elyes (Code Review) 01 Jul '20

01 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38907 ) Change subject: crossgcc: Upgrade IASL to version 20200214 ...................................................................... crossgcc: Upgrade IASL to version 20200214 Change: https://acpica.org/node/177 Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20200214_iasl.patch D util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38907/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 150e616..b1c930b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20200110 +IASL_VERSION=20200214 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200110_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200214_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20200110_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200214_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum deleted file mode 100644 index 48c0a2f..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50c163d965aa2cbee9a3a5d9244d1a0d16c06ec0 tarballs/acpica-unix2-20200110.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum new file mode 100644 index 0000000..97ef41e --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum @@ -0,0 +1 @@ +70f4e47590c82553287b2f301020352c59db7589 tarballs/acpica-unix2-20200214.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/38907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Gerrit-Change-Number: 38907 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

8 30

Change in coreboot[master]: [WIP] tigerlake: add TCC activation functionality
by Sumeet R Pawnikar (Code Review) 01 Jul '20

01 Jul '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41855 ) Change subject: [WIP] tigerlake: add TCC activation functionality ...................................................................... [WIP] tigerlake: add TCC activation functionality This enables to configure the Thermal Control Circuit (TCC) activation value to new value as tcc_offset in degree Celcius. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action before CPU temperature reaches maximum operating temperature TjMax value. BUG=None BRANCH=None TEST=Built for volteer platform and verified the MSR value. Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41855/1 diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index f5870ec..a61e431 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -30,6 +30,26 @@ fsps_load(romstage_handoff_is_resume()); } +static void configure_thermal_target(void) +{ + config_t *conf = config_of_soc(); + msr_t msr; + + /* Set TCC activation offset */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ + msr.lo &= ~0x7f; + msr.lo |= 0xe6; /* setting 100ms thermal time window */ + wrmsr(MSR_TEMPERATURE_TARGET, msr); +} + static void configure_isst(void) { config_t *conf = config_of_soc(); @@ -216,4 +236,7 @@ { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_thermal_target(); } diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index bdcd357..1aeddd6 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -205,6 +205,9 @@ /* Enable TCPU for processor thermal control */ params->Device4Enable = config->Device4Enable; + /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/41855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5 Gerrit-Change-Number: 41855 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: mb/google/zork: update G2 TS RST delay time
by Kevin Chiu (Code Review) 01 Jul '20

01 Jul '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42867 ) Change subject: mb/google/zork: update G2 TS RST delay time ...................................................................... mb/google/zork: update G2 TS RST delay time in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/berknip/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42867/1 diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 18288ec..229469e 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -93,7 +93,7 @@ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.reset_delay_ms" = "1" + register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/42867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Gerrit-Change-Number: 42867 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src/mainboard/prodrive/hermes/variants/baseboard: add support for sat...
by Jonas Löffelholz (Code Review) 01 Jul '20

01 Jul '20

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42804 ) Change subject: src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap ...................................................................... src/mainboard/prodrive/hermes/variants/baseboard: add support for sata hotswap Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42804/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 3388239..c4be117 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -19,6 +19,15 @@ register "SataPortsEnable[6]" = "1" register "SataPortsEnable[7]" = "1" + register "SataPortsHotPlug[0]" = "1" + register "SataPortsHotPlug[1]" = "1" + register "SataPortsHotPlug[2]" = "1" + register "SataPortsHotPlug[3]" = "1" + register "SataPortsHotPlug[4]" = "1" + register "SataPortsHotPlug[5]" = "1" + register "SataPortsHotPlug[6]" = "1" + register "SataPortsHotPlug[7]" = "1" + register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Gerrit-Change-Number: 42804 Gerrit-PatchSet: 1 Gerrit-Owner: Jonas Löffelholz Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: src/soc/intel/cannonlake: add support for sata hotswap
by Jonas Löffelholz (Code Review) 01 Jul '20

01 Jul '20

Jonas Löffelholz has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42803 ) Change subject: src/soc/intel/cannonlake: add support for sata hotswap ...................................................................... src/soc/intel/cannonlake: add support for sata hotswap Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz(a)9elements.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42803/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3ebbc5e..ac523d8 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -147,6 +147,7 @@ uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; uint8_t SataPortsDevSlpResetConfig[8]; + uint8_t SataPortsHotPlug[8]; /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ uint8_t SlpS0WithGbeSupport; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a3b5588..c43d1b2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,6 +177,10 @@ sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + #if CONFIG(SOC_INTEL_COMETLAKE) memcpy(params->SataPortsDevSlpResetConfig, config->SataPortsDevSlpResetConfig, -- To view, visit https://review.coreboot.org/c/coreboot/+/42803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Gerrit-Change-Number: 42803 Gerrit-PatchSet: 1 Gerrit-Owner: Jonas Löffelholz Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: 3rdparty/amd_blobs: Update Picasso PSP files
by Marshall Dawson (Code Review) 01 Jul '20

01 Jul '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42893 ) Change subject: 3rdparty/amd_blobs: Update Picasso PSP files ...................................................................... 3rdparty/amd_blobs: Update Picasso PSP files Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I752804919227c1522374b93e08abee13396b2679 --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/42893/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 5d4d09e..1ac6d42 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 5d4d09e984578d129928b74cab78f78d214609e1 +Subproject commit 1ac6d42bf336af639ae849933cbb818e51b1ffd1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I752804919227c1522374b93e08abee13396b2679 Gerrit-Change-Number: 42893 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/skylake: Update ASL syntax in xhci.asl
by Edward O'Callaghan (Code Review) 01 Jul '20

01 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42898 ) Change subject: soc/intel/skylake: Update ASL syntax in xhci.asl ...................................................................... soc/intel/skylake: Update ASL syntax in xhci.asl Use some defines as well for clarity. Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 19 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/42898/1 diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 5a877d4..2f5d8b2 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -1,5 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define PORTSCN_OFFSET 0x480 +#define PORTSCXUSB3_OFFSET 0x540 + +#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 +#define RO_BITS_OFF_MASK ~0x80FE0012 + /* * USB Port Wake Enable (UPWE) on usb attach/detach * Arg0 - Port Number @@ -8,8 +14,7 @@ */ Method (UPWE, 3, Serialized) { - /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ - Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + Local0 = Arg1 + ((Arg0 - 1) * 0x10) /* Map ((XMEM << 16) + Local0 in PSCR */ OperationRegion (PSCR, SystemMemory, @@ -18,16 +23,16 @@ { PSCT, 32, } - Store(PSCT, Local0) + Local0 = PSCT /* * And port status/control reg with RO and RWS bits * RO bits: 0, 2:3, 10:13, 24, 28:30 * RWS bits: 5:9, 14:16, 25:27 */ - And (Local0, ~0x80FE0012, Local0) + Local0 = Local0 & RO_BITS_OFF_MASK /* Set WCE and WDE bits */ - Or (Local0, 0x6000000, Local0) - Store(Local0, PSCT) + Local0 = Local0 | WAKE_ON_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 } /* @@ -38,20 +43,19 @@ */ Method (UWES, 3, Serialized) { - Store (Arg0, Local0) + Local0 = Arg0 While (One) { FindSetRightBit (Local0, Local1) - If (LEqual (Local1, Zero)) { + If (Local1 == Zero) { Break } UPWE (Local1, Arg1, Arg2) /* * Clear the lowest set bit in Local0 since it was * processed. - * Local0 = Local0 & (Local0 - 1) */ - And (Local0, Subtract (Local0, 1), Local0) + Local0 = Local0 & (Local0 - 1) } } @@ -65,9 +69,9 @@ Method (_DSW, 3) { - Store (Arg0, PMEE) - UWES (And (\U2WE, 0x3FF), 0x480, XMEM) - UWES (And (\U3WE, 0x3F), 0x540, XMEM) + PMEE = Arg0 + UWES ((\U2WE & 0x3FF), PORTSCN_OFFSET, XMEM) + UWES ((\U3WE & 0x3F ), PORTSCXUSB3_OFFSET, XMEM) } Name (_S3D, 3) /* D3 supported in S3 */ @@ -221,11 +225,11 @@ // REV: Revision 0x02 for ACPI 5.0 CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + REV = 0x02 // VISI: Port visibility to user per port CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + VISI = Arg0 Return (PCKG) } -- To view, visit https://review.coreboot.org/c/coreboot/+/42898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f Gerrit-Change-Number: 42898 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4
by John Zhao (Code Review) 01 Jul '20

01 Jul '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42821 ) Change subject: soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4 ...................................................................... soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4 This change adds Platform-Wide _OSC capabilities for native USB4 support. There is Engineering Change Request (ECR) with _OSC addition for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18 as native USB4 support. The OS sets this bit to indicate support for an OSPM-native USB4 Connection Manager which handles USB4 connection events and link management. The OS use the _OSC mechanism and the bit defined in this ECR to obtain configuration and connection management capabilities of USB4 connections. This change also fixs the byte index for the DWord-addressable field CDW3 from the capabilities buffer. BUG=b:140645231 TEST=Check Type C device all ports connection/enumeration with SW CM. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad --- M src/soc/intel/tigerlake/acpi/tcss.asl 1 file changed, 39 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42821/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 3f51ecc..7434a54 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -139,29 +139,46 @@ Method (_OSC, 4, Serialized) { - /* - * Operating System Capabilities for USB4 - * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} - * Arg1: Revision ID = 1 - * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 - * Arg3: DWORD capabilities buffer: - * First DWORD: The standard definition bits are used to return errors. - * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. - * Third DWORD: OSPM control field for USB4. - * bit 0: USB tunneling - * bit 1: DisplayPort tunneling - * bit 2: PCIe tunneling - * bit 3: Inter-domain USB4 internet protocol - * bit 31:4: reserved - * Return: The platform acknowledges the capabilities buffer by returning - * a buffer of DWORD of the same length. Masked/Cleared bits in the - * control field indicate that the platform does not permit OSPM - * control of the respectively capabilities or features. - */ - Name (CTRL, 0) /* Control field value */ CreateDWordField (Arg3, 0, CDW1) - If (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { - CreateDWordField (Arg3, 2, CDW3) + If (Arg0 == ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")) { + /* Platform-Wide _OSC Capabilities + * Arg0: UUID = {0811B06E-4A27-44F9-8D60-3CBBC22E7B48} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arge3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: See ACPI specification Platform-Wide _OSC Capabilities + * DWORD2 table for Bits 0-17. Bit 18 is newly defined as native USB4 + * support. The OS sets this bit to indicate support for an OSPM-native + * USB4 Connection Manager which handles USB4 connection events and + * link management. + */ + If (Arg1 != REVISION) { + CDW1 |= UNRECOGNIZED_REVISION + } + Return (Arg3) + } ElseIf (Arg0 == ToUUID("23A0D13A-26AB-486C-9C5F-0FFA525A575A")) { + /* + * Operating System Capabilities for USB4 + * Arg0: UUID = {23A0D13A-26AB-486C-9C5F-0FFA525A575A} + * Arg1: Revision ID = 1 + * Arg2: Count of entries (DWORD) in Arg3 (Integer): 3 + * Arg3: DWORD capabilities buffer: + * First DWORD: The standard definition bits are used to return errors. + * Second DWORD: OSPM support field for USB4, bits [31:0] reserved. + * Third DWORD: OSPM control field for USB4. + * bit 0: USB tunneling + * bit 1: DisplayPort tunneling + * bit 2: PCIe tunneling + * bit 3: Inter-domain USB4 internet protocol + * bit 31:4: reserved + * Return: The platform acknowledges the capabilities buffer by + * returning a buffer of DWORD of the same length. Masked/Cleared bits + * in the control field indicate that the platform does not permit OSPM + * control of the respectively capabilities or features. + */ + Name (CTRL, 0) /* Control field value */ + CreateDWordField (Arg3, 8, CDW3) CTRL = CDW3 If (Arg1 != REVISION_ID) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad Gerrit-Change-Number: 42821 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Fix a typo in tests/lib/Makefile.inc
by Anna Karas (Code Review) 01 Jul '20

01 Jul '20

Anna Karas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42312 ) Change subject: tests: Fix a typo in tests/lib/Makefile.inc ...................................................................... tests: Fix a typo in tests/lib/Makefile.inc Fix a typo in a comment in Makefile.inc. Signed-off-by: Anna Karas <aka(a)semihalf.com> Change-Id: I236b040a83700bcd34d99db61e5dad0ff7abb28c --- M tests/lib/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/42312/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 565bb31..61f99bf 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -# object filest should be under build/tests/ build/test/src/ build/test/run/ +# object files should be under build/tests/ build/test/src/ build/test/run/ # two examples - first should be simply string.c, second should use -wrap tests-y += string-test -- To view, visit https://review.coreboot.org/c/coreboot/+/42312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I236b040a83700bcd34d99db61e5dad0ff7abb28c Gerrit-Change-Number: 42312 Gerrit-PatchSet: 1 Gerrit-Owner: Anna Karas <aka(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: set GPIOs to wake-up from touchpad
by Furquan Shaikh (Code Review) 01 Jul '20

01 Jul '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42726 to review the following change. Change subject: mb/google/zork: set GPIOs to wake-up from touchpad ...................................................................... mb/google/zork: set GPIOs to wake-up from touchpad This allows the system to wake from the touchpad if the touchpad is powered in S3. BUG=b:154676993 TEST=enter S3 with the follow-on patch and verify that the system can wake from S3. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I222f1de9a25a8aa24d56fde09a487cbf3737446f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Tested-by: Furquan Shaikh <furquan(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/42726/1 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 50c842b..d8a3714 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -101,6 +101,7 @@ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_UP, EDGE_LOW, S3_S4_S5), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* EN_PWR_TOUCHPAD */ @@ -110,8 +111,8 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ PAD_GPI(GPIO_9, PULL_UP), + PAD_WAKE(GPIO_9, PULL_UP, EDGE_LOW, S3_S4_S5), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* EC_IN_RW_OD */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index d3f7ae3..bac5333 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -97,6 +97,7 @@ PAD_NF(GPIO_2, WAKE_L, PULL_UP), /* PEN_DETECT_ODL */ PAD_GPI(GPIO_4, PULL_UP), + PAD_WAKE(GPIO_4, PULL_UP, EDGE_LOW, S3_S4_S5), /* PEN_POWER_EN - Enabled*/ PAD_GPO(GPIO_5, HIGH), /* FPMCU_INT_L */ @@ -107,8 +108,8 @@ /* I2S_LRCLK - Bit banged in depthcharge */ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ - /* TODO: Make sure driver sets as wake source */ PAD_GPI(GPIO_9, PULL_UP), + PAD_WAKE(GPIO_9, PULL_UP, EDGE_LOW, S3_S4_S5), /* S0iX SLP - (unused - goes to EC & FPMCU */ PAD_GPI(GPIO_10, PULL_UP), /* FPMCU_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I222f1de9a25a8aa24d56fde09a487cbf3737446f Gerrit-Change-Number: 42726 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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