coreboot-gerrit June 2020

coreboot-gerrit@coreboot.org

1 participants
2826 discussions

Change in coreboot[master]: mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dt
by Edward O'Callaghan (Code Review) 30 Jun '20

30 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42714 ) Change subject: mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dt ...................................................................... mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dt BUG=b:159187889 BRANCH=none TEST=none Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/mainboard/google/hatch/variants/puff/overridetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42714/1 diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index ededac4..d675954 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -84,6 +84,18 @@ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/42714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13626a236f1b7385208c4181150f094cbda490ed Gerrit-Change-Number: 42714 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: soc/intel/cannonlake: Add UWES ASL into xhci.asl
by Edward O'Callaghan (Code Review) 30 Jun '20

30 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42737 ) Change subject: soc/intel/cannonlake: Add UWES ASL into xhci.asl ...................................................................... soc/intel/cannonlake: Add UWES ASL into xhci.asl Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`. This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:159187889 BRANCH=none TEST=none Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M src/soc/intel/cannonlake/acpi/xhci.asl 1 file changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42737/1 diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index d5187e6..fabe1f1 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -2,6 +2,61 @@ #include <soc/gpe.h> +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ + Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, + Add (ShiftLeft (Arg2, 16), Local0), 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Store(PSCT, Local0) + /* + * And port status/control reg with RO and RWS bits + * RO bits: 0, 2:3, 10:13, 24, 28:30 + * RWS bits: 5:9, 14:16, 25:27 + */ + And (Local0, ~0x80FE0012, Local0) + /* Set WCE and WDE bits */ + Or (Local0, 0x6000000, Local0) + Store(Local0, PSCT) +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Store (Arg0, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + * Local0 = Local0 & (Local0 - 1) + */ + And (Local0, Subtract (Local0, 1), Local0) + } +} + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -10,6 +65,14 @@ Name (_PRW, Package () { GPE0_PME_B0, 3 }) + Name (_DSW, 3) + { + Store (Arg0, PMEE) + UWES (And (\U2WE, 0x3FF), 0x480, XMEM) + UWES (And (\U3WE, 0x3F ), 0x540, XMEM) + + } + Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Gerrit-Change-Number: 42737 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/google/volteer: Add support for passive USB-C daughterboard
by Caveh Jalali (Code Review) 30 Jun '20

30 Jun '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42905 ) Change subject: mb/google/volteer: Add support for passive USB-C daughterboard ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… PS1, Line 159: device generic 1 on : probe DB_USB USB4_GEN2 : probe DB_USB USB3_ACTIVE : probe DB_USB USB4_GEN3 : probe DB_USB USB3_NO_A : end : end : chip drivers/intel/pmc_mux/con : register "usb2_port_number" = "4" : register "usb3_port_number" = "2" : # SBU & HSL follow CC : device generic 1 on : probe DB_USB USB3_PASSIVE : end > Hmm, this might start to get a little repetitive (having to re-declare each device)... […] i'm open to suggestions - don't you then have to walk the device tree and "fix" the sbu_orientation? some simple declarative duplication at this level seems preferable to actual code. also, from what i've seen so far, most variants have fixed configurations for audio and usb, so the need for "probe" may be very limited. -- To view, visit https://review.coreboot.org/c/coreboot/+/42905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Gerrit-Change-Number: 42905 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Jun 2020 20:54:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI F...
by Christian Walter (Code Review) 30 Jun '20

30 Jun '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40308 ) Change subject: drivers/ocp/dmi: Add OCP_DMI driver for populating SMBIOS from IPMI FRU data ...................................................................... Patch Set 51: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/40308/51/src/drivers/ocp/dmi/smbio… File src/drivers/ocp/dmi/smbios.c: https://review.coreboot.org/c/coreboot/+/40308/51/src/drivers/ocp/dmi/smbio… PS51, Line 176: *p+ Why do we double null terminate here? -- To view, visit https://review.coreboot.org/c/coreboot/+/40308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c958dfad83216cd12545760a19d205efc2515b Gerrit-Change-Number: 40308 Gerrit-PatchSet: 51 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 20:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 30 Jun '20

30 Jun '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42733 to look at the new patch set (#6). Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... [WIP] sb/amd/pi/hudson: Fixes for common GPIO API Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Kconfig A src/southbridge/amd/pi/hudson/soc/gpio.h A src/southbridge/amd/pi/hudson/soc/smi.h M src/vendorcode/amd/pi/Makefile.inc 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42733/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Angel Pons (Code Review) 30 Jun '20

30 Jun '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 4: Code-Review+1 (13 comments) Reviewing board ports for shiny new hardware makes me jealous https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 2: /* This file is part of the coreboot project. */ We dropped these lines (apply to all files) https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 16: Zero 0, please https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 21: One 1, please https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 17: Method (_STA, 0, NotSerialized) : { : Return (0x0F) : } Not needed: https://review.coreboot.org/c/coreboot/+/35523/122/src/mainboard/acer/aspir… https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 24: #include "thermal.asl" I'd include this from "dsdt.asl" and rename the file to "ac.asl" https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/acpi/thermal.asl: https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 42: nit: Enable ACPI debugging in Linux, and add these two lines to every fan's _STA method right before returning: Debug = "FN0x._STA" Debug = Local1 Then drop all fan devices where its value is zero, and let me know if there are any fans where _STA is non-zero https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 115: Device (FAN1) Two fans? https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 159: Device (FAN2) THREE fans? https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 203: Device (FAN3) FOUR??? https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 247: Device (FAN4) Are you sure this isn't a drone? https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 166: Enable I don't think so https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 167: register "deep_s3_enable_ac" = "0" : register "deep_s3_enable_dc" = "0" : register "deep_s5_enable_ac" = "0" : register "deep_s5_enable_dc" = "0" Those default to zero already and make no sense with "deep_sx_config" = "0" https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/dsdt.asl: https://review.coreboot.org/c/coreboot/+/40278/4/src/mainboard/purism/libre… PS4, Line 26: Scope (\_SB.PCI0.LPCB) Move this scope inside "acpi/ec.asl" for clarity? -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 19:31:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/common/gpio: Use gpio_setbits32()
by Aaron Durbin (Code Review) 30 Jun '20

30 Jun '20

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42688 ) Change subject: soc/amd/common/gpio: Use gpio_setbits32() ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4413d113dff550900348a44f71b949b7547a9cfc Gerrit-Change-Number: 42688 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 19:20:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: jasperlake: enable tcc_offset functionality
by Sumeet R Pawnikar (Code Review) 30 Jun '20

30 Jun '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42515 ) Change subject: jasperlake: enable tcc_offset functionality ...................................................................... jasperlake: enable tcc_offset functionality This enables Thermal Control Circuit (TCC) activation feature to set tcc_offset value to new value as 10 degree Celcius in devicetree. BUG=None BRANCH=None TEST=Built for dedede platform and verified the MSR value Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/fsp_params.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/42515/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4a68444..b8071fb 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,6 +155,8 @@ # Enable processor thermal control register "Device4Enable" = "1" + register "tcc_offset" = "10" # TCC of 90C + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index ed9cfe7..3112e0a 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -210,4 +210,7 @@ { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); + + /* Thermal throttle activation offset */ + configure_thermal_target(); } diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 75e1c64..6493fd5 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -190,6 +190,9 @@ params->Device4Enable = config->Device4Enable; + /* Set TccActivationOffset */ + params->TccActivationOffset = config->tcc_offset; + /* eMMC configuration */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); if (!dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6 Gerrit-Change-Number: 42515 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/volteer: Add support for passive USB-C daughterboard
by Tim Wawrzynczak (Code Review) 30 Jun '20

30 Jun '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42905 ) Change subject: mb/google/volteer: Add support for passive USB-C daughterboard ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/42905/1/src/mainboard/google/volte… PS1, Line 159: device generic 1 on : probe DB_USB USB4_GEN2 : probe DB_USB USB3_ACTIVE : probe DB_USB USB4_GEN3 : probe DB_USB USB3_NO_A : end : end : chip drivers/intel/pmc_mux/con : register "usb2_port_number" = "4" : register "usb3_port_number" = "2" : # SBU & HSL follow CC : device generic 1 on : probe DB_USB USB3_PASSIVE : end Hmm, this might start to get a little repetitive (having to re-declare each device)... what do you think about using the direct fw_config probe interface, fw_config_probe() in a variant.c or similar ? -- To view, visit https://review.coreboot.org/c/coreboot/+/42905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Gerrit-Change-Number: 42905 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Jun 2020 18:54:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 30 Jun '20

30 Jun '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 25: > Patch Set 25: Code-Review+1 > > (1 comment) > > > Patch Set 25: > > > > > Patch Set 25: > > > > > > What's the status of this patchset? > > > > The whole patch chain waits for review and testing. As there was no feedback in month I dropped the interest in this. It was successfully tested on QEMU and Intel Nehalem platforms, so it's definitely working on blob free platforms. > > With the patches you have landed, is it possible to enable paging on x86_32? Would be nice to have it to catch stack overflows or writes to random sections of memory. You can already enable paging on x86_32, but those page tables are different from x86_64 page tables. Those features aren't used in coreboot, but could be added. -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 25 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 30 Jun 2020 18:44:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2020